Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[1]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[2]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[3]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[4]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[5]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[6]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[7]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[8]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[9]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[10]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[11]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[12]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[13]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[14]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[15]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[16]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[17]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[18]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[19]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[20]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[21]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[22]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[23]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[24]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[25]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[26]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[27]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[28]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[29]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[30]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[31]	14808040	1			T20	357		T21	1		T22	333

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279454059

1

T20

7967

T21

32

T22

6598

auto[1]

194403221

1

T20

3457

T22

4058

T23

40798

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

379374062

1

T20

7076

T21

32

T22

8062

auto[1]

94483218

1

T20

4348

T22

2594

T25

98

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351124662

1

T20

7083

T21

32

T22

8111

auto[1]

122732618

1

T20

4341

T22

2545

T25

1135

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5417556	1			T20	109		T21	1		T22	144
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4077087	1			T20	38		T22	80		T23	1290
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1487844	1			T20	70		T22	29		T28	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1829619	1			T20	74		T22	72		T25	39
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	532158	1			T25	9		T28	142		T29	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1463776	1			T20	66		T22	8		T25	6
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5415054	1			T20	111		T21	1		T22	138
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4067273	1			T20	35		T22	92		T23	1247
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1487250	1			T20	56		T22	47		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1832767	1			T20	82		T22	18		T25	9
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	534302	1			T25	3		T28	36		T29	8
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1471394	1			T20	73		T22	38		T25	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5409915	1			T20	124		T21	1		T22	109
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4074788	1			T20	50		T22	94		T23	1287
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1484366	1			T20	48		T22	38		T25	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1836634	1			T20	55		T22	38		T25	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	534659	1			T28	70		T29	7		T30	5028
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1467678	1			T20	80		T22	54		T28	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5418799	1			T20	107		T21	1		T22	119
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4060899	1			T20	43		T22	92		T23	1271
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1484247	1			T20	59		T22	34		T28	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1832092	1			T20	70		T22	38		T25	23
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	536321	1			T25	7		T28	88		T29	6
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1475682	1			T20	78		T22	50		T28	16
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5401300	1			T20	115		T21	1		T22	122
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4082480	1			T20	45		T22	86		T23	1315
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1491748	1			T20	53		T22	53		T28	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1828977	1			T20	56		T22	36		T25	31
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	531900	1			T25	10		T28	107		T29	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1471635	1			T20	88		T22	36		T28	8
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5418567	1			T20	136		T21	1		T22	134
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4064438	1			T20	40		T22	81		T23	1254
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1487111	1			T20	70		T22	42		T28	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1835686	1			T20	72		T22	22		T25	50
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	532174	1			T25	9		T28	10		T29	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1470064	1			T20	39		T22	54		T25	6
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5408817	1			T20	116		T21	1		T22	143
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4078060	1			T20	40		T22	85		T23	1276
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1485792	1			T20	81		T22	25		T28	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1835004	1			T20	60		T22	32		T25	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	529680	1			T25	1		T28	18		T29	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1470687	1			T20	60		T22	48		T29	17
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5410582	1			T20	112		T21	1		T22	127
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4065664	1			T20	39		T22	84		T23	1228
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1485639	1			T20	46		T22	38		T25	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1834350	1			T20	86		T22	42		T25	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	534588	1			T28	36		T29	12		T30	5439
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1477217	1			T20	74		T22	42		T28	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5414093	1			T20	127		T21	1		T22	141
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4075630	1			T20	33		T22	87		T23	1276
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1489741	1			T20	78		T22	41		T28	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1824079	1			T20	52		T22	28		T25	33
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	534371	1			T25	16		T28	78		T29	9
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1470126	1			T20	67		T22	36		T25	6
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5402798	1			T20	119		T21	1		T22	96
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4079377	1			T20	35		T22	98		T23	1288
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1485054	1			T20	68		T22	44		T25	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1834008	1			T20	63		T22	55		T25	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	535065	1			T28	83		T29	3		T30	5232
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1471738	1			T20	72		T22	40		T28	8
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5412847	1			T20	112		T21	1		T22	123
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4077810	1			T20	38		T22	89		T23	1261
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1486609	1			T20	63		T22	57		T28	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1831549	1			T20	62		T22	32		T25	38
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	533563	1			T25	9		T28	106		T29	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1465662	1			T20	82		T22	32		T25	4
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5421301	1			T20	119		T21	1		T22	130
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4066074	1			T20	39		T22	86		T23	1303
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1490408	1			T20	79		T22	30		T28	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1832121	1			T20	62		T22	32		T25	43
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	531865	1			T25	12		T28	83		T29	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1466271	1			T20	58		T22	55		T25	4
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5408624	1			T20	95		T21	1		T22	122
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4075896	1			T20	49		T22	79		T23	1263
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1489139	1			T20	62		T22	36		T28	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1829394	1			T20	97		T22	44		T25	44
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	531029	1			T25	6		T28	65		T29	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1473958	1			T20	54		T22	52		T25	4
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5411043	1			T20	101		T21	1		T22	118
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4069885	1			T20	31		T22	102		T23	1240
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1485820	1			T20	66		T22	42		T25	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1834808	1			T20	81		T22	33		T25	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	530696	1			T25	4		T28	81		T29	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1475788	1			T20	78		T22	38		T28	8
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5408940	1			T20	106		T21	1		T22	122
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4072297	1			T20	40		T22	79		T23	1283
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1489285	1			T20	72		T22	44		T28	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1830335	1			T20	71		T22	36		T25	40
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	534891	1			T25	6		T28	87		T29	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1472292	1			T20	68		T22	52		T25	4
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5404007	1			T20	123		T21	1		T22	104
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4074368	1			T20	35		T22	93		T23	1304
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1486340	1			T20	76		T22	20		T28	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1832174	1			T20	63		T22	84		T25	26
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	536037	1			T25	5		T28	67		T29	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1475114	1			T20	60		T22	32		T28	6
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5413116	1			T20	120		T21	1		T22	114
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4077507	1			T20	41		T22	89		T23	1257
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1480995	1			T20	80		T22	46		T28	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1830613	1			T20	52		T22	38		T25	42
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	533893	1			T25	12		T28	29		T29	7
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1471916	1			T20	64		T22	46		T29	21
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5424179	1			T20	97		T21	1		T22	135
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4071063	1			T20	39		T22	76		T23	1280
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1477777	1			T20	93		T22	58		T25	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1830846	1			T20	52		T22	34		T25	24
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	533915	1			T25	4		T28	71		T29	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1470260	1			T20	76		T22	30		T25	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5400362	1			T20	102		T21	1		T22	120
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4085918	1			T20	43		T22	90		T23	1299
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1472844	1			T20	80		T22	36		T28	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1843772	1			T20	60		T22	46		T25	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	533647	1			T28	67		T29	4		T30	5321
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1471497	1			T20	72		T22	41		T29	29
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5419478	1			T20	106		T21	1		T22	150
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4073218	1			T20	46		T22	76		T23	1238
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1482223	1			T20	69		T22	40		T25	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1834983	1			T20	72		T22	31		T25	14
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	533420	1			T25	5		T28	85		T29	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1464718	1			T20	64		T22	36		T25	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5423059	1			T20	137		T21	1		T22	151
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4063743	1			T20	39		T22	73		T23	1274
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1483252	1			T20	53		T22	30		T25	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1835625	1			T20	76		T22	41		T25	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	533911	1			T25	13		T28	74		T29	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1468450	1			T20	52		T22	38		T25	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5423242	1			T20	136		T21	1		T22	143
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4064938	1			T20	44		T22	72		T23	1270
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1480287	1			T20	73		T22	62		T28	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1841011	1			T20	60		T22	22		T25	30
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	533925	1			T25	12		T28	137		T30	5122
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1464637	1			T20	44		T22	34		T25	4
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5417691	1			T20	93		T21	1		T22	124
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4077593	1			T20	41		T22	84		T23	1282
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1482161	1			T20	64		T22	58		T25	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1831559	1			T20	71		T22	25		T25	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	533169	1			T28	60		T29	2		T30	5259
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1465867	1			T20	88		T22	42		T28	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5416431	1			T20	110		T21	1		T22	118
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4078927	1			T20	43		T22	88		T23	1257
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1478109	1			T20	76		T22	48		T28	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1836869	1			T20	72		T22	51		T25	26
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	533235	1			T25	3		T28	56		T29	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1464469	1			T20	56		T22	28		T28	4
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5420690	1			T20	120		T21	1		T22	142
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4075198	1			T20	40		T22	85		T23	1263
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1472559	1			T20	58		T22	26		T29	22
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1840151	1			T20	73		T22	38		T25	42
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	534475	1			T25	7		T28	126		T29	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1464967	1			T20	66		T22	42		T25	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5417208	1			T20	103		T21	1		T22	123
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4075012	1			T20	33		T22	86		T23	1311
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1479533	1			T20	58		T22	16		T25	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1838917	1			T20	93		T22	64		T25	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	531362	1			T25	4		T28	86		T29	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1466008	1			T20	70		T22	44		T28	6
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5416280	1			T20	116		T21	1		T22	134
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4073972	1			T20	38		T22	77		T23	1249
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1481577	1			T20	75		T22	38		T28	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1833823	1			T20	62		T22	34		T25	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	535463	1			T25	8		T28	81		T29	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1466925	1			T20	66		T22	50		T28	10
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5418368	1			T20	104		T21	1		T22	122
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4081040	1			T20	39		T22	94		T23	1264
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1488239	1			T20	58		T22	34		T28	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1827020	1			T20	62		T22	41		T25	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	530211	1			T25	9		T28	54		T29	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1463162	1			T20	94		T22	42		T25	4
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5429524	1			T20	118		T21	1		T22	106
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4070928	1			T20	42		T22	94		T23	1330
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1479546	1			T20	54		T22	38		T28	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1832114	1			T20	76		T22	41		T25	44
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	531058	1			T25	10		T28	92		T30	5470
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1464870	1			T20	67		T22	54		T25	4
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5425703	1			T20	106		T21	1		T22	133
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4063897	1			T20	42		T22	95		T23	1286
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1481508	1			T20	86		T22	45		T25	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1834880	1			T20	52		T22	24		T25	32
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	534237	1			T25	5		T28	23		T30	5221
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1467815	1			T20	71		T22	36		T25	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5417289	1			T20	112		T21	1		T22	144
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4079558	1			T20	40		T22	78		T23	1256
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1481344	1			T20	62		T22	40		T25	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1836523	1			T20	76		T22	26		T25	27
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	530583	1			T25	6		T28	81		T29	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1462743	1			T20	67		T22	45		T25	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5432655	1			T20	118		T21	1		T22	138
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4067416	1			T20	41		T22	79		T23	1296
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1484843	1			T20	86		T22	44		T28	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1829048	1			T20	50		T22	32		T25	36
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	531436	1			T25	6		T28	111		T29	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1462642	1			T20	62		T22	40		T28	12

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal