Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[1]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[2]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[3]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[4]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[5]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[6]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[7]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[8]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[9]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[10]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[11]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[12]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[13]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[14]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[15]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[16]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[17]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[18]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[19]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[20]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[21]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[22]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[23]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[24]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[25]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[26]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[27]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[28]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[29]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[30]	14808040	1			T20	357		T21	1		T22	333
bins_for_gpio_bits[31]	14808040	1			T20	357		T21	1		T22	333

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279454059

1

T20

7967

T21

32

T22

6598

auto[1]

194403221

1

T20

3457

T22

4058

T23

40798

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279448500

1

T20

7961

T21

32

T22

6595

auto[1]

194408780

1

T20

3463

T22

4061

T23

40798

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8471323	1			T20	234		T21	1		T22	241
bins_for_gpio_bits[0]	auto[0]	auto[1]	263519	1			T20	19		T22	4		T25	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	263696	1			T20	19		T22	4		T25	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	5809502	1			T20	85		T22	84		T23	1290
bins_for_gpio_bits[1]	auto[0]	auto[0]	8471193	1			T20	230		T21	1		T22	194
bins_for_gpio_bits[1]	auto[0]	auto[1]	263701	1			T20	18		T22	9		T25	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	263878	1			T20	19		T22	9		T25	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5809268	1			T20	90		T22	121		T23	1247
bins_for_gpio_bits[2]	auto[0]	auto[0]	8467685	1			T20	213		T21	1		T22	174
bins_for_gpio_bits[2]	auto[0]	auto[1]	263064	1			T20	14		T22	11		T28	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	263230	1			T20	14		T22	11		T28	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	5814061	1			T20	116		T22	137		T23	1287
bins_for_gpio_bits[3]	auto[0]	auto[0]	8470974	1			T20	214		T21	1		T22	180
bins_for_gpio_bits[3]	auto[0]	auto[1]	263994	1			T20	22		T22	11		T28	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	264164	1			T20	22		T22	11		T28	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	5808908	1			T20	99		T22	131		T23	1271
bins_for_gpio_bits[4]	auto[0]	auto[0]	8458081	1			T20	208		T21	1		T22	201
bins_for_gpio_bits[4]	auto[0]	auto[1]	263769	1			T20	16		T22	10		T28	3
bins_for_gpio_bits[4]	auto[1]	auto[0]	263944	1			T20	16		T22	10		T28	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	5822246	1			T20	117		T22	112		T23	1315
bins_for_gpio_bits[5]	auto[0]	auto[0]	8477437	1			T20	262		T21	1		T22	188
bins_for_gpio_bits[5]	auto[0]	auto[1]	263725	1			T20	15		T22	10		T25	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	263927	1			T20	16		T22	10		T25	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	5802951	1			T20	64		T22	125		T23	1254
bins_for_gpio_bits[6]	auto[0]	auto[0]	8465324	1			T20	240		T21	1		T22	190
bins_for_gpio_bits[6]	auto[0]	auto[1]	264124	1			T20	17		T22	10		T28	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	264289	1			T20	17		T22	10		T28	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	5814303	1			T20	83		T22	123		T23	1276
bins_for_gpio_bits[7]	auto[0]	auto[0]	8466244	1			T20	226		T21	1		T22	199
bins_for_gpio_bits[7]	auto[0]	auto[1]	264169	1			T20	18		T22	8		T28	5
bins_for_gpio_bits[7]	auto[1]	auto[0]	264327	1			T20	18		T22	8		T28	5
bins_for_gpio_bits[7]	auto[1]	auto[1]	5813300	1			T20	95		T22	118		T23	1228
bins_for_gpio_bits[8]	auto[0]	auto[0]	8464145	1			T20	239		T21	1		T22	201
bins_for_gpio_bits[8]	auto[0]	auto[1]	263617	1			T20	17		T22	9		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	263768	1			T20	18		T22	9		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	5816510	1			T20	83		T22	114		T23	1276
bins_for_gpio_bits[9]	auto[0]	auto[0]	8457480	1			T20	228		T21	1		T22	182
bins_for_gpio_bits[9]	auto[0]	auto[1]	264191	1			T20	22		T22	13		T28	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	264380	1			T20	22		T22	13		T28	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5821989	1			T20	85		T22	125		T23	1288
bins_for_gpio_bits[10]	auto[0]	auto[0]	8467892	1			T20	215		T21	1		T22	201
bins_for_gpio_bits[10]	auto[0]	auto[1]	262947	1			T20	22		T22	11		T25	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	263113	1			T20	22		T22	11		T25	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	5814088	1			T20	98		T22	110		T23	1261
bins_for_gpio_bits[11]	auto[0]	auto[0]	8480064	1			T20	243		T21	1		T22	180
bins_for_gpio_bits[11]	auto[0]	auto[1]	263547	1			T20	17		T22	11		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	263766	1			T20	17		T22	12		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5800663	1			T20	80		T22	130		T23	1303
bins_for_gpio_bits[12]	auto[0]	auto[0]	8462846	1			T20	240		T21	1		T22	189
bins_for_gpio_bits[12]	auto[0]	auto[1]	264124	1			T20	14		T22	13		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	264311	1			T20	14		T22	13		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5816759	1			T20	89		T22	118		T23	1263
bins_for_gpio_bits[13]	auto[0]	auto[0]	8467038	1			T20	229		T21	1		T22	183
bins_for_gpio_bits[13]	auto[0]	auto[1]	264480	1			T20	19		T22	10		T28	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	264633	1			T20	19		T22	10		T28	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	5811889	1			T20	90		T22	130		T23	1240
bins_for_gpio_bits[14]	auto[0]	auto[0]	8463899	1			T20	230		T21	1		T22	189
bins_for_gpio_bits[14]	auto[0]	auto[1]	264506	1			T20	19		T22	13		T25	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	264661	1			T20	19		T22	13		T25	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5814974	1			T20	89		T22	118		T23	1283
bins_for_gpio_bits[15]	auto[0]	auto[0]	8459084	1			T20	242		T21	1		T22	199
bins_for_gpio_bits[15]	auto[0]	auto[1]	263251	1			T20	20		T22	9		T28	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	263437	1			T20	20		T22	9		T28	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	5822268	1			T20	75		T22	116		T23	1304
bins_for_gpio_bits[16]	auto[0]	auto[0]	8460937	1			T20	236		T21	1		T22	187
bins_for_gpio_bits[16]	auto[0]	auto[1]	263618	1			T20	16		T22	11		T28	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	263787	1			T20	16		T22	11		T28	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5819698	1			T20	89		T22	124		T23	1257
bins_for_gpio_bits[17]	auto[0]	auto[0]	8469218	1			T20	222		T21	1		T22	220
bins_for_gpio_bits[17]	auto[0]	auto[1]	263421	1			T20	20		T22	7		T25	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	263584	1			T20	20		T22	7		T25	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5811817	1			T20	95		T22	99		T23	1280
bins_for_gpio_bits[18]	auto[0]	auto[0]	8452328	1			T20	225		T21	1		T22	191
bins_for_gpio_bits[18]	auto[0]	auto[1]	264459	1			T20	17		T22	10		T28	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	264650	1			T20	17		T22	11		T28	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	5826603	1			T20	98		T22	121		T23	1299
bins_for_gpio_bits[19]	auto[0]	auto[0]	8473157	1			T20	232		T21	1		T22	214
bins_for_gpio_bits[19]	auto[0]	auto[1]	263348	1			T20	15		T22	7		T25	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	263527	1			T20	15		T22	7		T25	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	5808008	1			T20	95		T22	105		T23	1238
bins_for_gpio_bits[20]	auto[0]	auto[0]	8477687	1			T20	251		T21	1		T22	211
bins_for_gpio_bits[20]	auto[0]	auto[1]	264018	1			T20	15		T22	11		T25	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	264249	1			T20	15		T22	11		T25	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	5802086	1			T20	76		T22	100		T23	1274
bins_for_gpio_bits[21]	auto[0]	auto[0]	8480787	1			T20	256		T21	1		T22	216
bins_for_gpio_bits[21]	auto[0]	auto[1]	263595	1			T20	13		T22	11		T25	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	263753	1			T20	13		T22	11		T25	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5799905	1			T20	75		T22	95		T23	1270
bins_for_gpio_bits[22]	auto[0]	auto[0]	8467281	1			T20	210		T21	1		T22	196
bins_for_gpio_bits[22]	auto[0]	auto[1]	263952	1			T20	18		T22	11		T28	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	264130	1			T20	18		T22	11		T28	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5812677	1			T20	111		T22	115		T23	1282
bins_for_gpio_bits[23]	auto[0]	auto[0]	8467615	1			T20	240		T21	1		T22	206
bins_for_gpio_bits[23]	auto[0]	auto[1]	263628	1			T20	18		T22	11		T28	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	263794	1			T20	18		T22	11		T28	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	5813003	1			T20	81		T22	105		T23	1257
bins_for_gpio_bits[24]	auto[0]	auto[0]	8469744	1			T20	232		T21	1		T22	199
bins_for_gpio_bits[24]	auto[0]	auto[1]	263512	1			T20	19		T22	7		T25	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	263656	1			T20	19		T22	7		T25	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	5811128	1			T20	87		T22	120		T23	1263
bins_for_gpio_bits[25]	auto[0]	auto[0]	8471752	1			T20	235		T21	1		T22	193
bins_for_gpio_bits[25]	auto[0]	auto[1]	263744	1			T20	19		T22	10		T28	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	263906	1			T20	19		T22	10		T28	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	5808638	1			T20	84		T22	120		T23	1311
bins_for_gpio_bits[26]	auto[0]	auto[0]	8467343	1			T20	238		T21	1		T22	193
bins_for_gpio_bits[26]	auto[0]	auto[1]	264151	1			T20	15		T22	13		T28	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	264337	1			T20	15		T22	13		T28	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5812209	1			T20	89		T22	114		T23	1249
bins_for_gpio_bits[27]	auto[0]	auto[0]	8469667	1			T20	205		T21	1		T22	187
bins_for_gpio_bits[27]	auto[0]	auto[1]	263797	1			T20	19		T22	10		T25	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	263960	1			T20	19		T22	10		T25	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5810616	1			T20	114		T22	126		T23	1264
bins_for_gpio_bits[28]	auto[0]	auto[0]	8477530	1			T20	231		T21	1		T22	173
bins_for_gpio_bits[28]	auto[0]	auto[1]	263490	1			T20	16		T22	12		T25	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	263654	1			T20	17		T22	12		T25	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	5803366	1			T20	93		T22	136		T23	1330
bins_for_gpio_bits[29]	auto[0]	auto[0]	8477730	1			T20	225		T21	1		T22	193
bins_for_gpio_bits[29]	auto[0]	auto[1]	264177	1			T20	18		T22	9		T25	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	264361	1			T20	19		T22	9		T25	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5801772	1			T20	95		T22	122		T23	1286
bins_for_gpio_bits[30]	auto[0]	auto[0]	8470916	1			T20	232		T21	1		T22	201
bins_for_gpio_bits[30]	auto[0]	auto[1]	264104	1			T20	17		T22	8		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	264240	1			T20	18		T22	9		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5808780	1			T20	90		T22	115		T23	1256
bins_for_gpio_bits[31]	auto[0]	auto[0]	8482815	1			T20	239		T21	1		T22	204
bins_for_gpio_bits[31]	auto[0]	auto[1]	263542	1			T20	15		T22	10		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	263731	1			T20	15		T22	10		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5797952	1			T20	88		T22	109		T23	1296