Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8538748 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6489727 |
1 |
|
|
T23 |
1714 |
|
T30 |
233121 |
|
T43 |
178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14197825 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
830650 |
1 |
|
|
T23 |
294 |
|
T30 |
30921 |
|
T43 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8558647 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6469828 |
1 |
|
|
T23 |
1482 |
|
T30 |
236219 |
|
T43 |
186 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2823121 |
1 |
|
|
T23 |
657 |
|
T30 |
104850 |
|
T43 |
88 |
| auto[1] |
auto[0] |
auto[1] |
415287 |
1 |
|
|
T23 |
155 |
|
T30 |
15939 |
|
T43 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2816057 |
1 |
|
|
T23 |
531 |
|
T30 |
100448 |
|
T43 |
83 |
| auto[1] |
auto[1] |
auto[1] |
415363 |
1 |
|
|
T23 |
139 |
|
T30 |
14982 |
|
T43 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8552714 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6475761 |
1 |
|
|
T23 |
1478 |
|
T30 |
234861 |
|
T43 |
221 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14199286 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
829189 |
1 |
|
|
T23 |
293 |
|
T30 |
30707 |
|
T43 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8574279 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6454196 |
1 |
|
|
T23 |
1573 |
|
T30 |
236451 |
|
T43 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2820033 |
1 |
|
|
T23 |
749 |
|
T30 |
101600 |
|
T43 |
24 |
| auto[1] |
auto[0] |
auto[1] |
415702 |
1 |
|
|
T23 |
167 |
|
T30 |
15352 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2804974 |
1 |
|
|
T23 |
531 |
|
T30 |
104144 |
|
T43 |
70 |
| auto[1] |
auto[1] |
auto[1] |
413487 |
1 |
|
|
T23 |
126 |
|
T30 |
15355 |
|
T43 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8556470 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6472005 |
1 |
|
|
T23 |
1828 |
|
T30 |
232638 |
|
T43 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14192968 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
835507 |
1 |
|
|
T23 |
351 |
|
T30 |
31148 |
|
T43 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8537041 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6491434 |
1 |
|
|
T23 |
1854 |
|
T30 |
239048 |
|
T43 |
192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2843504 |
1 |
|
|
T23 |
745 |
|
T30 |
105059 |
|
T43 |
64 |
| auto[1] |
auto[0] |
auto[1] |
420071 |
1 |
|
|
T23 |
164 |
|
T30 |
15838 |
|
T43 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2812423 |
1 |
|
|
T23 |
758 |
|
T30 |
102841 |
|
T43 |
110 |
| auto[1] |
auto[1] |
auto[1] |
415436 |
1 |
|
|
T23 |
187 |
|
T30 |
15310 |
|
T43 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8558874 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6469601 |
1 |
|
|
T23 |
1586 |
|
T30 |
234442 |
|
T43 |
152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14196098 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
832377 |
1 |
|
|
T23 |
287 |
|
T30 |
31465 |
|
T43 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8555980 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6472495 |
1 |
|
|
T23 |
1567 |
|
T30 |
238612 |
|
T43 |
140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2823173 |
1 |
|
|
T23 |
705 |
|
T30 |
102695 |
|
T43 |
58 |
| auto[1] |
auto[0] |
auto[1] |
417316 |
1 |
|
|
T23 |
157 |
|
T30 |
15648 |
|
T43 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2816945 |
1 |
|
|
T23 |
575 |
|
T30 |
104452 |
|
T43 |
68 |
| auto[1] |
auto[1] |
auto[1] |
415061 |
1 |
|
|
T23 |
130 |
|
T30 |
15817 |
|
T43 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8554296 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6474179 |
1 |
|
|
T23 |
1724 |
|
T30 |
228407 |
|
T43 |
155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14194897 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
833578 |
1 |
|
|
T23 |
385 |
|
T30 |
30184 |
|
T43 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8544897 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6483578 |
1 |
|
|
T23 |
1945 |
|
T30 |
232194 |
|
T43 |
180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2834191 |
1 |
|
|
T23 |
809 |
|
T30 |
104718 |
|
T43 |
85 |
| auto[1] |
auto[0] |
auto[1] |
418010 |
1 |
|
|
T23 |
205 |
|
T30 |
15903 |
|
T43 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2815809 |
1 |
|
|
T23 |
751 |
|
T30 |
97292 |
|
T43 |
83 |
| auto[1] |
auto[1] |
auto[1] |
415568 |
1 |
|
|
T23 |
180 |
|
T30 |
14281 |
|
T43 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8542410 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6486065 |
1 |
|
|
T23 |
1849 |
|
T30 |
235090 |
|
T43 |
164 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14197286 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
831189 |
1 |
|
|
T23 |
315 |
|
T30 |
30834 |
|
T43 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8560479 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6467996 |
1 |
|
|
T23 |
1693 |
|
T30 |
236929 |
|
T43 |
148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2809666 |
1 |
|
|
T23 |
657 |
|
T30 |
102044 |
|
T43 |
73 |
| auto[1] |
auto[0] |
auto[1] |
413874 |
1 |
|
|
T23 |
155 |
|
T30 |
15286 |
|
T43 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2827141 |
1 |
|
|
T23 |
721 |
|
T30 |
104051 |
|
T43 |
65 |
| auto[1] |
auto[1] |
auto[1] |
417315 |
1 |
|
|
T23 |
160 |
|
T30 |
15548 |
|
T43 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8573270 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6455205 |
1 |
|
|
T23 |
1606 |
|
T30 |
225348 |
|
T43 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14194676 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
833799 |
1 |
|
|
T23 |
337 |
|
T30 |
30259 |
|
T43 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8546005 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6482470 |
1 |
|
|
T23 |
1760 |
|
T30 |
232438 |
|
T43 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2829607 |
1 |
|
|
T23 |
835 |
|
T30 |
107494 |
|
T43 |
53 |
| auto[1] |
auto[0] |
auto[1] |
418738 |
1 |
|
|
T23 |
196 |
|
T30 |
16299 |
|
T43 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2819064 |
1 |
|
|
T23 |
588 |
|
T30 |
94685 |
|
T43 |
77 |
| auto[1] |
auto[1] |
auto[1] |
415061 |
1 |
|
|
T23 |
141 |
|
T30 |
13960 |
|
T43 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8537036 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6491439 |
1 |
|
|
T23 |
1887 |
|
T30 |
238009 |
|
T43 |
156 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14196352 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
832123 |
1 |
|
|
T23 |
303 |
|
T30 |
30992 |
|
T43 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8555348 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6473127 |
1 |
|
|
T23 |
1647 |
|
T30 |
237249 |
|
T43 |
148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2804959 |
1 |
|
|
T23 |
586 |
|
T30 |
99105 |
|
T43 |
71 |
| auto[1] |
auto[0] |
auto[1] |
411927 |
1 |
|
|
T23 |
128 |
|
T30 |
14701 |
|
T43 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2836045 |
1 |
|
|
T23 |
758 |
|
T30 |
107152 |
|
T43 |
69 |
| auto[1] |
auto[1] |
auto[1] |
420196 |
1 |
|
|
T23 |
175 |
|
T30 |
16291 |
|
T43 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8547240 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6481235 |
1 |
|
|
T23 |
1378 |
|
T30 |
235634 |
|
T43 |
168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14194093 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
834382 |
1 |
|
|
T23 |
315 |
|
T30 |
29888 |
|
T43 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8544677 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6483798 |
1 |
|
|
T23 |
1752 |
|
T30 |
230300 |
|
T43 |
187 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2832732 |
1 |
|
|
T23 |
909 |
|
T30 |
98597 |
|
T43 |
81 |
| auto[1] |
auto[0] |
auto[1] |
419139 |
1 |
|
|
T23 |
199 |
|
T30 |
14480 |
|
T43 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2816684 |
1 |
|
|
T23 |
528 |
|
T30 |
101815 |
|
T43 |
91 |
| auto[1] |
auto[1] |
auto[1] |
415243 |
1 |
|
|
T23 |
116 |
|
T30 |
15408 |
|
T43 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8560838 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6467637 |
1 |
|
|
T23 |
1738 |
|
T30 |
242537 |
|
T43 |
217 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14197224 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
831251 |
1 |
|
|
T23 |
358 |
|
T30 |
31025 |
|
T43 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8554976 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6473499 |
1 |
|
|
T23 |
1967 |
|
T30 |
235702 |
|
T43 |
165 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2828030 |
1 |
|
|
T23 |
799 |
|
T30 |
98829 |
|
T43 |
44 |
| auto[1] |
auto[0] |
auto[1] |
416533 |
1 |
|
|
T23 |
172 |
|
T30 |
14950 |
|
T43 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2814218 |
1 |
|
|
T23 |
810 |
|
T30 |
105848 |
|
T43 |
110 |
| auto[1] |
auto[1] |
auto[1] |
414718 |
1 |
|
|
T23 |
186 |
|
T30 |
16075 |
|
T43 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8538730 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6489745 |
1 |
|
|
T23 |
1814 |
|
T30 |
230487 |
|
T43 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14196192 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
832283 |
1 |
|
|
T23 |
288 |
|
T30 |
30296 |
|
T43 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8567976 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6460499 |
1 |
|
|
T23 |
1542 |
|
T30 |
232408 |
|
T43 |
182 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2803385 |
1 |
|
|
T23 |
539 |
|
T30 |
103953 |
|
T43 |
83 |
| auto[1] |
auto[0] |
auto[1] |
413887 |
1 |
|
|
T23 |
131 |
|
T30 |
15761 |
|
T43 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2824831 |
1 |
|
|
T23 |
715 |
|
T30 |
98159 |
|
T43 |
84 |
| auto[1] |
auto[1] |
auto[1] |
418396 |
1 |
|
|
T23 |
157 |
|
T30 |
14535 |
|
T43 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8558884 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6469591 |
1 |
|
|
T23 |
1546 |
|
T30 |
241302 |
|
T43 |
156 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14197170 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
831305 |
1 |
|
|
T23 |
360 |
|
T30 |
32242 |
|
T43 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8562315 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6466160 |
1 |
|
|
T23 |
1912 |
|
T30 |
244808 |
|
T43 |
188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2811426 |
1 |
|
|
T23 |
852 |
|
T30 |
102513 |
|
T43 |
55 |
| auto[1] |
auto[0] |
auto[1] |
414586 |
1 |
|
|
T23 |
193 |
|
T30 |
15444 |
|
T43 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2823429 |
1 |
|
|
T23 |
700 |
|
T30 |
110053 |
|
T43 |
116 |
| auto[1] |
auto[1] |
auto[1] |
416719 |
1 |
|
|
T23 |
167 |
|
T30 |
16798 |
|
T43 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8586584 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6441891 |
1 |
|
|
T23 |
1240 |
|
T30 |
241294 |
|
T43 |
198 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14195737 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
832738 |
1 |
|
|
T23 |
262 |
|
T30 |
30511 |
|
T43 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8554709 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6473766 |
1 |
|
|
T23 |
1403 |
|
T30 |
234836 |
|
T43 |
170 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2841200 |
1 |
|
|
T23 |
805 |
|
T30 |
97041 |
|
T43 |
49 |
| auto[1] |
auto[0] |
auto[1] |
420387 |
1 |
|
|
T23 |
184 |
|
T30 |
14268 |
|
T43 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2799828 |
1 |
|
|
T23 |
336 |
|
T30 |
107284 |
|
T43 |
108 |
| auto[1] |
auto[1] |
auto[1] |
412351 |
1 |
|
|
T23 |
78 |
|
T30 |
16243 |
|
T43 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8544936 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6483539 |
1 |
|
|
T23 |
2235 |
|
T30 |
227907 |
|
T43 |
129 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14200978 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
827497 |
1 |
|
|
T23 |
303 |
|
T30 |
30917 |
|
T43 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8579946 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6448529 |
1 |
|
|
T23 |
1576 |
|
T30 |
236060 |
|
T43 |
205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2808300 |
1 |
|
|
T23 |
486 |
|
T30 |
104601 |
|
T43 |
103 |
| auto[1] |
auto[0] |
auto[1] |
413549 |
1 |
|
|
T23 |
113 |
|
T30 |
15953 |
|
T43 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2812732 |
1 |
|
|
T23 |
787 |
|
T30 |
100542 |
|
T43 |
88 |
| auto[1] |
auto[1] |
auto[1] |
413948 |
1 |
|
|
T23 |
190 |
|
T30 |
14964 |
|
T43 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8532877 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6495598 |
1 |
|
|
T23 |
1579 |
|
T30 |
232682 |
|
T43 |
202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14198029 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
830446 |
1 |
|
|
T23 |
291 |
|
T30 |
30676 |
|
T43 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8568118 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6460357 |
1 |
|
|
T23 |
1621 |
|
T30 |
235682 |
|
T43 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2803597 |
1 |
|
|
T23 |
667 |
|
T30 |
102324 |
|
T43 |
47 |
| auto[1] |
auto[0] |
auto[1] |
412580 |
1 |
|
|
T23 |
152 |
|
T30 |
15033 |
|
T43 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2826314 |
1 |
|
|
T23 |
663 |
|
T30 |
102682 |
|
T43 |
61 |
| auto[1] |
auto[1] |
auto[1] |
417866 |
1 |
|
|
T23 |
139 |
|
T30 |
15643 |
|
T43 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8581043 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6447432 |
1 |
|
|
T23 |
1755 |
|
T30 |
233122 |
|
T43 |
124 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14194810 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
833665 |
1 |
|
|
T23 |
337 |
|
T30 |
30274 |
|
T43 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8551832 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6476643 |
1 |
|
|
T23 |
1768 |
|
T30 |
233432 |
|
T43 |
165 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2837393 |
1 |
|
|
T23 |
716 |
|
T30 |
104167 |
|
T43 |
92 |
| auto[1] |
auto[0] |
auto[1] |
420204 |
1 |
|
|
T23 |
161 |
|
T30 |
15499 |
|
T43 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2805585 |
1 |
|
|
T23 |
715 |
|
T30 |
98991 |
|
T43 |
65 |
| auto[1] |
auto[1] |
auto[1] |
413461 |
1 |
|
|
T23 |
176 |
|
T30 |
14775 |
|
T43 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8539785 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6488690 |
1 |
|
|
T23 |
1624 |
|
T30 |
235645 |
|
T43 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14199603 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
828872 |
1 |
|
|
T23 |
324 |
|
T30 |
30031 |
|
T43 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8575300 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6453175 |
1 |
|
|
T23 |
1740 |
|
T30 |
229801 |
|
T43 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2805413 |
1 |
|
|
T23 |
660 |
|
T30 |
100737 |
|
T43 |
63 |
| auto[1] |
auto[0] |
auto[1] |
412662 |
1 |
|
|
T23 |
156 |
|
T30 |
14920 |
|
T43 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2818890 |
1 |
|
|
T23 |
756 |
|
T30 |
99033 |
|
T43 |
75 |
| auto[1] |
auto[1] |
auto[1] |
416210 |
1 |
|
|
T23 |
168 |
|
T30 |
15111 |
|
T43 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8526174 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6502301 |
1 |
|
|
T23 |
1748 |
|
T30 |
232358 |
|
T43 |
163 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14193653 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
834822 |
1 |
|
|
T23 |
295 |
|
T30 |
30369 |
|
T43 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8538289 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6490186 |
1 |
|
|
T23 |
1541 |
|
T30 |
233793 |
|
T43 |
203 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2801901 |
1 |
|
|
T23 |
642 |
|
T30 |
100984 |
|
T43 |
87 |
| auto[1] |
auto[0] |
auto[1] |
412306 |
1 |
|
|
T23 |
153 |
|
T30 |
15002 |
|
T43 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2853463 |
1 |
|
|
T23 |
604 |
|
T30 |
102440 |
|
T43 |
100 |
| auto[1] |
auto[1] |
auto[1] |
422516 |
1 |
|
|
T23 |
142 |
|
T30 |
15367 |
|
T43 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8522377 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6506098 |
1 |
|
|
T23 |
1710 |
|
T30 |
236815 |
|
T43 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14196672 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
831803 |
1 |
|
|
T23 |
292 |
|
T30 |
31390 |
|
T43 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8560259 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6468216 |
1 |
|
|
T23 |
1535 |
|
T30 |
240510 |
|
T43 |
148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2818198 |
1 |
|
|
T23 |
605 |
|
T30 |
104220 |
|
T43 |
76 |
| auto[1] |
auto[0] |
auto[1] |
415770 |
1 |
|
|
T23 |
142 |
|
T30 |
15478 |
|
T43 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2818215 |
1 |
|
|
T23 |
638 |
|
T30 |
104900 |
|
T43 |
61 |
| auto[1] |
auto[1] |
auto[1] |
416033 |
1 |
|
|
T23 |
150 |
|
T30 |
15912 |
|
T43 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8531292 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6497183 |
1 |
|
|
T23 |
1599 |
|
T30 |
237842 |
|
T43 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14200819 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
827656 |
1 |
|
|
T23 |
292 |
|
T30 |
28552 |
|
T43 |
10 |