Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8575408 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6453067 |
1 |
|
|
T23 |
1577 |
|
T30 |
221835 |
|
T43 |
157 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2798270 |
1 |
|
|
T23 |
627 |
|
T30 |
96268 |
|
T43 |
76 |
| auto[1] |
auto[0] |
auto[1] |
411039 |
1 |
|
|
T23 |
150 |
|
T30 |
14133 |
|
T43 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2827141 |
1 |
|
|
T23 |
658 |
|
T30 |
97015 |
|
T43 |
71 |
| auto[1] |
auto[1] |
auto[1] |
416617 |
1 |
|
|
T23 |
142 |
|
T30 |
14419 |
|
T43 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |