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Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8544936 1 T20 219 T21 1 T22 253
auto[1] 6483539 1 T23 2235 T30 227907 T43 129


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12317817 1 T20 219 T21 1 T22 253
auto[1] 2710658 1 T23 960 T30 87844 T43 78


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8576834 1 T20 219 T21 1 T22 253
auto[1] 6451641 1 T23 1903 T30 231283 T43 155


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1871123 1 T23 316 T30 75304 T43 35
auto[1] auto[0] auto[1] 1356777 1 T23 306 T30 46075 T43 44
auto[1] auto[1] auto[0] 1869860 1 T23 627 T30 68135 T43 42
auto[1] auto[1] auto[1] 1353881 1 T23 654 T30 41769 T43 34


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%