Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8547532 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6480943 |
1 |
|
|
T23 |
1857 |
|
T30 |
230032 |
|
T43 |
127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14198421 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
830054 |
1 |
|
|
T23 |
342 |
|
T30 |
31062 |
|
T43 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8576070 |
1 |
|
|
T20 |
219 |
|
T21 |
1 |
|
T22 |
253 |
| auto[1] |
6452405 |
1 |
|
|
T23 |
1770 |
|
T30 |
236529 |
|
T43 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2806349 |
1 |
|
|
T23 |
663 |
|
T30 |
105398 |
|
T43 |
83 |
| auto[1] |
auto[0] |
auto[1] |
414031 |
1 |
|
|
T23 |
167 |
|
T30 |
16052 |
|
T43 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2816002 |
1 |
|
|
T23 |
765 |
|
T30 |
100069 |
|
T43 |
42 |
| auto[1] |
auto[1] |
auto[1] |
416023 |
1 |
|
|
T23 |
175 |
|
T30 |
15010 |
|
T43 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |