Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 945
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T762 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2463510399 Feb 21 12:41:04 PM PST 24 Feb 21 12:41:06 PM PST 24 15843187 ps
T763 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.866791742 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 33480074 ps
T764 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2249701781 Feb 21 12:41:01 PM PST 24 Feb 21 12:41:04 PM PST 24 272549895 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3757782019 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:52 PM PST 24 47259163 ps
T766 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.901625918 Feb 21 12:41:12 PM PST 24 Feb 21 12:41:15 PM PST 24 177200928 ps
T767 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2027600824 Feb 21 12:41:10 PM PST 24 Feb 21 12:41:12 PM PST 24 18733842 ps
T768 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.296987806 Feb 21 12:41:10 PM PST 24 Feb 21 12:41:12 PM PST 24 25250457 ps
T769 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.818692006 Feb 21 12:40:45 PM PST 24 Feb 21 12:40:48 PM PST 24 33421223 ps
T48 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4235074353 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:21 PM PST 24 216267790 ps
T770 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.169639665 Feb 21 12:40:59 PM PST 24 Feb 21 12:41:02 PM PST 24 144425894 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3680221083 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 35035161 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3494540402 Feb 21 12:40:45 PM PST 24 Feb 21 12:40:58 PM PST 24 533544284 ps
T94 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.698823512 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 111932656 ps
T773 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1892604308 Feb 21 12:40:49 PM PST 24 Feb 21 12:40:52 PM PST 24 173949784 ps
T774 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.197403672 Feb 21 12:40:49 PM PST 24 Feb 21 12:40:52 PM PST 24 56562763 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3778240246 Feb 21 12:41:11 PM PST 24 Feb 21 12:41:13 PM PST 24 135111979 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3263481429 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:52 PM PST 24 15509781 ps
T777 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1630681710 Feb 21 12:40:45 PM PST 24 Feb 21 12:40:47 PM PST 24 43426032 ps
T778 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3965327734 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:53 PM PST 24 165051799 ps
T779 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2041331132 Feb 21 12:41:14 PM PST 24 Feb 21 12:41:17 PM PST 24 22185046 ps
T780 /workspace/coverage/cover_reg_top/21.gpio_intr_test.4079504857 Feb 21 12:41:10 PM PST 24 Feb 21 12:41:12 PM PST 24 29071788 ps
T781 /workspace/coverage/cover_reg_top/25.gpio_intr_test.522146305 Feb 21 12:41:09 PM PST 24 Feb 21 12:41:11 PM PST 24 13624575 ps
T782 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2121858383 Feb 21 12:40:55 PM PST 24 Feb 21 12:40:58 PM PST 24 76608483 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.227438674 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:46 PM PST 24 107408874 ps
T784 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2264609026 Feb 21 12:41:05 PM PST 24 Feb 21 12:41:07 PM PST 24 401333940 ps
T785 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1235686008 Feb 21 12:41:12 PM PST 24 Feb 21 12:41:14 PM PST 24 29170154 ps
T786 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1084108142 Feb 21 12:41:20 PM PST 24 Feb 21 12:41:22 PM PST 24 24932234 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_intr_test.622608002 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:51 PM PST 24 15541968 ps
T788 /workspace/coverage/cover_reg_top/29.gpio_intr_test.598853378 Feb 21 12:41:13 PM PST 24 Feb 21 12:41:15 PM PST 24 99549177 ps
T80 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4188769284 Feb 21 12:40:49 PM PST 24 Feb 21 12:40:52 PM PST 24 13052715 ps
T789 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3364694654 Feb 21 12:41:02 PM PST 24 Feb 21 12:41:04 PM PST 24 267324086 ps
T790 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2163428532 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 15837115 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_intr_test.352526184 Feb 21 12:40:47 PM PST 24 Feb 21 12:40:51 PM PST 24 29193000 ps
T792 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4234041331 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 80464060 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2157132614 Feb 21 12:40:47 PM PST 24 Feb 21 12:40:51 PM PST 24 711199905 ps
T794 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3475504434 Feb 21 12:41:09 PM PST 24 Feb 21 12:41:10 PM PST 24 13078128 ps
T795 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1707201049 Feb 21 12:40:51 PM PST 24 Feb 21 12:40:53 PM PST 24 14459124 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1303272488 Feb 21 12:41:09 PM PST 24 Feb 21 12:41:11 PM PST 24 22300557 ps
T797 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1089586670 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 16797125 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.751554358 Feb 21 12:40:59 PM PST 24 Feb 21 12:41:02 PM PST 24 22341719 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1539802832 Feb 21 12:41:15 PM PST 24 Feb 21 12:41:17 PM PST 24 46050701 ps
T800 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4186226071 Feb 21 12:40:56 PM PST 24 Feb 21 12:41:00 PM PST 24 285808540 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2983762551 Feb 21 12:40:45 PM PST 24 Feb 21 12:40:46 PM PST 24 43625820 ps
T802 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1997072719 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:53 PM PST 24 386568086 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3661250717 Feb 21 12:40:59 PM PST 24 Feb 21 12:41:02 PM PST 24 348474030 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1765134939 Feb 21 12:40:46 PM PST 24 Feb 21 12:40:47 PM PST 24 46052283 ps
T805 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1865175710 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:53 PM PST 24 51849231 ps
T806 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1086533760 Feb 21 12:40:51 PM PST 24 Feb 21 12:40:55 PM PST 24 91141653 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2923444337 Feb 21 12:41:15 PM PST 24 Feb 21 12:41:17 PM PST 24 38293872 ps
T82 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.713109564 Feb 21 12:40:55 PM PST 24 Feb 21 12:40:57 PM PST 24 21653867 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1070838441 Feb 21 12:40:59 PM PST 24 Feb 21 12:41:02 PM PST 24 54796538 ps
T808 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3013274660 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:56 PM PST 24 74191407 ps
T809 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2585221455 Feb 21 12:41:02 PM PST 24 Feb 21 12:41:03 PM PST 24 57708729 ps
T810 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.544269090 Feb 21 12:41:11 PM PST 24 Feb 21 12:41:14 PM PST 24 34072522 ps
T811 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.661906556 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:56 PM PST 24 877125483 ps
T812 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1614332755 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:23 PM PST 24 19173104 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.417169451 Feb 21 12:40:54 PM PST 24 Feb 21 12:40:59 PM PST 24 1311763250 ps
T813 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2630525553 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 53240557 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1328797964 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:20 PM PST 24 40234936 ps
T815 /workspace/coverage/cover_reg_top/8.gpio_intr_test.449029353 Feb 21 12:40:47 PM PST 24 Feb 21 12:40:49 PM PST 24 24043379 ps
T816 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1940805244 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:22 PM PST 24 27703528 ps
T817 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3145189647 Feb 21 12:40:50 PM PST 24 Feb 21 12:40:55 PM PST 24 679633086 ps
T84 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1650750578 Feb 21 12:40:47 PM PST 24 Feb 21 12:40:51 PM PST 24 59370725 ps
T818 /workspace/coverage/cover_reg_top/42.gpio_intr_test.591837294 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:22 PM PST 24 50342414 ps
T819 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2385745651 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:46 PM PST 24 28701106 ps
T820 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3553214448 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:46 PM PST 24 35205199 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1511399694 Feb 21 12:40:47 PM PST 24 Feb 21 12:40:49 PM PST 24 153761416 ps
T822 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2169491293 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:52 PM PST 24 11745444 ps
T823 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1733295630 Feb 21 12:40:55 PM PST 24 Feb 21 12:40:57 PM PST 24 39090281 ps
T824 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.38818673 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 39848777 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3675774251 Feb 21 12:40:48 PM PST 24 Feb 21 12:40:51 PM PST 24 16525078 ps
T97 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1389661314 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 455071806 ps
T826 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3502485246 Feb 21 12:40:54 PM PST 24 Feb 21 12:40:55 PM PST 24 14679724 ps
T827 /workspace/coverage/cover_reg_top/27.gpio_intr_test.4134909185 Feb 21 12:41:10 PM PST 24 Feb 21 12:41:12 PM PST 24 36465286 ps
T87 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2258690514 Feb 21 12:40:59 PM PST 24 Feb 21 12:41:04 PM PST 24 22518160 ps
T828 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2114701737 Feb 21 12:41:17 PM PST 24 Feb 21 12:41:19 PM PST 24 97940337 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2354947394 Feb 21 12:40:43 PM PST 24 Feb 21 12:40:45 PM PST 24 16376239 ps
T830 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2668849140 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:22 PM PST 24 60261841 ps
T831 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3427361618 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 47903189 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3907791259 Feb 21 12:40:53 PM PST 24 Feb 21 12:40:55 PM PST 24 424334435 ps
T833 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1804921573 Feb 21 12:41:10 PM PST 24 Feb 21 12:41:12 PM PST 24 16327736 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3635078130 Feb 21 12:41:16 PM PST 24 Feb 21 12:41:17 PM PST 24 270020912 ps
T834 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3444672446 Feb 21 12:40:56 PM PST 24 Feb 21 12:40:58 PM PST 24 42411956 ps
T835 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.832859936 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:24 PM PST 24 50666370 ps
T836 /workspace/coverage/cover_reg_top/26.gpio_intr_test.966198659 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:24 PM PST 24 12966143 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2252238629 Feb 21 12:40:46 PM PST 24 Feb 21 12:40:47 PM PST 24 36611029 ps
T838 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.452461310 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:46 PM PST 24 206079232 ps
T839 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.373882927 Feb 21 12:40:56 PM PST 24 Feb 21 12:40:58 PM PST 24 52927809 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.911658802 Feb 21 12:40:44 PM PST 24 Feb 21 12:40:45 PM PST 24 16129125 ps
T840 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2968234638 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:20 PM PST 24 42919025 ps
T841 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1702998871 Feb 21 12:40:49 PM PST 24 Feb 21 12:40:53 PM PST 24 28356083 ps
T842 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3326551186 Feb 21 12:41:00 PM PST 24 Feb 21 12:41:02 PM PST 24 33252473 ps
T843 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1070569277 Feb 21 12:40:45 PM PST 24 Feb 21 12:40:48 PM PST 24 160480363 ps
T844 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3390288137 Feb 21 12:41:16 PM PST 24 Feb 21 12:41:19 PM PST 24 331922594 ps
T845 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.318694876 Feb 21 12:40:54 PM PST 24 Feb 21 12:40:58 PM PST 24 83368220 ps
T846 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2277649974 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 350788843 ps
T847 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399946058 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:05 PM PST 24 60841334 ps
T848 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1471750507 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:35 PM PST 24 82871825 ps
T849 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2097922329 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:50 PM PST 24 70347612 ps
T850 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2595595044 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:08 PM PST 24 53716729 ps
T851 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.198346413 Feb 21 12:41:35 PM PST 24 Feb 21 12:41:37 PM PST 24 71860171 ps
T852 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545988766 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:50 PM PST 24 43804675 ps
T853 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3327396579 Feb 21 12:42:01 PM PST 24 Feb 21 12:42:04 PM PST 24 36852970 ps
T854 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.182485991 Feb 21 12:41:59 PM PST 24 Feb 21 12:42:03 PM PST 24 150713562 ps
T855 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3745325554 Feb 21 12:41:59 PM PST 24 Feb 21 12:42:02 PM PST 24 217620857 ps
T856 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3245135631 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 48648898 ps
T857 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.816103831 Feb 21 12:41:47 PM PST 24 Feb 21 12:41:48 PM PST 24 62167928 ps
T858 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2076827814 Feb 21 12:41:41 PM PST 24 Feb 21 12:41:42 PM PST 24 173341513 ps
T859 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1432761043 Feb 21 12:42:23 PM PST 24 Feb 21 12:42:25 PM PST 24 247043751 ps
T860 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1535532265 Feb 21 12:41:31 PM PST 24 Feb 21 12:41:33 PM PST 24 675090717 ps
T861 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.18526148 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:10 PM PST 24 44203801 ps
T862 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1056271641 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:15 PM PST 24 41912427 ps
T863 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258004828 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:06 PM PST 24 27591798 ps
T864 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3706430838 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:05 PM PST 24 47088923 ps
T865 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579063950 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 80912699 ps
T866 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550858728 Feb 21 12:41:56 PM PST 24 Feb 21 12:41:57 PM PST 24 55956949 ps
T867 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1497721322 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:11 PM PST 24 79338227 ps
T868 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233858089 Feb 21 12:42:14 PM PST 24 Feb 21 12:42:15 PM PST 24 130882891 ps
T869 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4248711317 Feb 21 12:41:48 PM PST 24 Feb 21 12:41:50 PM PST 24 150211652 ps
T870 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1510676545 Feb 21 12:41:40 PM PST 24 Feb 21 12:41:42 PM PST 24 151945874 ps
T871 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861428007 Feb 21 12:41:45 PM PST 24 Feb 21 12:41:46 PM PST 24 82062501 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.683824350 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 75827953 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3797789201 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:50 PM PST 24 47425652 ps
T874 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1528070793 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 52910025 ps
T875 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2300689956 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:53 PM PST 24 84638747 ps
T876 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1925204103 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:09 PM PST 24 226276066 ps
T877 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2089100404 Feb 21 12:41:48 PM PST 24 Feb 21 12:41:50 PM PST 24 83595546 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279851017 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 47379957 ps
T879 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613804771 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 80276860 ps
T880 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.639988872 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:35 PM PST 24 78944331 ps
T881 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.698024399 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 270504259 ps
T882 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2321026140 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 49394248 ps
T883 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4148049067 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 54912661 ps
T884 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353766660 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:53 PM PST 24 157126498 ps
T885 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3761284061 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 49321205 ps
T886 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1108496477 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:05 PM PST 24 38281697 ps
T887 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1610092724 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 83931726 ps
T888 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.410577617 Feb 21 12:41:36 PM PST 24 Feb 21 12:41:37 PM PST 24 17436307 ps
T889 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2108532389 Feb 21 12:41:31 PM PST 24 Feb 21 12:41:32 PM PST 24 132078682 ps
T890 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2007243978 Feb 21 12:43:19 PM PST 24 Feb 21 12:43:21 PM PST 24 64400425 ps
T891 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.510829921 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 189145713 ps
T892 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.378000576 Feb 21 12:41:48 PM PST 24 Feb 21 12:41:50 PM PST 24 72240711 ps
T893 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.523489981 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:19 PM PST 24 70314730 ps
T894 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2675356668 Feb 21 12:42:00 PM PST 24 Feb 21 12:42:03 PM PST 24 136470250 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2328720031 Feb 21 12:41:51 PM PST 24 Feb 21 12:41:54 PM PST 24 229387626 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3564007082 Feb 21 12:43:49 PM PST 24 Feb 21 12:43:54 PM PST 24 368400222 ps
T897 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1525737994 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:18 PM PST 24 102357968 ps
T898 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1755812618 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:35 PM PST 24 118507521 ps
T899 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2042996133 Feb 21 12:41:56 PM PST 24 Feb 21 12:41:57 PM PST 24 31288390 ps
T900 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.806615384 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 95237080 ps
T901 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.464473715 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:56 PM PST 24 20912299 ps
T902 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63152799 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 96768869 ps
T903 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671267331 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:06 PM PST 24 685154364 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1647121783 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 250026549 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3094887088 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 106707238 ps
T906 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918539277 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 239024758 ps
T907 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1596569405 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 35267428 ps
T908 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.358310923 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 53195326 ps
T909 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4215360325 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 42184630 ps
T910 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1051011161 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:07 PM PST 24 46120561 ps
T911 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3178528072 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 108962100 ps
T912 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2642872404 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 52037633 ps
T913 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2448160476 Feb 21 12:42:14 PM PST 24 Feb 21 12:42:16 PM PST 24 199620829 ps
T914 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1553097229 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:07 PM PST 24 63296740 ps
T915 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3784120305 Feb 21 12:41:42 PM PST 24 Feb 21 12:41:44 PM PST 24 54967770 ps
T916 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1590768029 Feb 21 12:41:58 PM PST 24 Feb 21 12:42:01 PM PST 24 199842549 ps
T917 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.975117456 Feb 21 12:41:42 PM PST 24 Feb 21 12:41:44 PM PST 24 61147610 ps
T918 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1417153592 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:11 PM PST 24 186169594 ps
T919 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.45295432 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 21185773 ps
T920 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.282511993 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:07 PM PST 24 56249037 ps
T921 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2959573003 Feb 21 12:41:57 PM PST 24 Feb 21 12:41:59 PM PST 24 47661688 ps
T922 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.449659705 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 28167369 ps
T923 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2373418131 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:51 PM PST 24 116144995 ps
T924 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711421443 Feb 21 12:42:00 PM PST 24 Feb 21 12:42:03 PM PST 24 255535606 ps
T925 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3738105018 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 493265929 ps
T926 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2373773339 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:10 PM PST 24 540940872 ps
T927 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.777743324 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 294253658 ps
T928 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294516656 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:06 PM PST 24 388333546 ps
T929 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511980528 Feb 21 12:41:41 PM PST 24 Feb 21 12:41:43 PM PST 24 73841369 ps
T930 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2126608929 Feb 21 12:41:57 PM PST 24 Feb 21 12:41:58 PM PST 24 54901552 ps
T931 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172978932 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:07 PM PST 24 57539937 ps
T932 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4149362351 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 90860946 ps
T933 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2783707184 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:35 PM PST 24 34295116 ps
T934 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.868906695 Feb 21 12:41:40 PM PST 24 Feb 21 12:41:42 PM PST 24 435375486 ps
T935 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4049557127 Feb 21 12:43:41 PM PST 24 Feb 21 12:43:43 PM PST 24 522163897 ps
T936 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3590143208 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:18 PM PST 24 106236760 ps
T937 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.263062407 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 236371858 ps
T938 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.29394954 Feb 21 12:43:19 PM PST 24 Feb 21 12:43:21 PM PST 24 25764287 ps
T939 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1732853498 Feb 21 12:42:15 PM PST 24 Feb 21 12:42:17 PM PST 24 87872848 ps
T940 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2270175845 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 116451072 ps
T941 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3732064333 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 74549597 ps
T942 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4248749269 Feb 21 12:42:14 PM PST 24 Feb 21 12:42:15 PM PST 24 171995005 ps
T943 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2936876577 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 238663594 ps
T944 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3724637305 Feb 21 12:41:39 PM PST 24 Feb 21 12:41:40 PM PST 24 33849438 ps
T945 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.22329856 Feb 21 12:41:41 PM PST 24 Feb 21 12:41:43 PM PST 24 237248535 ps

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2948997570
Short name T26
Test name
Test status
Simulation time 79106239 ps
CPU time 3.08 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 198112 kb
Host smart-533ac05d-a4ab-41b5-9a75-5c9db0308bcd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948997570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2948997570
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1825370309
Short name T30
Test name
Test status
Simulation time 42328908999 ps
CPU time 1191.26 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:23:02 PM PST 24
Peak memory 198372 kb
Host smart-7ca4a979-f636-42a5-88aa-5c2b0069017b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1825370309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1825370309
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2282793299
Short name T4
Test name
Test status
Simulation time 4207369075 ps
CPU time 48.18 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:03:06 PM PST 24
Peak memory 198200 kb
Host smart-8c0dd976-bd5b-436f-b5fe-d603754db92e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282793299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2282793299
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2730408459
Short name T70
Test name
Test status
Simulation time 15859085 ps
CPU time 0.74 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 196136 kb
Host smart-f9531f9b-a685-4cc4-92a7-61e73389044e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730408459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2730408459
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.287302403
Short name T35
Test name
Test status
Simulation time 209401275 ps
CPU time 1.39 seconds
Started Feb 21 12:40:50 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198164 kb
Host smart-54d0d567-d55b-4e58-9a34-4ac3368c08c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287302403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.287302403
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2800544307
Short name T44
Test name
Test status
Simulation time 14671911 ps
CPU time 0.62 seconds
Started Feb 21 03:02:37 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 193952 kb
Host smart-cd21859c-a26a-4390-8705-00a542cbc5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800544307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2800544307
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3533796416
Short name T41
Test name
Test status
Simulation time 193440292 ps
CPU time 0.92 seconds
Started Feb 21 03:01:58 PM PST 24
Finished Feb 21 03:01:59 PM PST 24
Peak memory 213872 kb
Host smart-0e4060aa-cf3f-493b-8807-2ed4077da9e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533796416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3533796416
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2644996361
Short name T45
Test name
Test status
Simulation time 99598846 ps
CPU time 1.09 seconds
Started Feb 21 12:40:57 PM PST 24
Finished Feb 21 12:40:59 PM PST 24
Peak memory 198156 kb
Host smart-de775a80-32a6-4daf-82c5-fff8a4db8844
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644996361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2644996361
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2590900850
Short name T73
Test name
Test status
Simulation time 18569962 ps
CPU time 0.81 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:13 PM PST 24
Peak memory 196480 kb
Host smart-948f0327-d64e-40c7-a876-c478bf325bd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590900850 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2590900850
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3009392966
Short name T36
Test name
Test status
Simulation time 390879350 ps
CPU time 1.11 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:57 PM PST 24
Peak memory 198268 kb
Host smart-a61292eb-4bc3-4bcb-acab-9c52420b94aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009392966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3009392966
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1389661314
Short name T97
Test name
Test status
Simulation time 455071806 ps
CPU time 0.84 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 197452 kb
Host smart-6b20b3f3-4980-4615-b60e-16a073a28b9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389661314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1389661314
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2865203619
Short name T744
Test name
Test status
Simulation time 23361092 ps
CPU time 0.67 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 194680 kb
Host smart-896cf963-4fb7-47b8-b0e6-8ccaf3eb0b13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865203619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2865203619
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.818692006
Short name T769
Test name
Test status
Simulation time 33421223 ps
CPU time 1.43 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:48 PM PST 24
Peak memory 197376 kb
Host smart-bb76e2fc-82cf-4016-9a73-8c2181971112
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818692006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.818692006
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.911658802
Short name T86
Test name
Test status
Simulation time 16129125 ps
CPU time 0.62 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 195604 kb
Host smart-25b4c48e-5eaf-467d-93b5-d9640bc8ab6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911658802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.911658802
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1834953497
Short name T726
Test name
Test status
Simulation time 24098938 ps
CPU time 1.05 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 198104 kb
Host smart-a2c213a1-c4e9-4c63-ba8c-9f155b210928
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834953497 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1834953497
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1539802832
Short name T799
Test name
Test status
Simulation time 46050701 ps
CPU time 0.63 seconds
Started Feb 21 12:41:15 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 194944 kb
Host smart-9653fad6-8f06-4148-9fda-5b23595eb6c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539802832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1539802832
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2983762551
Short name T801
Test name
Test status
Simulation time 43625820 ps
CPU time 0.55 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 193848 kb
Host smart-0b78c5f9-35a8-41a4-a67f-b3bb70d0e6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983762551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2983762551
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2546877346
Short name T731
Test name
Test status
Simulation time 870293434 ps
CPU time 1.72 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 198236 kb
Host smart-8b2522bc-6347-4155-b5c3-cfbfd6be1b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546877346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2546877346
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2157132614
Short name T793
Test name
Test status
Simulation time 711199905 ps
CPU time 2.47 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 197288 kb
Host smart-65112997-ef2c-485a-9669-8f6341328fa3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157132614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2157132614
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3263481429
Short name T776
Test name
Test status
Simulation time 15509781 ps
CPU time 0.6 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 194844 kb
Host smart-2842e033-cc9e-48e3-83fa-f47875db628a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263481429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3263481429
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.866791742
Short name T763
Test name
Test status
Simulation time 33480074 ps
CPU time 0.85 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 198148 kb
Host smart-7fc8a763-be00-4de2-9398-88e10533fd3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866791742 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.866791742
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.38818673
Short name T824
Test name
Test status
Simulation time 39848777 ps
CPU time 0.58 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 194664 kb
Host smart-c6b4ae5b-4cae-4b75-89e7-cd49260afc18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_c
sr_rw.38818673
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1733295630
Short name T823
Test name
Test status
Simulation time 39090281 ps
CPU time 0.65 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:57 PM PST 24
Peak memory 193940 kb
Host smart-95156cfb-d2be-4b8d-a4a0-2e1f86c23738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733295630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1733295630
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1765134939
Short name T804
Test name
Test status
Simulation time 46052283 ps
CPU time 0.7 seconds
Started Feb 21 12:40:46 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 196444 kb
Host smart-b44c660f-87ae-4fc2-a495-5ae55b067fa4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765134939 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1765134939
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3494540402
Short name T772
Test name
Test status
Simulation time 533544284 ps
CPU time 1.85 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198236 kb
Host smart-0182899e-a838-486e-9a7a-1be24112c5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494540402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3494540402
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.449177274
Short name T47
Test name
Test status
Simulation time 48280641 ps
CPU time 0.87 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 197396 kb
Host smart-b6b4c06c-c289-4913-8150-eb220ec8c957
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449177274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.449177274
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2249701781
Short name T764
Test name
Test status
Simulation time 272549895 ps
CPU time 1.18 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 198276 kb
Host smart-45b0b24a-d27f-42f2-b78d-a845cf98268e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249701781 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2249701781
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2258690514
Short name T87
Test name
Test status
Simulation time 22518160 ps
CPU time 0.58 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 194932 kb
Host smart-84870695-e273-4d64-8de8-580a9d6b464e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258690514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2258690514
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2169491293
Short name T822
Test name
Test status
Simulation time 11745444 ps
CPU time 0.57 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 193868 kb
Host smart-5d13f9a5-74c0-402c-86ba-41e79e970de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169491293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2169491293
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3364694654
Short name T789
Test name
Test status
Simulation time 267324086 ps
CPU time 0.81 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 196444 kb
Host smart-9880196e-979b-4260-bef4-2b233a4ebadb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364694654 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3364694654
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2264609026
Short name T784
Test name
Test status
Simulation time 401333940 ps
CPU time 1.82 seconds
Started Feb 21 12:41:05 PM PST 24
Finished Feb 21 12:41:07 PM PST 24
Peak memory 198268 kb
Host smart-0f2581cb-028b-4d21-a97a-9fc129c34a30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264609026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2264609026
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3661250717
Short name T803
Test name
Test status
Simulation time 348474030 ps
CPU time 1.06 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 198240 kb
Host smart-59c2bdbe-9312-4b37-adb4-9520a5a9c86e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661250717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3661250717
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3239072789
Short name T720
Test name
Test status
Simulation time 76197654 ps
CPU time 1.82 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198284 kb
Host smart-fcc61fa9-5f98-4589-ab00-acbec18983d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239072789 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3239072789
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4188769284
Short name T80
Test name
Test status
Simulation time 13052715 ps
CPU time 0.6 seconds
Started Feb 21 12:40:49 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 194948 kb
Host smart-7b04e5b8-42b4-40ab-b9d4-836666edc60a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188769284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4188769284
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1303272488
Short name T796
Test name
Test status
Simulation time 22300557 ps
CPU time 0.58 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:11 PM PST 24
Peak memory 194520 kb
Host smart-29c2dcdc-3eca-4c57-a26d-1930c0517c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303272488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1303272488
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.823194631
Short name T89
Test name
Test status
Simulation time 63916762 ps
CPU time 0.86 seconds
Started Feb 21 12:40:52 PM PST 24
Finished Feb 21 12:40:54 PM PST 24
Peak memory 196432 kb
Host smart-35819cd8-4752-438e-b11b-9f8bf3e89b3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823194631 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.823194631
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1702998871
Short name T841
Test name
Test status
Simulation time 28356083 ps
CPU time 1.44 seconds
Started Feb 21 12:40:49 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198208 kb
Host smart-57f287fd-7a16-4df4-9d32-4fff2036abc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702998871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1702998871
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1892604308
Short name T773
Test name
Test status
Simulation time 173949784 ps
CPU time 0.86 seconds
Started Feb 21 12:40:49 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 197464 kb
Host smart-1e7b5bd0-bafa-49ee-8d52-c18e19c967d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892604308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1892604308
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3013274660
Short name T808
Test name
Test status
Simulation time 74191407 ps
CPU time 1.61 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:56 PM PST 24
Peak memory 198252 kb
Host smart-39b2addc-e94c-4cfc-917a-55a3132c801a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013274660 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3013274660
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2964016271
Short name T71
Test name
Test status
Simulation time 14478686 ps
CPU time 0.63 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:16 PM PST 24
Peak memory 194876 kb
Host smart-0516481f-ba3b-4bb9-9775-5090ed949b7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964016271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2964016271
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2630525553
Short name T813
Test name
Test status
Simulation time 53240557 ps
CPU time 0.58 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 193748 kb
Host smart-6791ddcb-215d-49ca-a702-d217c0ed23c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630525553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2630525553
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1804921573
Short name T833
Test name
Test status
Simulation time 16327736 ps
CPU time 0.66 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 195756 kb
Host smart-c25d190d-9e90-4f12-a31d-9096ef7ac5b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804921573 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1804921573
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.901625918
Short name T766
Test name
Test status
Simulation time 177200928 ps
CPU time 2.33 seconds
Started Feb 21 12:41:12 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 198152 kb
Host smart-f27e579e-d7db-4206-98e1-2d7e6044cc49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901625918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.901625918
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.373882927
Short name T839
Test name
Test status
Simulation time 52927809 ps
CPU time 0.88 seconds
Started Feb 21 12:40:56 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 197436 kb
Host smart-644b6734-1894-4465-99be-244df21ab4c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373882927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.373882927
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1328797964
Short name T814
Test name
Test status
Simulation time 40234936 ps
CPU time 0.7 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 197408 kb
Host smart-2fc05840-3cb3-4cea-baa6-73c94479ddae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328797964 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1328797964
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1000652923
Short name T760
Test name
Test status
Simulation time 11653565 ps
CPU time 0.55 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:56 PM PST 24
Peak memory 193340 kb
Host smart-71419743-ffef-499f-bfc8-4cc21efacb6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000652923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1000652923
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.595299713
Short name T734
Test name
Test status
Simulation time 24315495 ps
CPU time 0.59 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 193836 kb
Host smart-3171886a-bdc9-461e-8196-b61861d5e38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595299713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.595299713
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3778240246
Short name T775
Test name
Test status
Simulation time 135111979 ps
CPU time 0.74 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:13 PM PST 24
Peak memory 197160 kb
Host smart-a9903f94-0eee-4f85-9eb4-2ccfac8c855e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778240246 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3778240246
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.318694876
Short name T845
Test name
Test status
Simulation time 83368220 ps
CPU time 1.48 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198216 kb
Host smart-9f5cd2eb-7728-4e14-aa57-a734b82d59c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318694876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.318694876
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4235074353
Short name T48
Test name
Test status
Simulation time 216267790 ps
CPU time 1.38 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:21 PM PST 24
Peak memory 198044 kb
Host smart-8ef2ade8-1966-41ad-9a80-abf478b9ff20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235074353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4235074353
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1235686008
Short name T785
Test name
Test status
Simulation time 29170154 ps
CPU time 0.92 seconds
Started Feb 21 12:41:12 PM PST 24
Finished Feb 21 12:41:14 PM PST 24
Peak memory 198112 kb
Host smart-c1632d70-1ca1-48eb-9b28-a4cd512b781d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235686008 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1235686008
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3444672446
Short name T834
Test name
Test status
Simulation time 42411956 ps
CPU time 0.6 seconds
Started Feb 21 12:40:56 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 195752 kb
Host smart-f4f4c4ec-0374-4859-b56f-47be58405301
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444672446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3444672446
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3384829985
Short name T724
Test name
Test status
Simulation time 19786374 ps
CPU time 0.55 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 193784 kb
Host smart-32658ad3-8999-44f8-8d90-39ded059a9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384829985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3384829985
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3427361618
Short name T831
Test name
Test status
Simulation time 47903189 ps
CPU time 0.65 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 195384 kb
Host smart-a461810e-8c48-4ab1-91af-65004a560b32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427361618 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3427361618
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4118059099
Short name T758
Test name
Test status
Simulation time 269646373 ps
CPU time 1.6 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:59 PM PST 24
Peak memory 198156 kb
Host smart-e5dff2c2-f8c9-46f5-8e5c-5f4a54f954b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118059099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4118059099
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.661906556
Short name T811
Test name
Test status
Simulation time 877125483 ps
CPU time 1.18 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:56 PM PST 24
Peak memory 198212 kb
Host smart-651a5fca-4dd2-45bc-b1eb-8c74d01b357b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661906556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.661906556
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1627409722
Short name T755
Test name
Test status
Simulation time 75299926 ps
CPU time 0.95 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 198084 kb
Host smart-56e50197-c68e-48d3-8c57-1cb800251f80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627409722 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1627409722
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3508356694
Short name T76
Test name
Test status
Simulation time 43245201 ps
CPU time 0.6 seconds
Started Feb 21 12:41:18 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 195212 kb
Host smart-18b59176-c830-4c34-a330-31bfe88ee1d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508356694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3508356694
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4120694906
Short name T730
Test name
Test status
Simulation time 51331699 ps
CPU time 0.6 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 193924 kb
Host smart-9a4184d9-f07a-4e1e-9c15-3a1aaa18a4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120694906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4120694906
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.452461310
Short name T838
Test name
Test status
Simulation time 206079232 ps
CPU time 0.72 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 196160 kb
Host smart-cef4c2b0-da19-4844-a219-0a8cd75da866
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452461310 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.452461310
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.227438674
Short name T783
Test name
Test status
Simulation time 107408874 ps
CPU time 1.59 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 198244 kb
Host smart-0ce2fce5-57aa-49c5-9393-157b37dc257b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227438674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.227438674
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3826979236
Short name T721
Test name
Test status
Simulation time 60503088 ps
CPU time 0.68 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 198032 kb
Host smart-c76d5f67-9815-4c67-8d50-e65537cbf780
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826979236 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3826979236
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.953129810
Short name T77
Test name
Test status
Simulation time 154661844 ps
CPU time 0.63 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 195704 kb
Host smart-4a724c65-067e-44ba-a310-df54702386ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953129810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.953129810
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3553214448
Short name T820
Test name
Test status
Simulation time 35205199 ps
CPU time 0.57 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 193900 kb
Host smart-7c73bbd5-7203-4372-b673-4dbe021020d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553214448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3553214448
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2163428532
Short name T790
Test name
Test status
Simulation time 15837115 ps
CPU time 0.61 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 194944 kb
Host smart-9871507a-e9c6-4e84-aa4f-16d9c926f6bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163428532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2163428532
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3736636152
Short name T756
Test name
Test status
Simulation time 499221256 ps
CPU time 3.36 seconds
Started Feb 21 12:40:46 PM PST 24
Finished Feb 21 12:40:50 PM PST 24
Peak memory 198116 kb
Host smart-7c829ab7-8098-4de1-b9b1-20c0894b218b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736636152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3736636152
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2121858383
Short name T782
Test name
Test status
Simulation time 76608483 ps
CPU time 1.12 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198244 kb
Host smart-8533a5d8-99b8-4763-b2a5-1062c8d552d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121858383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2121858383
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1070838441
Short name T807
Test name
Test status
Simulation time 54796538 ps
CPU time 0.74 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 197828 kb
Host smart-a035b603-799c-4e7c-8bb4-5594445050b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070838441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1070838441
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3675774251
Short name T825
Test name
Test status
Simulation time 16525078 ps
CPU time 0.62 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 195100 kb
Host smart-c8f5c518-5d04-4ba2-95d5-58caf5826258
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675774251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3675774251
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.622608002
Short name T787
Test name
Test status
Simulation time 15541968 ps
CPU time 0.6 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 194572 kb
Host smart-8e2f922e-4702-4f90-9a3b-bba0c84f5a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622608002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.622608002
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2255225827
Short name T91
Test name
Test status
Simulation time 82139977 ps
CPU time 0.69 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 195892 kb
Host smart-68097ae9-8eea-470b-a5c9-d4585e307655
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255225827 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2255225827
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.169639665
Short name T770
Test name
Test status
Simulation time 144425894 ps
CPU time 2.37 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 198152 kb
Host smart-0a2cc82f-a4d8-47a0-b941-a3c5256ae0da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169639665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.169639665
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1997072719
Short name T802
Test name
Test status
Simulation time 386568086 ps
CPU time 1.49 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198288 kb
Host smart-3545439a-aa81-49e4-a55a-16df4699dac0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997072719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1997072719
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.367979418
Short name T719
Test name
Test status
Simulation time 153290496 ps
CPU time 0.8 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 198148 kb
Host smart-d8ee899d-6311-405e-807e-328882699bdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367979418 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.367979418
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1707201049
Short name T795
Test name
Test status
Simulation time 14459124 ps
CPU time 0.58 seconds
Started Feb 21 12:40:51 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 193644 kb
Host smart-c1362e9a-da3b-4658-9619-417228959a09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707201049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1707201049
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.563063247
Short name T757
Test name
Test status
Simulation time 17968467 ps
CPU time 0.57 seconds
Started Feb 21 12:41:05 PM PST 24
Finished Feb 21 12:41:05 PM PST 24
Peak memory 193872 kb
Host smart-881b90a9-8197-40c5-939d-3554f68faf49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563063247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.563063247
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3137199384
Short name T92
Test name
Test status
Simulation time 27081949 ps
CPU time 0.73 seconds
Started Feb 21 12:40:50 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 196628 kb
Host smart-7aff733e-22c8-4e0f-bd07-76eecacf5f12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137199384 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3137199384
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.889313866
Short name T740
Test name
Test status
Simulation time 256519835 ps
CPU time 1.54 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 198204 kb
Host smart-74ad637e-e7e8-44cb-87d5-8b3bdc93369c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889313866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.889313866
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2418319284
Short name T96
Test name
Test status
Simulation time 129286775 ps
CPU time 1.16 seconds
Started Feb 21 12:41:00 PM PST 24
Finished Feb 21 12:41:03 PM PST 24
Peak memory 198208 kb
Host smart-ee2ae2e8-958d-4bba-abe2-e57c68de8e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418319284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2418319284
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2220958277
Short name T743
Test name
Test status
Simulation time 69983922 ps
CPU time 0.94 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 198092 kb
Host smart-7b1a9a7a-c44f-4fe1-81f6-f61564963e93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220958277 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2220958277
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1089586670
Short name T797
Test name
Test status
Simulation time 16797125 ps
CPU time 0.61 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 195048 kb
Host smart-ee538051-b96b-42e9-b339-e6c6c50d8457
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089586670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1089586670
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1767390086
Short name T732
Test name
Test status
Simulation time 38131245 ps
CPU time 0.58 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:11 PM PST 24
Peak memory 193872 kb
Host smart-9285d757-7b41-4a4f-a7cf-789e78680bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767390086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1767390086
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.493393403
Short name T88
Test name
Test status
Simulation time 29332516 ps
CPU time 0.73 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:18 PM PST 24
Peak memory 196232 kb
Host smart-d46a7be4-cf81-409e-803a-74b349ac36b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493393403 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.493393403
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2114701737
Short name T828
Test name
Test status
Simulation time 97940337 ps
CPU time 2.21 seconds
Started Feb 21 12:41:17 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 198184 kb
Host smart-04d25c2b-3bec-41cb-b699-e2e32dcafd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114701737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2114701737
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2144347571
Short name T37
Test name
Test status
Simulation time 185811708 ps
CPU time 0.84 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 197124 kb
Host smart-62253631-4b44-4b9d-9ace-c11cca708ea4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144347571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2144347571
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.814708059
Short name T72
Test name
Test status
Simulation time 19669711 ps
CPU time 0.88 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 196208 kb
Host smart-e1b7aaef-2865-44ff-a034-c3f49b5381c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814708059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.814708059
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3145189647
Short name T817
Test name
Test status
Simulation time 679633086 ps
CPU time 2.44 seconds
Started Feb 21 12:40:50 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 196836 kb
Host smart-08ae61f9-318a-4f37-baa1-7fdffc28a902
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145189647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3145189647
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1650750578
Short name T84
Test name
Test status
Simulation time 59370725 ps
CPU time 0.64 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 195036 kb
Host smart-951203d0-b175-44fb-928b-c80f9cfe5100
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650750578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1650750578
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3757782019
Short name T765
Test name
Test status
Simulation time 47259163 ps
CPU time 0.79 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 198168 kb
Host smart-d3f9968e-88e3-4989-86c1-0d707a5b7820
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757782019 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3757782019
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1191161421
Short name T79
Test name
Test status
Simulation time 18498065 ps
CPU time 0.64 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 195080 kb
Host smart-0a8ce81b-ea07-4ebc-ae0c-cbae0e2b92ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191161421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1191161421
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2276826583
Short name T725
Test name
Test status
Simulation time 50745880 ps
CPU time 0.54 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:50 PM PST 24
Peak memory 194528 kb
Host smart-93751fa6-00f9-49c9-9672-89144a175aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276826583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2276826583
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.751554358
Short name T798
Test name
Test status
Simulation time 22341719 ps
CPU time 0.69 seconds
Started Feb 21 12:40:59 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 195296 kb
Host smart-b3287d7b-1513-47c1-bf6f-9217f9eae7f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751554358 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.751554358
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.757169665
Short name T733
Test name
Test status
Simulation time 221692474 ps
CPU time 2.65 seconds
Started Feb 21 12:40:50 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 198440 kb
Host smart-8e164d7e-81e7-4acd-a8d6-69659be687e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757169665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.757169665
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2960266383
Short name T728
Test name
Test status
Simulation time 14772240 ps
CPU time 0.59 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 193984 kb
Host smart-43372269-e02d-4f2d-862f-406804d1a55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960266383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2960266383
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4079504857
Short name T780
Test name
Test status
Simulation time 29071788 ps
CPU time 0.62 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 193976 kb
Host smart-805187ca-2b9a-4d95-b598-c4793f8b8e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079504857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4079504857
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2027600824
Short name T767
Test name
Test status
Simulation time 18733842 ps
CPU time 0.59 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 193952 kb
Host smart-e14c68ad-e9b9-41c0-a844-e7e5ae7e2394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027600824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2027600824
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2922010803
Short name T761
Test name
Test status
Simulation time 43649595 ps
CPU time 0.6 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:16 PM PST 24
Peak memory 194104 kb
Host smart-0d35daf4-f2a9-4f27-9f5d-c49f74667cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922010803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2922010803
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2353172203
Short name T751
Test name
Test status
Simulation time 50642889 ps
CPU time 0.57 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193892 kb
Host smart-af366d68-b7cf-4e20-b206-8a93e234ede2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353172203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2353172203
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.522146305
Short name T781
Test name
Test status
Simulation time 13624575 ps
CPU time 0.6 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:11 PM PST 24
Peak memory 194556 kb
Host smart-d2876613-82d2-4b62-8e23-8f7980f315e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522146305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.522146305
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.966198659
Short name T836
Test name
Test status
Simulation time 12966143 ps
CPU time 0.61 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 193932 kb
Host smart-9f09a908-7b89-40eb-9ba4-f33e77b3cadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966198659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.966198659
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4134909185
Short name T827
Test name
Test status
Simulation time 36465286 ps
CPU time 0.65 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 194012 kb
Host smart-d89c68ea-270a-4e6c-8951-b86e3533f6e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134909185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4134909185
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2585221455
Short name T809
Test name
Test status
Simulation time 57708729 ps
CPU time 0.55 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:03 PM PST 24
Peak memory 193900 kb
Host smart-ecd93e43-a1c9-426c-9577-c7162fc582a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585221455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2585221455
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.598853378
Short name T788
Test name
Test status
Simulation time 99549177 ps
CPU time 0.62 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 194504 kb
Host smart-8fb81e21-1802-4815-90f3-c9aee97da5e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598853378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.598853378
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.197403672
Short name T774
Test name
Test status
Simulation time 56562763 ps
CPU time 0.73 seconds
Started Feb 21 12:40:49 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 195728 kb
Host smart-44c932a6-b91c-4dbd-b7d3-7a720477e18a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197403672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.197403672
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1086533760
Short name T806
Test name
Test status
Simulation time 91141653 ps
CPU time 2.15 seconds
Started Feb 21 12:40:51 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 198120 kb
Host smart-f69e0197-ff47-45cb-bb2b-7f90de3c014e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086533760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1086533760
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1947425837
Short name T746
Test name
Test status
Simulation time 22950026 ps
CPU time 0.66 seconds
Started Feb 21 12:41:04 PM PST 24
Finished Feb 21 12:41:06 PM PST 24
Peak memory 194768 kb
Host smart-3e120a7f-8625-4801-bcc9-bddc0c2b24d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947425837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1947425837
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3680221083
Short name T771
Test name
Test status
Simulation time 35035161 ps
CPU time 0.97 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 198160 kb
Host smart-062537ed-04da-4303-8a8f-a4e52a82c5db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680221083 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3680221083
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.155086068
Short name T95
Test name
Test status
Simulation time 16448518 ps
CPU time 0.62 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:50 PM PST 24
Peak memory 195652 kb
Host smart-764dd667-b69a-46f5-bad2-74a013963d80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155086068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.155086068
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2853860679
Short name T722
Test name
Test status
Simulation time 11856346 ps
CPU time 0.58 seconds
Started Feb 21 12:40:52 PM PST 24
Finished Feb 21 12:40:54 PM PST 24
Peak memory 193844 kb
Host smart-b8e33c9a-9476-458f-ba62-48f722b1331c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853860679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2853860679
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3291149678
Short name T78
Test name
Test status
Simulation time 154082173 ps
CPU time 0.89 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:11 PM PST 24
Peak memory 197352 kb
Host smart-e07c89d7-5240-4d73-adfd-a3a7199ffc54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291149678 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3291149678
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3390288137
Short name T844
Test name
Test status
Simulation time 331922594 ps
CPU time 1.98 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 198232 kb
Host smart-a6a65b05-418d-4d6c-9fa3-38ed5d284298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390288137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3390288137
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.317206392
Short name T747
Test name
Test status
Simulation time 176462549 ps
CPU time 0.86 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 197420 kb
Host smart-b9f8f862-914e-4e54-8cb6-aabeb22e8e13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317206392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.317206392
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4118365824
Short name T723
Test name
Test status
Simulation time 45731400 ps
CPU time 0.58 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 193928 kb
Host smart-7972b6c5-2e2a-44a2-ba0f-13199b4ac423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118365824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4118365824
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.75229324
Short name T750
Test name
Test status
Simulation time 15121595 ps
CPU time 0.58 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193864 kb
Host smart-5b1698bc-6f3b-4cf0-82bf-97c1fbb8ffdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75229324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.75229324
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1940805244
Short name T816
Test name
Test status
Simulation time 27703528 ps
CPU time 0.59 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193848 kb
Host smart-050779ed-c379-4583-b283-abaeca10d423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940805244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1940805244
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3637771287
Short name T735
Test name
Test status
Simulation time 37052028 ps
CPU time 0.59 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 194028 kb
Host smart-3c3aeadc-0e19-47f2-aa02-094ca64de812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637771287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3637771287
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4099897660
Short name T737
Test name
Test status
Simulation time 30385371 ps
CPU time 0.56 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 193808 kb
Host smart-c520b703-e9dc-4c8a-ab30-9c6d6f16f4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099897660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4099897660
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2463510399
Short name T762
Test name
Test status
Simulation time 15843187 ps
CPU time 0.65 seconds
Started Feb 21 12:41:04 PM PST 24
Finished Feb 21 12:41:06 PM PST 24
Peak memory 193952 kb
Host smart-95f08992-c378-4f61-850e-2c5583632c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463510399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2463510399
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1614332755
Short name T812
Test name
Test status
Simulation time 19173104 ps
CPU time 0.6 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:23 PM PST 24
Peak memory 193992 kb
Host smart-321c336b-c34f-419c-b0d1-8642a7e02487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614332755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1614332755
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1084108142
Short name T786
Test name
Test status
Simulation time 24932234 ps
CPU time 0.67 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193960 kb
Host smart-d95a4e91-b9f6-46e9-a0ed-0b15e9625ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084108142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1084108142
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2668849140
Short name T830
Test name
Test status
Simulation time 60261841 ps
CPU time 0.61 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193904 kb
Host smart-0561c22c-0a79-47fa-b22f-c4e760c56efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668849140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2668849140
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.812116962
Short name T752
Test name
Test status
Simulation time 34082537 ps
CPU time 0.66 seconds
Started Feb 21 12:41:12 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 193920 kb
Host smart-8b56c513-2a16-4d29-943b-606c28ab4a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812116962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.812116962
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3635078130
Short name T85
Test name
Test status
Simulation time 270020912 ps
CPU time 0.73 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 196012 kb
Host smart-0fb2fe7d-030d-4840-ac50-52de1917402c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635078130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3635078130
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.417169451
Short name T83
Test name
Test status
Simulation time 1311763250 ps
CPU time 2.48 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:59 PM PST 24
Peak memory 196780 kb
Host smart-a3b2f32a-fe87-4f29-8dd9-dde6c9d81593
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417169451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.417169451
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2923444337
Short name T81
Test name
Test status
Simulation time 38293872 ps
CPU time 0.63 seconds
Started Feb 21 12:41:15 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 195144 kb
Host smart-6105246e-add5-47e6-b49f-a274fc1c8b93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923444337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2923444337
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4234041331
Short name T792
Test name
Test status
Simulation time 80464060 ps
CPU time 1.06 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 198092 kb
Host smart-3f3e849c-c4ce-454a-a6a4-5ea238e683d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234041331 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4234041331
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3379669382
Short name T75
Test name
Test status
Simulation time 12552653 ps
CPU time 0.6 seconds
Started Feb 21 12:40:51 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 195616 kb
Host smart-911cbdca-eb95-4487-8e67-a0a696a46d39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379669382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3379669382
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3502485246
Short name T826
Test name
Test status
Simulation time 14679724 ps
CPU time 0.58 seconds
Started Feb 21 12:40:54 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 193884 kb
Host smart-be0021fc-87da-474b-a8e8-ae5f399194f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502485246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3502485246
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2351525342
Short name T69
Test name
Test status
Simulation time 36153133 ps
CPU time 0.89 seconds
Started Feb 21 12:40:58 PM PST 24
Finished Feb 21 12:41:00 PM PST 24
Peak memory 197356 kb
Host smart-b9422f09-9580-4dea-95bb-7ffe5fc59004
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351525342 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2351525342
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.133946761
Short name T748
Test name
Test status
Simulation time 158087457 ps
CPU time 1.58 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:21 PM PST 24
Peak memory 198108 kb
Host smart-d03ee18b-8807-408c-8822-1e22edfae42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133946761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.133946761
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3907791259
Short name T832
Test name
Test status
Simulation time 424334435 ps
CPU time 1.4 seconds
Started Feb 21 12:40:53 PM PST 24
Finished Feb 21 12:40:55 PM PST 24
Peak memory 198172 kb
Host smart-2cb934e5-c7f1-4397-87cc-6bef84008296
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907791259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3907791259
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3863561226
Short name T754
Test name
Test status
Simulation time 15227199 ps
CPU time 0.57 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 193884 kb
Host smart-5f722f6e-2a82-4ada-8f60-2501a3d66444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863561226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3863561226
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1004818704
Short name T738
Test name
Test status
Simulation time 42045992 ps
CPU time 0.6 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:03 PM PST 24
Peak memory 193920 kb
Host smart-85bacc47-7a4c-4908-9971-d0191d4c32aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004818704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1004818704
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.591837294
Short name T818
Test name
Test status
Simulation time 50342414 ps
CPU time 0.57 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193852 kb
Host smart-b90d98ab-3593-4997-8e7e-d24e983002f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591837294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.591837294
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3475504434
Short name T794
Test name
Test status
Simulation time 13078128 ps
CPU time 0.58 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:10 PM PST 24
Peak memory 193932 kb
Host smart-4192cfad-c5b8-4370-83f1-30a34d7e6347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475504434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3475504434
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.897961684
Short name T729
Test name
Test status
Simulation time 11716511 ps
CPU time 0.67 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 193916 kb
Host smart-d7e07ae0-6465-4821-b62f-010efdc6f0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897961684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.897961684
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2041331132
Short name T779
Test name
Test status
Simulation time 22185046 ps
CPU time 0.65 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 193972 kb
Host smart-abd09cef-24ea-48c8-aef2-378bc7e7edc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041331132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2041331132
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2968234638
Short name T840
Test name
Test status
Simulation time 42919025 ps
CPU time 0.58 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 193892 kb
Host smart-bd0e143c-10c7-47d4-ab49-f1d861b17925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968234638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2968234638
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2122995005
Short name T745
Test name
Test status
Simulation time 50198224 ps
CPU time 0.57 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 193744 kb
Host smart-87a9f508-2296-4324-b0b7-e93c3f92c6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122995005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2122995005
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1430365324
Short name T759
Test name
Test status
Simulation time 19668647 ps
CPU time 0.55 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 193872 kb
Host smart-d36f5ceb-a62e-433b-9663-6c97965e40f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430365324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1430365324
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3326551186
Short name T842
Test name
Test status
Simulation time 33252473 ps
CPU time 0.56 seconds
Started Feb 21 12:41:00 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 193856 kb
Host smart-81ade7df-2af1-4ef9-b9fe-89ac618c9be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326551186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3326551186
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.4294628003
Short name T742
Test name
Test status
Simulation time 17081668 ps
CPU time 0.7 seconds
Started Feb 21 12:41:12 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 196908 kb
Host smart-d884a7ff-52e9-4c1c-8e27-866044333d8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294628003 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.4294628003
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.296987806
Short name T768
Test name
Test status
Simulation time 25250457 ps
CPU time 0.56 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 194076 kb
Host smart-9b13865a-31ba-4e3a-9add-b8a667ec77f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296987806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.296987806
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4271731062
Short name T727
Test name
Test status
Simulation time 14626403 ps
CPU time 0.6 seconds
Started Feb 21 12:41:18 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 194544 kb
Host smart-ede98240-5c73-4af9-9536-7b9d303b2ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271731062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4271731062
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.292501502
Short name T90
Test name
Test status
Simulation time 21157042 ps
CPU time 0.67 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 195868 kb
Host smart-78424842-a2d9-4a2a-8753-bb500a95c427
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292501502 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.292501502
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4186226071
Short name T800
Test name
Test status
Simulation time 285808540 ps
CPU time 2.29 seconds
Started Feb 21 12:40:56 PM PST 24
Finished Feb 21 12:41:00 PM PST 24
Peak memory 198152 kb
Host smart-7e23b881-13d4-45a1-aa47-e7741336708a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186226071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4186226071
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.544269090
Short name T810
Test name
Test status
Simulation time 34072522 ps
CPU time 1.54 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:14 PM PST 24
Peak memory 198352 kb
Host smart-231acbe3-c744-4955-bac8-2d53fc55e7c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544269090 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.544269090
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.713109564
Short name T82
Test name
Test status
Simulation time 21653867 ps
CPU time 0.56 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:57 PM PST 24
Peak memory 194092 kb
Host smart-b585174a-319d-4fdb-90cb-0724bf178def
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713109564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.713109564
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2252238629
Short name T837
Test name
Test status
Simulation time 36611029 ps
CPU time 0.58 seconds
Started Feb 21 12:40:46 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 194508 kb
Host smart-62ccdc96-cce1-45bf-ba05-b6d62b82d904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252238629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2252238629
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.832859936
Short name T835
Test name
Test status
Simulation time 50666370 ps
CPU time 0.78 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 197252 kb
Host smart-e99b9c0a-adda-4a8e-b26e-f04f71898b29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832859936 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.832859936
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.243290947
Short name T736
Test name
Test status
Simulation time 88414010 ps
CPU time 1.73 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 198252 kb
Host smart-39074d90-9158-4b4c-8e7d-87dbc7e02108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243290947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.243290947
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3038274624
Short name T49
Test name
Test status
Simulation time 115341882 ps
CPU time 1.34 seconds
Started Feb 21 12:40:50 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198308 kb
Host smart-c13d81d3-0287-4fd7-ba2e-292b899fdf14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038274624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3038274624
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1671314558
Short name T739
Test name
Test status
Simulation time 88128400 ps
CPU time 0.8 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 198152 kb
Host smart-eedf2a6d-25de-4083-b6f7-adc41693cc72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671314558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1671314558
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2354947394
Short name T829
Test name
Test status
Simulation time 16376239 ps
CPU time 0.59 seconds
Started Feb 21 12:40:43 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 195080 kb
Host smart-bad87359-399a-4d09-83dd-95428db91b9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354947394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2354947394
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2650331883
Short name T753
Test name
Test status
Simulation time 43539441 ps
CPU time 0.6 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 194608 kb
Host smart-8a7e573e-715b-4bbf-b055-3e5890af1ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650331883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2650331883
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.698823512
Short name T94
Test name
Test status
Simulation time 111932656 ps
CPU time 0.72 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:45 PM PST 24
Peak memory 196288 kb
Host smart-dcb88313-3206-4c23-bddf-292619f46eb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698823512 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.698823512
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1070569277
Short name T843
Test name
Test status
Simulation time 160480363 ps
CPU time 2.21 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:48 PM PST 24
Peak memory 198268 kb
Host smart-41aace13-8582-4073-bca1-2c595c711e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070569277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1070569277
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1344022778
Short name T46
Test name
Test status
Simulation time 82709395 ps
CPU time 1.17 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198288 kb
Host smart-f2ab2b20-61fa-46fd-a228-10e5ae5f70ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344022778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1344022778
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3363345003
Short name T741
Test name
Test status
Simulation time 136800205 ps
CPU time 0.94 seconds
Started Feb 21 12:40:55 PM PST 24
Finished Feb 21 12:40:58 PM PST 24
Peak memory 198148 kb
Host smart-a2c7d5d2-eb66-4024-94eb-39c8206635c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363345003 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3363345003
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1630681710
Short name T777
Test name
Test status
Simulation time 43426032 ps
CPU time 0.72 seconds
Started Feb 21 12:40:45 PM PST 24
Finished Feb 21 12:40:47 PM PST 24
Peak memory 195080 kb
Host smart-9723a5d1-8539-4f70-8adf-65ae34732ca1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630681710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1630681710
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.449029353
Short name T815
Test name
Test status
Simulation time 24043379 ps
CPU time 0.58 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:49 PM PST 24
Peak memory 193932 kb
Host smart-11cee96d-e41d-43d4-8a38-da00089a56a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449029353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.449029353
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2385745651
Short name T819
Test name
Test status
Simulation time 28701106 ps
CPU time 0.78 seconds
Started Feb 21 12:40:44 PM PST 24
Finished Feb 21 12:40:46 PM PST 24
Peak memory 196220 kb
Host smart-945db4e3-1f40-4564-ac8c-a67f699e210d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385745651 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2385745651
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3965327734
Short name T778
Test name
Test status
Simulation time 165051799 ps
CPU time 2.35 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198232 kb
Host smart-c3167f7b-0715-4e60-8665-e47ba0ef5ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965327734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3965327734
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1511399694
Short name T821
Test name
Test status
Simulation time 153761416 ps
CPU time 0.83 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:49 PM PST 24
Peak memory 197136 kb
Host smart-ba78b62e-589d-4777-a49d-d61961b3f3e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511399694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1511399694
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3853121716
Short name T749
Test name
Test status
Simulation time 74888582 ps
CPU time 0.69 seconds
Started Feb 21 12:41:00 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 198032 kb
Host smart-dc3114db-b86b-4084-aea9-6a066753d997
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853121716 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3853121716
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3219659729
Short name T74
Test name
Test status
Simulation time 33358395 ps
CPU time 0.62 seconds
Started Feb 21 12:40:58 PM PST 24
Finished Feb 21 12:40:59 PM PST 24
Peak memory 194932 kb
Host smart-df8c3f67-a169-4888-9237-6a6806916e1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219659729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3219659729
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.352526184
Short name T791
Test name
Test status
Simulation time 29193000 ps
CPU time 0.55 seconds
Started Feb 21 12:40:47 PM PST 24
Finished Feb 21 12:40:51 PM PST 24
Peak memory 193884 kb
Host smart-b6149da6-f7d0-459c-92a6-e82be578a653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352526184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.352526184
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.667149328
Short name T93
Test name
Test status
Simulation time 23633425 ps
CPU time 0.7 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:52 PM PST 24
Peak memory 195116 kb
Host smart-6ca46162-e220-4fec-8cf5-1da506b28d6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667149328 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.667149328
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1865175710
Short name T805
Test name
Test status
Simulation time 51849231 ps
CPU time 2.61 seconds
Started Feb 21 12:40:48 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198240 kb
Host smart-939900f6-a6a7-48e2-8f27-f5ca1879d471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865175710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1865175710
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1417100871
Short name T38
Test name
Test status
Simulation time 167201416 ps
CPU time 0.99 seconds
Started Feb 21 12:40:49 PM PST 24
Finished Feb 21 12:40:53 PM PST 24
Peak memory 198004 kb
Host smart-1ed85735-3059-47b3-ba30-0f0c0d24ae89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417100871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1417100871
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2230182831
Short name T192
Test name
Test status
Simulation time 50435948 ps
CPU time 0.59 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 193964 kb
Host smart-5ef6e458-dd9f-48cc-a8cf-942c79a09240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230182831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2230182831
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3930052729
Short name T396
Test name
Test status
Simulation time 14462403 ps
CPU time 0.66 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 194176 kb
Host smart-995949fa-ec67-476c-9f60-1d77ebf6f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930052729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3930052729
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2569179498
Short name T410
Test name
Test status
Simulation time 3416081941 ps
CPU time 23.17 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 196732 kb
Host smart-16ebe352-339c-448f-b29e-7e69bd9543d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569179498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2569179498
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.670206639
Short name T229
Test name
Test status
Simulation time 77033797 ps
CPU time 1.05 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:01:55 PM PST 24
Peak memory 196812 kb
Host smart-923b06c5-081e-49b2-b1a1-5671f29b3139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670206639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.670206639
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1976613640
Short name T345
Test name
Test status
Simulation time 57282550 ps
CPU time 1.03 seconds
Started Feb 21 03:01:58 PM PST 24
Finished Feb 21 03:01:59 PM PST 24
Peak memory 196088 kb
Host smart-7ba24890-e96e-4437-b6d2-34d8919ee8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976613640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1976613640
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2986125592
Short name T329
Test name
Test status
Simulation time 71794520 ps
CPU time 2.82 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 198204 kb
Host smart-b66d7962-9825-4908-a770-8540e06af2ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986125592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2986125592
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.323293068
Short name T609
Test name
Test status
Simulation time 183295280 ps
CPU time 3.35 seconds
Started Feb 21 03:02:04 PM PST 24
Finished Feb 21 03:02:07 PM PST 24
Peak memory 197000 kb
Host smart-e8ec3e6d-d9d6-43f5-94f4-177bd2167017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323293068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.323293068
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2526612202
Short name T433
Test name
Test status
Simulation time 56015489 ps
CPU time 1.13 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 195988 kb
Host smart-57da13c9-fb7b-4e5a-9ef9-184a64e04439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526612202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2526612202
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1843586727
Short name T693
Test name
Test status
Simulation time 26123804 ps
CPU time 0.91 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 196180 kb
Host smart-89c1b915-1681-45d9-9c32-582ed309c4a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843586727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1843586727
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2220035083
Short name T468
Test name
Test status
Simulation time 1112550806 ps
CPU time 5.49 seconds
Started Feb 21 03:01:55 PM PST 24
Finished Feb 21 03:02:01 PM PST 24
Peak memory 198136 kb
Host smart-0f337312-2adf-461c-9c3f-0f8f01692f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220035083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2220035083
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3728029668
Short name T505
Test name
Test status
Simulation time 161546213 ps
CPU time 1.23 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 195660 kb
Host smart-552769c1-5f33-4382-9c03-668de365329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728029668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3728029668
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.835103857
Short name T215
Test name
Test status
Simulation time 69986368 ps
CPU time 1.19 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:01:52 PM PST 24
Peak memory 195652 kb
Host smart-6d4ee115-2090-4dc7-9261-5a48c6aec52c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835103857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.835103857
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.837918112
Short name T10
Test name
Test status
Simulation time 29829535898 ps
CPU time 88.24 seconds
Started Feb 21 03:01:48 PM PST 24
Finished Feb 21 03:03:17 PM PST 24
Peak memory 198264 kb
Host smart-ef9b42c0-9d3a-4b04-98b1-2dbe1ab22de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837918112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.837918112
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4150530750
Short name T588
Test name
Test status
Simulation time 72808393652 ps
CPU time 1758.01 seconds
Started Feb 21 03:02:04 PM PST 24
Finished Feb 21 03:31:22 PM PST 24
Peak memory 198464 kb
Host smart-334d42b2-e643-41a9-b801-e9681b48b899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4150530750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4150530750
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.541368833
Short name T600
Test name
Test status
Simulation time 11309160 ps
CPU time 0.57 seconds
Started Feb 21 03:02:02 PM PST 24
Finished Feb 21 03:02:03 PM PST 24
Peak memory 193952 kb
Host smart-c48a8a15-df10-4352-95a1-16211b0c74e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541368833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.541368833
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1986261039
Short name T193
Test name
Test status
Simulation time 84916332 ps
CPU time 0.77 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 195340 kb
Host smart-d89934dc-87dc-4fd5-b24a-6ba7967322c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986261039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1986261039
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2201518999
Short name T219
Test name
Test status
Simulation time 279720938 ps
CPU time 3.7 seconds
Started Feb 21 03:02:07 PM PST 24
Finished Feb 21 03:02:11 PM PST 24
Peak memory 195916 kb
Host smart-cc4415b9-37b6-4ec0-83c0-5974fded9e43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201518999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2201518999
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1796219319
Short name T6
Test name
Test status
Simulation time 176420380 ps
CPU time 0.86 seconds
Started Feb 21 03:01:57 PM PST 24
Finished Feb 21 03:01:59 PM PST 24
Peak memory 195908 kb
Host smart-4c48941e-bf70-43f0-8e70-135257a7a447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796219319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1796219319
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3909507869
Short name T477
Test name
Test status
Simulation time 102640256 ps
CPU time 0.87 seconds
Started Feb 21 03:02:08 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 196752 kb
Host smart-fa57c019-925d-4270-afdb-96c67e281d04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909507869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3909507869
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2392521470
Short name T668
Test name
Test status
Simulation time 79701071 ps
CPU time 2.94 seconds
Started Feb 21 03:02:06 PM PST 24
Finished Feb 21 03:02:10 PM PST 24
Peak memory 195992 kb
Host smart-2607ed9e-ccf8-412c-a6ed-0817b14ccaf1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392521470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2392521470
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1859237436
Short name T271
Test name
Test status
Simulation time 84006347 ps
CPU time 2.54 seconds
Started Feb 21 03:01:57 PM PST 24
Finished Feb 21 03:02:01 PM PST 24
Peak memory 197344 kb
Host smart-ea6b0022-4492-4bb9-ac19-8a97745d91a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859237436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1859237436
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.889128406
Short name T401
Test name
Test status
Simulation time 326369329 ps
CPU time 1.23 seconds
Started Feb 21 03:01:56 PM PST 24
Finished Feb 21 03:01:58 PM PST 24
Peak memory 197124 kb
Host smart-ff89d311-d46c-4647-9e21-2351d266691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889128406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.889128406
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3890925266
Short name T518
Test name
Test status
Simulation time 26579047 ps
CPU time 1.04 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:01:51 PM PST 24
Peak memory 196136 kb
Host smart-256853ce-d3e9-4057-adaf-c549670c04c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890925266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3890925266
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1441791008
Short name T289
Test name
Test status
Simulation time 247880494 ps
CPU time 2.12 seconds
Started Feb 21 03:01:54 PM PST 24
Finished Feb 21 03:01:56 PM PST 24
Peak memory 198116 kb
Host smart-b52f9e6b-e761-4b5a-8bca-4077ada854a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441791008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1441791008
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.486023802
Short name T50
Test name
Test status
Simulation time 32556579 ps
CPU time 0.8 seconds
Started Feb 21 03:02:07 PM PST 24
Finished Feb 21 03:02:08 PM PST 24
Peak memory 213804 kb
Host smart-6f80e3dc-14ba-4a9a-b813-b0734e9a5cde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486023802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.486023802
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.579008331
Short name T459
Test name
Test status
Simulation time 133156839 ps
CPU time 1.26 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 195908 kb
Host smart-384afb10-ec99-4c3b-8092-d4180adc8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579008331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.579008331
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.695303970
Short name T12
Test name
Test status
Simulation time 139010871 ps
CPU time 1.42 seconds
Started Feb 21 03:02:08 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 196776 kb
Host smart-b8359fbb-dcde-41be-a4bc-88578b763938
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695303970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.695303970
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3487941064
Short name T484
Test name
Test status
Simulation time 30708153913 ps
CPU time 182.88 seconds
Started Feb 21 03:01:54 PM PST 24
Finished Feb 21 03:04:57 PM PST 24
Peak memory 198200 kb
Host smart-2a2da29d-0747-4ffe-9561-b8e4cc52182d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487941064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3487941064
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.73937444
Short name T432
Test name
Test status
Simulation time 42539979496 ps
CPU time 1269.49 seconds
Started Feb 21 03:01:57 PM PST 24
Finished Feb 21 03:23:08 PM PST 24
Peak memory 198324 kb
Host smart-0ddf25b0-b931-494a-a84c-e8f724863a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=73937444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.73937444
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.172016544
Short name T102
Test name
Test status
Simulation time 62209491 ps
CPU time 0.6 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 194172 kb
Host smart-23ced180-70e1-41bd-ae03-b790d72c0cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172016544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.172016544
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3945022467
Short name T149
Test name
Test status
Simulation time 46025507 ps
CPU time 0.65 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 193720 kb
Host smart-af69a990-fb3f-4118-8146-78f4b26f949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945022467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3945022467
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4250417202
Short name T597
Test name
Test status
Simulation time 740567518 ps
CPU time 25.78 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:40 PM PST 24
Peak memory 195604 kb
Host smart-9fe0134d-c3bb-4742-8c48-f06b2fba2dd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250417202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4250417202
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1903499002
Short name T489
Test name
Test status
Simulation time 88080903 ps
CPU time 0.94 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 197280 kb
Host smart-8d386fef-a972-45b8-bfe4-0c260e7ab67e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903499002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1903499002
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2189604811
Short name T270
Test name
Test status
Simulation time 165832328 ps
CPU time 1.3 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 198216 kb
Host smart-04921965-b853-4c2e-9563-1a8f2710eca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189604811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2189604811
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2177392872
Short name T341
Test name
Test status
Simulation time 52396874 ps
CPU time 2.2 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 198224 kb
Host smart-60797881-e1a1-4582-a768-3c7aff6c4895
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177392872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2177392872
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3480221700
Short name T495
Test name
Test status
Simulation time 225360783 ps
CPU time 1.27 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 196824 kb
Host smart-88652155-eb10-4c28-a58b-57bf786846dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480221700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3480221700
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1129393336
Short name T675
Test name
Test status
Simulation time 61597501 ps
CPU time 1.22 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196808 kb
Host smart-bb5ffcb6-b041-4731-9c7c-166cb5c1cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129393336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1129393336
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2849562111
Short name T556
Test name
Test status
Simulation time 74815898 ps
CPU time 0.75 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 195372 kb
Host smart-720c66fc-34b9-4266-9d7c-d40649a3276e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849562111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2849562111
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3760223095
Short name T191
Test name
Test status
Simulation time 429794636 ps
CPU time 6.3 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:30 PM PST 24
Peak memory 198136 kb
Host smart-b38c0f71-07e6-4f34-9eef-f11c4c720079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760223095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3760223095
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1214484940
Short name T562
Test name
Test status
Simulation time 65442593 ps
CPU time 1.24 seconds
Started Feb 21 03:02:25 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 196504 kb
Host smart-0f0f3e35-89a1-4a4d-bb4f-bbd988381b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214484940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1214484940
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3390179060
Short name T718
Test name
Test status
Simulation time 27057647 ps
CPU time 0.84 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 195428 kb
Host smart-36555c6e-f719-411b-a97b-dafbc083ff15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390179060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3390179060
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2646877420
Short name T589
Test name
Test status
Simulation time 63237823431 ps
CPU time 224.79 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:06:04 PM PST 24
Peak memory 198248 kb
Host smart-d343d49e-d2ff-42ac-98da-18fff3328b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646877420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2646877420
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3196518358
Short name T209
Test name
Test status
Simulation time 20289596 ps
CPU time 0.66 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 193988 kb
Host smart-fc734a3b-72b3-4359-8937-f564aabdf9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196518358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3196518358
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2651525483
Short name T641
Test name
Test status
Simulation time 49173142 ps
CPU time 0.84 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 196636 kb
Host smart-b80afd90-37a4-4a0b-ba7a-627d8afff31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651525483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2651525483
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.444563528
Short name T513
Test name
Test status
Simulation time 1915211536 ps
CPU time 8.53 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 195668 kb
Host smart-5dbfc801-1d3a-4795-b700-f790fe9eac6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444563528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.444563528
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3789742470
Short name T591
Test name
Test status
Simulation time 52567309 ps
CPU time 0.7 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 194612 kb
Host smart-24a423f0-e295-4719-b6cb-c5c94da9a491
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789742470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3789742470
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.54124670
Short name T712
Test name
Test status
Simulation time 311790596 ps
CPU time 1.11 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196208 kb
Host smart-21f6dbf6-c7f0-4d2a-9eb5-5a074a366451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54124670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.54124670
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.305294333
Short name T672
Test name
Test status
Simulation time 1296239627 ps
CPU time 3.56 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:02:38 PM PST 24
Peak memory 198224 kb
Host smart-96d45512-3b0a-4a88-b86b-2fb897870b81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305294333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.305294333
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.525258946
Short name T382
Test name
Test status
Simulation time 36063926 ps
CPU time 1.29 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:36 PM PST 24
Peak memory 196836 kb
Host smart-3a59e319-fd80-44f0-ba78-15042e886742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525258946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
525258946
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1786048369
Short name T645
Test name
Test status
Simulation time 74993691 ps
CPU time 0.78 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 196116 kb
Host smart-429e4258-d134-427d-a552-acd7c8096246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786048369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1786048369
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1884069125
Short name T199
Test name
Test status
Simulation time 28485962 ps
CPU time 0.63 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 194340 kb
Host smart-989d756e-65f6-4a65-a015-4baa04131e4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884069125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1884069125
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1508807923
Short name T18
Test name
Test status
Simulation time 338415890 ps
CPU time 3.25 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:44 PM PST 24
Peak memory 198096 kb
Host smart-492afb3a-c1fe-4c40-a18f-b8d5b35f195b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508807923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1508807923
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2137913026
Short name T276
Test name
Test status
Simulation time 92338877 ps
CPU time 1.28 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 198100 kb
Host smart-fbe87429-68ef-4877-b990-abf06ec09e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137913026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2137913026
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2802295235
Short name T375
Test name
Test status
Simulation time 95435716 ps
CPU time 0.87 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 196464 kb
Host smart-38e8975e-8f9c-43ce-bec9-008ce4d01341
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802295235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2802295235
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.4291616290
Short name T671
Test name
Test status
Simulation time 16204673355 ps
CPU time 75.94 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 198280 kb
Host smart-e961f755-047a-4cab-a229-b5861944f807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291616290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.4291616290
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3412764024
Short name T424
Test name
Test status
Simulation time 440246317776 ps
CPU time 2560.38 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:45:22 PM PST 24
Peak memory 198332 kb
Host smart-e7148d9e-3cc1-4a35-b04f-dc311c771f34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3412764024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3412764024
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1605993742
Short name T218
Test name
Test status
Simulation time 40782779 ps
CPU time 0.58 seconds
Started Feb 21 03:02:31 PM PST 24
Finished Feb 21 03:02:33 PM PST 24
Peak memory 194868 kb
Host smart-da27a4d5-94ad-4b9f-9c58-8c9b57cd52af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605993742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1605993742
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1663681591
Short name T640
Test name
Test status
Simulation time 30295750 ps
CPU time 0.86 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 196328 kb
Host smart-9a3162e9-c0d0-489e-ab18-745d5dab4622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663681591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1663681591
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3289599119
Short name T699
Test name
Test status
Simulation time 1178835038 ps
CPU time 8.8 seconds
Started Feb 21 03:02:52 PM PST 24
Finished Feb 21 03:03:01 PM PST 24
Peak memory 198148 kb
Host smart-5ccc56f1-c768-4bc7-9e1d-d8000178d8a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289599119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3289599119
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.744793977
Short name T158
Test name
Test status
Simulation time 64935984 ps
CPU time 1.02 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 197248 kb
Host smart-798b6960-fca9-45ff-b01c-d428c17f1675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744793977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.744793977
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1583574564
Short name T565
Test name
Test status
Simulation time 529177652 ps
CPU time 1.35 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 198168 kb
Host smart-365ee40d-3109-4961-a52f-133df05393f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583574564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1583574564
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3111305869
Short name T716
Test name
Test status
Simulation time 296057692 ps
CPU time 2.76 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:02:37 PM PST 24
Peak memory 196436 kb
Host smart-de392f05-4e66-4753-8ede-bccbc32f6459
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111305869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3111305869
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.975650155
Short name T480
Test name
Test status
Simulation time 86198424 ps
CPU time 2.08 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 196708 kb
Host smart-e063e0d2-d7b5-4219-b94b-9e9bcfa803c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975650155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
975650155
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.424793187
Short name T644
Test name
Test status
Simulation time 38422722 ps
CPU time 1.01 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 196764 kb
Host smart-458bbb9e-5b11-4a74-bc44-26854d26ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424793187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.424793187
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1405056526
Short name T174
Test name
Test status
Simulation time 128286562 ps
CPU time 1.36 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 198040 kb
Host smart-c5faa823-54cf-48e9-ac2e-0fb43ac8ba45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405056526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1405056526
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2942833021
Short name T255
Test name
Test status
Simulation time 1151530622 ps
CPU time 2.13 seconds
Started Feb 21 03:02:31 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 198144 kb
Host smart-14bfe72d-d49e-4c4a-aa5f-3dd410644718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942833021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2942833021
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2660255456
Short name T472
Test name
Test status
Simulation time 243428036 ps
CPU time 1.15 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 195928 kb
Host smart-abcb5ad1-fe1c-42c8-9c01-8486ece55e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660255456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2660255456
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.359265141
Short name T534
Test name
Test status
Simulation time 76472965 ps
CPU time 0.92 seconds
Started Feb 21 03:02:28 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 196532 kb
Host smart-f46450b3-a11b-4c41-a39b-526d33b349e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359265141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.359265141
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2883037934
Short name T196
Test name
Test status
Simulation time 207075425411 ps
CPU time 111.13 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:04:36 PM PST 24
Peak memory 198224 kb
Host smart-1c58f54b-8693-4be9-8683-c1057aebe1f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883037934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2883037934
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2742673022
Short name T66
Test name
Test status
Simulation time 39826444830 ps
CPU time 968.34 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:18:53 PM PST 24
Peak memory 198252 kb
Host smart-4611b964-761d-4e8c-9be0-0e2b91bb93d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2742673022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2742673022
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4061558063
Short name T514
Test name
Test status
Simulation time 19860833 ps
CPU time 0.58 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 193956 kb
Host smart-e59fcf54-210a-46f5-9fdd-38d05709606c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061558063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4061558063
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.304783921
Short name T152
Test name
Test status
Simulation time 75806736 ps
CPU time 0.63 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 194800 kb
Host smart-8ee1c9d7-1e7e-47f0-86c8-ca0a400e0afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304783921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.304783921
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3195336125
Short name T583
Test name
Test status
Simulation time 242931393 ps
CPU time 12.65 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:31 PM PST 24
Peak memory 197092 kb
Host smart-b74ffe69-7ab6-457a-8f52-72c59a363159
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195336125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3195336125
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3662046821
Short name T101
Test name
Test status
Simulation time 148321071 ps
CPU time 0.76 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 194800 kb
Host smart-333a89d5-7a59-4581-aa9c-94584c5bba09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662046821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3662046821
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4291407131
Short name T13
Test name
Test status
Simulation time 432725883 ps
CPU time 1.45 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 195892 kb
Host smart-97a7990c-c517-4b97-a4c4-e48700c56f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291407131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4291407131
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.542929657
Short name T554
Test name
Test status
Simulation time 85251810 ps
CPU time 1.69 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 196860 kb
Host smart-dd830efa-6e72-4393-9157-f89b965a83b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542929657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.542929657
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1319998246
Short name T702
Test name
Test status
Simulation time 93235135 ps
CPU time 3.03 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 197236 kb
Host smart-11acf522-5b61-42b0-b2fd-5bc74d3827f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319998246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1319998246
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2627898719
Short name T124
Test name
Test status
Simulation time 46302412 ps
CPU time 0.66 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 194320 kb
Host smart-1c2a7bab-065c-4a77-98db-e9520ef221cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627898719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2627898719
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1999864975
Short name T586
Test name
Test status
Simulation time 138825676 ps
CPU time 0.91 seconds
Started Feb 21 03:02:38 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 196708 kb
Host smart-68a8815d-2cf7-4ade-b929-c20a1f951045
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999864975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1999864975
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1808249495
Short name T413
Test name
Test status
Simulation time 885169175 ps
CPU time 5.49 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 198068 kb
Host smart-7accee2b-0198-4623-b622-2a8ae47277f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808249495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1808249495
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2596947132
Short name T319
Test name
Test status
Simulation time 61412971 ps
CPU time 0.95 seconds
Started Feb 21 03:02:35 PM PST 24
Finished Feb 21 03:02:37 PM PST 24
Peak memory 195852 kb
Host smart-f45b17ec-5efe-4087-9bd1-50b71ccac17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596947132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2596947132
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3134694034
Short name T163
Test name
Test status
Simulation time 75520836 ps
CPU time 0.93 seconds
Started Feb 21 03:02:37 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 195624 kb
Host smart-2176587f-5da5-4ba1-be1c-a0ce83097066
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134694034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3134694034
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2433799474
Short name T140
Test name
Test status
Simulation time 14651611 ps
CPU time 0.56 seconds
Started Feb 21 03:02:26 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 193936 kb
Host smart-2277a077-e03b-4352-9a57-620ed101bc0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433799474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2433799474
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.221494323
Short name T692
Test name
Test status
Simulation time 18202826 ps
CPU time 0.63 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 194100 kb
Host smart-d89f25cd-8767-49a8-aa47-075d4ff573dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221494323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.221494323
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1948448036
Short name T464
Test name
Test status
Simulation time 387784611 ps
CPU time 16.86 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:36 PM PST 24
Peak memory 196944 kb
Host smart-369b0a0c-7887-4161-bacf-366260304367
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948448036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1948448036
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1271838773
Short name T629
Test name
Test status
Simulation time 78939390 ps
CPU time 0.67 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 194788 kb
Host smart-9c088d00-b1cf-45e9-bc85-645e0d4c736f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271838773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1271838773
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4154499795
Short name T247
Test name
Test status
Simulation time 94069667 ps
CPU time 1.27 seconds
Started Feb 21 03:02:26 PM PST 24
Finished Feb 21 03:02:27 PM PST 24
Peak memory 195928 kb
Host smart-294faad6-198a-4827-a104-04644be7b233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154499795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4154499795
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.751054510
Short name T202
Test name
Test status
Simulation time 355725601 ps
CPU time 3.59 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 198168 kb
Host smart-18efa7ac-f85e-4e78-a397-927c77e944a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751054510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.751054510
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1954987526
Short name T327
Test name
Test status
Simulation time 133663787 ps
CPU time 1.26 seconds
Started Feb 21 03:02:30 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 196032 kb
Host smart-41e8f23b-de16-41a4-ac2d-1c6f74243627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954987526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1954987526
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2850071377
Short name T275
Test name
Test status
Simulation time 32405668 ps
CPU time 1.22 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 198164 kb
Host smart-35bfc4d9-557b-4bbe-a122-784c7f5e1760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850071377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2850071377
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2644202001
Short name T605
Test name
Test status
Simulation time 18583007 ps
CPU time 0.68 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 195456 kb
Host smart-a78af2f2-9208-4975-83e9-80c25cb41725
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644202001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2644202001
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2968472942
Short name T648
Test name
Test status
Simulation time 432819684 ps
CPU time 3.59 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:45 PM PST 24
Peak memory 198036 kb
Host smart-95683597-c310-451e-94b6-130c4619e278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968472942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2968472942
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.987694322
Short name T444
Test name
Test status
Simulation time 292501225 ps
CPU time 1.35 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 196976 kb
Host smart-b3c1a31c-d85b-45db-8d92-3f317c480424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987694322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.987694322
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.4267142037
Short name T510
Test name
Test status
Simulation time 38678693 ps
CPU time 1.07 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 195648 kb
Host smart-53230e90-b0be-46a2-99e3-04fd27ea53a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267142037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.4267142037
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.600676142
Short name T474
Test name
Test status
Simulation time 77602992186 ps
CPU time 56.69 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 197828 kb
Host smart-f5c7ecf0-2a35-40e2-a61d-9bc512e27fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600676142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.600676142
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2113076433
Short name T138
Test name
Test status
Simulation time 27765568 ps
CPU time 0.91 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 196552 kb
Host smart-32f237fc-9444-466e-9d7b-1aadfdf9a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113076433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2113076433
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.257782061
Short name T607
Test name
Test status
Simulation time 366488997 ps
CPU time 6.64 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:41 PM PST 24
Peak memory 196884 kb
Host smart-cd29bdc1-ea40-48ba-97a2-dea40419df49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257782061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.257782061
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1482460012
Short name T420
Test name
Test status
Simulation time 90296546 ps
CPU time 1.09 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 196496 kb
Host smart-61b0dc16-1e6f-414d-b0d3-448b6672b432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482460012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1482460012
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1457731205
Short name T322
Test name
Test status
Simulation time 461239069 ps
CPU time 1.4 seconds
Started Feb 21 03:02:27 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 197264 kb
Host smart-11fd643c-3335-410b-993c-6720993de9b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457731205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1457731205
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2345339673
Short name T666
Test name
Test status
Simulation time 71932826 ps
CPU time 2.99 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:44 PM PST 24
Peak memory 196440 kb
Host smart-0b2643e2-b2a1-4d46-abd1-8aa24b947aa6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345339673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2345339673
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3711641292
Short name T160
Test name
Test status
Simulation time 201946880 ps
CPU time 1.66 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 196760 kb
Host smart-e3df5b10-4272-4e4c-b349-43ea0f95ec74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711641292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3711641292
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2098801427
Short name T29
Test name
Test status
Simulation time 44905638 ps
CPU time 0.67 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 194372 kb
Host smart-c6524ed1-46cb-48e2-bb0b-bb9337a81222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098801427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2098801427
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1016827322
Short name T705
Test name
Test status
Simulation time 500503004 ps
CPU time 1.03 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 196132 kb
Host smart-90ef9c84-db65-47c1-9753-9763d477141e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016827322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1016827322
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1182282127
Short name T54
Test name
Test status
Simulation time 1274548840 ps
CPU time 5.29 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 198080 kb
Host smart-9276071e-8d7b-4496-b1b7-3bb221f767e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182282127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1182282127
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1449479668
Short name T542
Test name
Test status
Simulation time 241066083 ps
CPU time 1.21 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:36 PM PST 24
Peak memory 196596 kb
Host smart-a5531fc3-f79c-4c2f-abb7-b4e62b97e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449479668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1449479668
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2261359990
Short name T232
Test name
Test status
Simulation time 303819084 ps
CPU time 0.97 seconds
Started Feb 21 03:02:25 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 195920 kb
Host smart-e4b31a3e-b7ca-48a2-9dac-8b7ddf955ac7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261359990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2261359990
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2090336503
Short name T360
Test name
Test status
Simulation time 2990909889 ps
CPU time 40.69 seconds
Started Feb 21 03:02:38 PM PST 24
Finished Feb 21 03:03:19 PM PST 24
Peak memory 198204 kb
Host smart-5b8753b4-1414-495e-9390-bdda11332634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090336503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2090336503
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.545067831
Short name T630
Test name
Test status
Simulation time 86709797 ps
CPU time 0.58 seconds
Started Feb 21 03:02:31 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 194636 kb
Host smart-c49b0aec-d261-4782-9173-ec87335b91d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545067831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.545067831
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3180031451
Short name T57
Test name
Test status
Simulation time 45028082 ps
CPU time 0.96 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 195964 kb
Host smart-73ef71c4-768c-412f-ab3c-006e0ef794ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180031451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3180031451
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4011924139
Short name T463
Test name
Test status
Simulation time 942115506 ps
CPU time 25.45 seconds
Started Feb 21 03:02:37 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 196960 kb
Host smart-1b543791-0591-445b-bbb0-9e887a64b6a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011924139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4011924139
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1844041377
Short name T183
Test name
Test status
Simulation time 113143919 ps
CPU time 0.72 seconds
Started Feb 21 03:02:37 PM PST 24
Finished Feb 21 03:02:38 PM PST 24
Peak memory 195536 kb
Host smart-1951b338-7320-4714-91ea-d1ed1b73d55c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844041377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1844041377
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4197295933
Short name T646
Test name
Test status
Simulation time 47552705 ps
CPU time 1.4 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 197852 kb
Host smart-942e3e4a-8a65-4bec-b37e-28f4285d286e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197295933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4197295933
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1712240003
Short name T507
Test name
Test status
Simulation time 70598014 ps
CPU time 2.8 seconds
Started Feb 21 03:02:38 PM PST 24
Finished Feb 21 03:02:41 PM PST 24
Peak memory 198184 kb
Host smart-7ce232b6-63a9-4175-8d94-6e12d65d11ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712240003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1712240003
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2914694563
Short name T657
Test name
Test status
Simulation time 113761030 ps
CPU time 2.61 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:44 PM PST 24
Peak memory 197360 kb
Host smart-908d6b15-d1e7-4c42-9db1-0862457663d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914694563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2914694563
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3844380589
Short name T312
Test name
Test status
Simulation time 30656743 ps
CPU time 1.11 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 195888 kb
Host smart-550298f8-12a8-49cf-9433-785fc867693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844380589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3844380589
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3071017211
Short name T164
Test name
Test status
Simulation time 54867865 ps
CPU time 1.28 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 198152 kb
Host smart-e73a6f42-c826-41f8-889d-bd5e82892e7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071017211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3071017211
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3767643635
Short name T250
Test name
Test status
Simulation time 79562914 ps
CPU time 3.68 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:45 PM PST 24
Peak memory 198132 kb
Host smart-badfac44-4d0c-4c1a-8ebe-95e7301004d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767643635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3767643635
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3665768229
Short name T317
Test name
Test status
Simulation time 112694970 ps
CPU time 0.92 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 195212 kb
Host smart-4d183de2-4434-4de2-a5aa-9748d05a9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665768229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3665768229
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1923738860
Short name T473
Test name
Test status
Simulation time 218372095 ps
CPU time 0.91 seconds
Started Feb 21 03:02:40 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 196384 kb
Host smart-6b9d73fb-3d00-4c0c-adeb-82920d349a05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923738860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1923738860
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1757720423
Short name T283
Test name
Test status
Simulation time 50561616492 ps
CPU time 98.67 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:04:12 PM PST 24
Peak memory 198248 kb
Host smart-03b5b591-f617-4578-ad6e-a202f641c660
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757720423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1757720423
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1294413949
Short name T577
Test name
Test status
Simulation time 22271661067 ps
CPU time 367.65 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:08:42 PM PST 24
Peak memory 198392 kb
Host smart-9fd383a8-f1ea-4848-8c8d-367205d30727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1294413949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1294413949
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3865270724
Short name T713
Test name
Test status
Simulation time 20204783 ps
CPU time 0.64 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 194112 kb
Host smart-f9a72cd3-85c4-4230-9b1b-62549cfa186b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865270724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3865270724
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3011065403
Short name T353
Test name
Test status
Simulation time 58906571 ps
CPU time 0.63 seconds
Started Feb 21 03:02:31 PM PST 24
Finished Feb 21 03:02:33 PM PST 24
Peak memory 194772 kb
Host smart-86d817e4-23ba-4fa8-be3f-8fd79ac657af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011065403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3011065403
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2791809922
Short name T431
Test name
Test status
Simulation time 573188577 ps
CPU time 4.15 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 195900 kb
Host smart-d00f4630-3c33-4151-9e61-42c865242702
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791809922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2791809922
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1860309016
Short name T448
Test name
Test status
Simulation time 88004886 ps
CPU time 1.02 seconds
Started Feb 21 03:02:31 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 196692 kb
Host smart-3681e3c1-42cc-40b4-b03f-d01e343dd364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860309016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1860309016
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1621365945
Short name T349
Test name
Test status
Simulation time 60642587 ps
CPU time 0.66 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 194548 kb
Host smart-9917374a-3053-4043-a1a7-c7e53976ca9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621365945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1621365945
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1615156011
Short name T709
Test name
Test status
Simulation time 79809211 ps
CPU time 3.27 seconds
Started Feb 21 03:02:34 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 198172 kb
Host smart-4b0e7235-1b2d-43e5-bf2d-3fd71da42863
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615156011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1615156011
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1574650000
Short name T113
Test name
Test status
Simulation time 34997709 ps
CPU time 1.31 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 197656 kb
Host smart-d24404c3-4dad-4d76-a125-2bf56d1d5bd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574650000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1574650000
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3493781325
Short name T303
Test name
Test status
Simulation time 54754508 ps
CPU time 1.17 seconds
Started Feb 21 03:02:32 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 196688 kb
Host smart-b5157bea-85a7-440b-a45a-a5a92df423d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493781325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3493781325
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3599350558
Short name T225
Test name
Test status
Simulation time 18969525 ps
CPU time 0.7 seconds
Started Feb 21 03:02:51 PM PST 24
Finished Feb 21 03:02:51 PM PST 24
Peak memory 194308 kb
Host smart-36b9f131-5532-46ca-ad02-2f3275a6c41b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599350558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3599350558
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3864298347
Short name T397
Test name
Test status
Simulation time 299246532 ps
CPU time 2 seconds
Started Feb 21 03:02:33 PM PST 24
Finished Feb 21 03:02:37 PM PST 24
Peak memory 198032 kb
Host smart-71e11291-e9c3-4e03-8a5c-6e21ff9e2ec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864298347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3864298347
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3916755826
Short name T307
Test name
Test status
Simulation time 41229854 ps
CPU time 1.05 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 196356 kb
Host smart-09596ec5-fd2f-41f9-be80-d156dbcd03fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916755826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3916755826
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2743348676
Short name T462
Test name
Test status
Simulation time 48244082 ps
CPU time 0.97 seconds
Started Feb 21 03:02:42 PM PST 24
Finished Feb 21 03:02:44 PM PST 24
Peak memory 196560 kb
Host smart-b55342c2-ae3d-4996-9408-b10d652be3c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743348676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2743348676
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2337245320
Short name T8
Test name
Test status
Simulation time 18808006285 ps
CPU time 207.16 seconds
Started Feb 21 03:02:34 PM PST 24
Finished Feb 21 03:06:02 PM PST 24
Peak memory 198164 kb
Host smart-15eeb10c-24f7-4f62-8412-48f943a7c076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337245320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2337245320
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.636177424
Short name T324
Test name
Test status
Simulation time 45989611 ps
CPU time 0.59 seconds
Started Feb 21 03:02:50 PM PST 24
Finished Feb 21 03:02:51 PM PST 24
Peak memory 193976 kb
Host smart-fffd8904-1e42-434a-8091-b18882b9eb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636177424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.636177424
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.949079489
Short name T244
Test name
Test status
Simulation time 39373272 ps
CPU time 0.77 seconds
Started Feb 21 03:02:44 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 196128 kb
Host smart-2caee32e-81f8-4068-af7f-cc3c56570883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949079489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.949079489
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2297780211
Short name T167
Test name
Test status
Simulation time 555217391 ps
CPU time 17.8 seconds
Started Feb 21 03:02:44 PM PST 24
Finished Feb 21 03:03:02 PM PST 24
Peak memory 196744 kb
Host smart-a7ce5878-c3ad-4175-b088-8c0afd37e926
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297780211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2297780211
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1667178423
Short name T389
Test name
Test status
Simulation time 70119214 ps
CPU time 0.76 seconds
Started Feb 21 03:02:56 PM PST 24
Finished Feb 21 03:02:57 PM PST 24
Peak memory 195576 kb
Host smart-4a02027b-38e9-468a-a933-d0f7b06ef458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667178423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1667178423
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2689000956
Short name T267
Test name
Test status
Simulation time 152279857 ps
CPU time 1.12 seconds
Started Feb 21 03:02:44 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 196184 kb
Host smart-23633202-ff34-415a-9bbe-576ba636a676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689000956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2689000956
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2546042324
Short name T259
Test name
Test status
Simulation time 66661946 ps
CPU time 2.69 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 198168 kb
Host smart-26d043b8-9e7e-4ac0-ab2c-276857cfd59e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546042324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2546042324
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1884755182
Short name T128
Test name
Test status
Simulation time 158545960 ps
CPU time 3.37 seconds
Started Feb 21 03:02:43 PM PST 24
Finished Feb 21 03:02:47 PM PST 24
Peak memory 195948 kb
Host smart-e83ed245-f244-4027-879a-55704bf56615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884755182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1884755182
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1909506801
Short name T395
Test name
Test status
Simulation time 119815250 ps
CPU time 1.15 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 197168 kb
Host smart-de772184-5a65-4ad2-ab58-445e050a197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909506801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1909506801
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.114063040
Short name T147
Test name
Test status
Simulation time 68780170 ps
CPU time 0.76 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:47 PM PST 24
Peak memory 196512 kb
Host smart-3ee0635c-3363-44b8-846d-37b0b5b53f5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114063040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.114063040
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1079739112
Short name T559
Test name
Test status
Simulation time 76893151 ps
CPU time 1.93 seconds
Started Feb 21 03:02:47 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 198100 kb
Host smart-d5a22464-225e-4822-abf6-ca73a6684720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079739112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1079739112
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2229243065
Short name T622
Test name
Test status
Simulation time 655658664 ps
CPU time 1.11 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 195852 kb
Host smart-38496f02-01e2-4b7b-a608-69ffe7a26f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229243065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2229243065
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1343564901
Short name T642
Test name
Test status
Simulation time 89262285 ps
CPU time 0.91 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 196552 kb
Host smart-6d28527b-c548-419b-ad2e-5e1c33bf7136
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343564901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1343564901
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.498415005
Short name T411
Test name
Test status
Simulation time 1343234906 ps
CPU time 31.03 seconds
Started Feb 21 03:02:55 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 198188 kb
Host smart-be47dcfb-83b7-4cdb-bbfa-dce76fcb8735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498415005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.498415005
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1985430637
Short name T56
Test name
Test status
Simulation time 11508331 ps
CPU time 0.57 seconds
Started Feb 21 03:02:47 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 193948 kb
Host smart-3dcb05ca-afd8-4649-931b-0e2cff766575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985430637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1985430637
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3044290487
Short name T313
Test name
Test status
Simulation time 43978896 ps
CPU time 0.79 seconds
Started Feb 21 03:02:58 PM PST 24
Finished Feb 21 03:02:59 PM PST 24
Peak memory 195408 kb
Host smart-80d2b2b9-db5d-4968-b65e-ca091d7befbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044290487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3044290487
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3162476692
Short name T220
Test name
Test status
Simulation time 1635623224 ps
CPU time 14.73 seconds
Started Feb 21 03:02:42 PM PST 24
Finished Feb 21 03:02:57 PM PST 24
Peak memory 196932 kb
Host smart-f9d1dc75-494c-44c5-b9a3-9d35072f1266
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162476692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3162476692
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.521167345
Short name T284
Test name
Test status
Simulation time 52681672 ps
CPU time 0.87 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 196764 kb
Host smart-6b44393f-732d-4189-91e7-6a736de9a41c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521167345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.521167345
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2494550540
Short name T430
Test name
Test status
Simulation time 85335709 ps
CPU time 0.91 seconds
Started Feb 21 03:02:54 PM PST 24
Finished Feb 21 03:02:55 PM PST 24
Peak memory 197568 kb
Host smart-eb0daa80-bd73-4dbb-8e77-48022df25e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494550540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2494550540
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4077775494
Short name T530
Test name
Test status
Simulation time 100644513 ps
CPU time 3.08 seconds
Started Feb 21 03:02:47 PM PST 24
Finished Feb 21 03:02:51 PM PST 24
Peak memory 198188 kb
Host smart-4177f3fa-c267-4d2a-982f-481ba21cc5c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077775494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4077775494
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3083048200
Short name T146
Test name
Test status
Simulation time 395456039 ps
CPU time 3 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 198148 kb
Host smart-d583a1bb-6fa3-414b-a75f-6a4c0fae5167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083048200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3083048200
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3917301383
Short name T221
Test name
Test status
Simulation time 217326727 ps
CPU time 1.32 seconds
Started Feb 21 03:02:48 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 197136 kb
Host smart-0959348e-c3a2-46ab-afa6-b90fcda6c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917301383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3917301383
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1558679230
Short name T500
Test name
Test status
Simulation time 38625577 ps
CPU time 0.97 seconds
Started Feb 21 03:02:43 PM PST 24
Finished Feb 21 03:02:45 PM PST 24
Peak memory 196048 kb
Host smart-41e8d589-a696-49c3-857b-c1bee24e3e56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558679230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1558679230
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3296653302
Short name T308
Test name
Test status
Simulation time 3037180467 ps
CPU time 3.06 seconds
Started Feb 21 03:02:52 PM PST 24
Finished Feb 21 03:02:55 PM PST 24
Peak memory 198120 kb
Host smart-b9d423a9-b851-46c0-8f26-942240fe1bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296653302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3296653302
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.627332273
Short name T352
Test name
Test status
Simulation time 41516942 ps
CPU time 1.18 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 196304 kb
Host smart-0351cf9f-3240-4236-bfcb-0585f84ea697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627332273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.627332273
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2421963515
Short name T478
Test name
Test status
Simulation time 697456982 ps
CPU time 1.47 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 196760 kb
Host smart-53135a68-cb11-4adb-bfa5-f0d186ae599e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421963515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2421963515
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2614337656
Short name T681
Test name
Test status
Simulation time 9702757783 ps
CPU time 96.05 seconds
Started Feb 21 03:02:47 PM PST 24
Finished Feb 21 03:04:24 PM PST 24
Peak memory 198228 kb
Host smart-69c62c50-2388-45bd-b5f1-cad73f4ac319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614337656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2614337656
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.182169912
Short name T493
Test name
Test status
Simulation time 13313402 ps
CPU time 0.55 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 193932 kb
Host smart-51f68aa0-85c7-4969-8334-26c7492ba2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182169912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.182169912
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1052056396
Short name T142
Test name
Test status
Simulation time 149550273 ps
CPU time 0.89 seconds
Started Feb 21 03:02:04 PM PST 24
Finished Feb 21 03:02:05 PM PST 24
Peak memory 196580 kb
Host smart-e5f04231-6ac6-47c4-85c6-47ad0134127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052056396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1052056396
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.307564116
Short name T350
Test name
Test status
Simulation time 1305652551 ps
CPU time 9.26 seconds
Started Feb 21 03:01:55 PM PST 24
Finished Feb 21 03:02:05 PM PST 24
Peak memory 196888 kb
Host smart-2fe594d2-7d09-4a40-a692-9d9954cc87db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307564116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.307564116
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.556862026
Short name T304
Test name
Test status
Simulation time 52371934 ps
CPU time 0.73 seconds
Started Feb 21 03:01:56 PM PST 24
Finished Feb 21 03:01:57 PM PST 24
Peak memory 195680 kb
Host smart-f96a2b61-b00f-4f54-979f-7ea281504cbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556862026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.556862026
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.554630848
Short name T14
Test name
Test status
Simulation time 123892518 ps
CPU time 1.25 seconds
Started Feb 21 03:01:56 PM PST 24
Finished Feb 21 03:01:58 PM PST 24
Peak memory 196108 kb
Host smart-48ace8f7-1058-4011-9a9b-72266d04fb46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554630848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.554630848
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2207288540
Short name T190
Test name
Test status
Simulation time 173037379 ps
CPU time 1.97 seconds
Started Feb 21 03:02:04 PM PST 24
Finished Feb 21 03:02:06 PM PST 24
Peak memory 198136 kb
Host smart-e0415b2f-f352-4608-adce-537ade411ebe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207288540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2207288540
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.885053713
Short name T416
Test name
Test status
Simulation time 1018543009 ps
CPU time 1.68 seconds
Started Feb 21 03:01:55 PM PST 24
Finished Feb 21 03:01:57 PM PST 24
Peak memory 195968 kb
Host smart-182ac4b1-c2d1-4b1f-9cf3-11e25aba2b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885053713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.885053713
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2602743554
Short name T501
Test name
Test status
Simulation time 144295993 ps
CPU time 1.24 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 196184 kb
Host smart-ec552df9-5ebf-4d24-a931-3aca9841b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602743554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2602743554
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3205659671
Short name T543
Test name
Test status
Simulation time 86784606 ps
CPU time 0.83 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:11 PM PST 24
Peak memory 196520 kb
Host smart-56dd7675-6c39-44c0-ad83-84947de09a29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205659671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3205659671
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1261693195
Short name T1
Test name
Test status
Simulation time 514204771 ps
CPU time 5.94 seconds
Started Feb 21 03:02:02 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 198084 kb
Host smart-7a6330f4-cb7d-45af-872f-26d7dcbf4718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261693195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1261693195
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2282196247
Short name T51
Test name
Test status
Simulation time 98799572 ps
CPU time 0.98 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 215004 kb
Host smart-3e463f3c-f8a8-485e-8bee-bb9957581509
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282196247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2282196247
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.369978499
Short name T558
Test name
Test status
Simulation time 56826770 ps
CPU time 1.08 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:01:54 PM PST 24
Peak memory 195664 kb
Host smart-d2fc0367-5073-4899-ac68-aab4044c0628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369978499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.369978499
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3962534207
Short name T127
Test name
Test status
Simulation time 204220215 ps
CPU time 1 seconds
Started Feb 21 03:02:08 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 195632 kb
Host smart-ca447495-6be4-4390-bad5-0d6af5c27345
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962534207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3962534207
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.439346428
Short name T455
Test name
Test status
Simulation time 2874929085 ps
CPU time 40.17 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:03:02 PM PST 24
Peak memory 198288 kb
Host smart-e942b0db-7a80-4200-af6a-d4d89ca9e980
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439346428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.439346428
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.212235851
Short name T371
Test name
Test status
Simulation time 91136669628 ps
CPU time 716.79 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:14:12 PM PST 24
Peak memory 198388 kb
Host smart-cc6e3ac3-05f7-4704-915f-b5afd7a4018f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=212235851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.212235851
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.829357159
Short name T547
Test name
Test status
Simulation time 23442400 ps
CPU time 0.56 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:02:42 PM PST 24
Peak memory 194176 kb
Host smart-c959ad66-86e1-4fd0-aa15-04ba9458df58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829357159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.829357159
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1372358852
Short name T340
Test name
Test status
Simulation time 27847876 ps
CPU time 0.73 seconds
Started Feb 21 03:02:42 PM PST 24
Finished Feb 21 03:02:43 PM PST 24
Peak memory 195368 kb
Host smart-b0f7d5e3-5700-48b5-8356-79ebff84b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372358852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1372358852
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3828832725
Short name T241
Test name
Test status
Simulation time 278368816 ps
CPU time 8.8 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:58 PM PST 24
Peak memory 198060 kb
Host smart-cba175b9-2c7a-4747-b5c1-dfa961a4b284
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828832725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3828832725
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2844542373
Short name T366
Test name
Test status
Simulation time 275624509 ps
CPU time 0.87 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:50 PM PST 24
Peak memory 197160 kb
Host smart-8ce6995e-e265-4088-ba3c-d28588c2d609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844542373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2844542373
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2435943894
Short name T610
Test name
Test status
Simulation time 41563643 ps
CPU time 0.9 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:47 PM PST 24
Peak memory 197540 kb
Host smart-e7414691-ce5c-43c5-870e-94b51d381e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435943894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2435943894
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1705018843
Short name T136
Test name
Test status
Simulation time 30399065 ps
CPU time 1.32 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:51 PM PST 24
Peak memory 197872 kb
Host smart-c2ef2735-d664-495a-98e0-fcf5eb050dbd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705018843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1705018843
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3241213596
Short name T280
Test name
Test status
Simulation time 123857004 ps
CPU time 1.47 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 196192 kb
Host smart-6be7e22c-6e6f-4beb-982b-26d4c9c6aae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241213596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3241213596
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2601655134
Short name T611
Test name
Test status
Simulation time 193422942 ps
CPU time 1.18 seconds
Started Feb 21 03:02:53 PM PST 24
Finished Feb 21 03:02:54 PM PST 24
Peak memory 196656 kb
Host smart-57906993-d9f7-42ee-9545-ae44226d2dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601655134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2601655134
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1117023432
Short name T453
Test name
Test status
Simulation time 123569695 ps
CPU time 1.2 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:50 PM PST 24
Peak memory 196096 kb
Host smart-7672d066-132e-46ed-845f-23565e11f6be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117023432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1117023432
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1600145455
Short name T639
Test name
Test status
Simulation time 1628127704 ps
CPU time 4.41 seconds
Started Feb 21 03:02:48 PM PST 24
Finished Feb 21 03:02:53 PM PST 24
Peak memory 198128 kb
Host smart-1197ab1e-b58e-42b2-b408-06b2348e608f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600145455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1600145455
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3152155944
Short name T579
Test name
Test status
Simulation time 77100804 ps
CPU time 0.83 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:50 PM PST 24
Peak memory 195344 kb
Host smart-a6b521a0-4b59-46b1-83a1-8c180b29650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152155944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3152155944
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.264583241
Short name T162
Test name
Test status
Simulation time 34907362 ps
CPU time 1.26 seconds
Started Feb 21 03:02:45 PM PST 24
Finished Feb 21 03:02:47 PM PST 24
Peak memory 198336 kb
Host smart-8e38580d-4867-4ba7-9383-079b97f0ddc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264583241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.264583241
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2236943810
Short name T19
Test name
Test status
Simulation time 10593338152 ps
CPU time 116.18 seconds
Started Feb 21 03:02:41 PM PST 24
Finished Feb 21 03:04:38 PM PST 24
Peak memory 198284 kb
Host smart-cecaced4-2619-4c61-82a7-5bc3d190c78a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236943810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2236943810
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.747814621
Short name T268
Test name
Test status
Simulation time 21065847 ps
CPU time 0.57 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:47 PM PST 24
Peak memory 194128 kb
Host smart-12b20d85-b20d-4a25-96f5-8e62b5114c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747814621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.747814621
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3626273363
Short name T627
Test name
Test status
Simulation time 42390100 ps
CPU time 0.71 seconds
Started Feb 21 03:02:52 PM PST 24
Finished Feb 21 03:02:53 PM PST 24
Peak memory 194144 kb
Host smart-ac3b6336-91ba-4ae6-8559-d25bd29929e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626273363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3626273363
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2192771708
Short name T292
Test name
Test status
Simulation time 3587278690 ps
CPU time 26.68 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:32 PM PST 24
Peak memory 198232 kb
Host smart-3c606d0a-c76a-44ee-a651-56269e77cac1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192771708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2192771708
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.27448058
Short name T331
Test name
Test status
Simulation time 129035359 ps
CPU time 1.09 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 196464 kb
Host smart-be14c409-03b4-4521-806c-ac1e513d4b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27448058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.27448058
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3182217473
Short name T182
Test name
Test status
Simulation time 45008681 ps
CPU time 1.17 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:06 PM PST 24
Peak memory 195808 kb
Host smart-104b8dd9-244a-44af-8b90-914c590fb571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182217473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3182217473
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.420774166
Short name T700
Test name
Test status
Simulation time 88571601 ps
CPU time 1.12 seconds
Started Feb 21 03:03:06 PM PST 24
Finished Feb 21 03:03:07 PM PST 24
Peak memory 197140 kb
Host smart-04a234b4-c8f9-45d7-b0bd-05671b309e0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420774166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.420774166
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.996672234
Short name T379
Test name
Test status
Simulation time 148223944 ps
CPU time 3.26 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:16 PM PST 24
Peak memory 198192 kb
Host smart-f092e712-d673-49bc-bb59-37a86d1f9b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996672234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
996672234
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1290605928
Short name T561
Test name
Test status
Simulation time 33728980 ps
CPU time 0.84 seconds
Started Feb 21 03:03:03 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 197312 kb
Host smart-28fea58e-9aa5-420c-9526-5af4f1818557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290605928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1290605928
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2989712424
Short name T615
Test name
Test status
Simulation time 145152981 ps
CPU time 1.44 seconds
Started Feb 21 03:03:03 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 197240 kb
Host smart-1da8c993-cec3-4fc7-bbb0-1ec72f23504e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989712424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2989712424
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.737834842
Short name T403
Test name
Test status
Simulation time 907626134 ps
CPU time 5.34 seconds
Started Feb 21 03:03:01 PM PST 24
Finished Feb 21 03:03:07 PM PST 24
Peak memory 198132 kb
Host smart-bef1aa58-2203-4311-808f-f3de4f1766ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737834842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.737834842
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.773293594
Short name T683
Test name
Test status
Simulation time 233705926 ps
CPU time 1.07 seconds
Started Feb 21 03:02:46 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 195908 kb
Host smart-bfe10825-ce65-49bd-b642-40f70e4bbbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773293594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.773293594
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2084782252
Short name T297
Test name
Test status
Simulation time 161306106 ps
CPU time 1.28 seconds
Started Feb 21 03:02:52 PM PST 24
Finished Feb 21 03:02:53 PM PST 24
Peak memory 196344 kb
Host smart-3c1bf4e1-5873-4473-9734-9c0785761a5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084782252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2084782252
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2772281367
Short name T203
Test name
Test status
Simulation time 12562581782 ps
CPU time 65.8 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 198172 kb
Host smart-dd6c3d78-9481-4785-b09d-3c212b74e24d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772281367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2772281367
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.265463948
Short name T63
Test name
Test status
Simulation time 124166877475 ps
CPU time 703.78 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:14:49 PM PST 24
Peak memory 198328 kb
Host smart-9380332e-8965-44bc-a671-bebad7b359a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=265463948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.265463948
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3834608478
Short name T197
Test name
Test status
Simulation time 14472370 ps
CPU time 0.57 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 194872 kb
Host smart-f9c17482-ac96-4350-9bae-62a30ac44ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834608478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3834608478
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3160190602
Short name T217
Test name
Test status
Simulation time 14829236 ps
CPU time 0.62 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:03:09 PM PST 24
Peak memory 194824 kb
Host smart-5259ad85-e644-40aa-89ef-07193645dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160190602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3160190602
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3975438293
Short name T446
Test name
Test status
Simulation time 560665409 ps
CPU time 16.35 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:22 PM PST 24
Peak memory 197072 kb
Host smart-85c824fc-8e0f-4da9-8912-8565e17539b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975438293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3975438293
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.117517860
Short name T135
Test name
Test status
Simulation time 21445378 ps
CPU time 0.65 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 195332 kb
Host smart-b8f39c26-8609-43a3-8935-a1d22aa6dbc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117517860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.117517860
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3033488312
Short name T548
Test name
Test status
Simulation time 98221875 ps
CPU time 0.73 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 194316 kb
Host smart-9db1cb1f-f72c-41ec-a5d2-089847c075fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033488312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3033488312
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.83154025
Short name T695
Test name
Test status
Simulation time 35700051 ps
CPU time 1.54 seconds
Started Feb 21 03:03:01 PM PST 24
Finished Feb 21 03:03:03 PM PST 24
Peak memory 196820 kb
Host smart-079e0b56-4cdf-4e19-b672-e1c189ffb41d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83154025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.gpio_intr_with_filter_rand_intr_event.83154025
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2451768493
Short name T391
Test name
Test status
Simulation time 230719500 ps
CPU time 2.56 seconds
Started Feb 21 03:03:02 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 196620 kb
Host smart-14cf4243-38d9-41c5-8c83-5692e10c35c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451768493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2451768493
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.743853275
Short name T443
Test name
Test status
Simulation time 169117886 ps
CPU time 1.01 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:12 PM PST 24
Peak memory 196072 kb
Host smart-fcd165ab-fdba-40c3-8aa3-993f4deda05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743853275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.743853275
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3573663462
Short name T707
Test name
Test status
Simulation time 180056271 ps
CPU time 0.94 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:50 PM PST 24
Peak memory 196548 kb
Host smart-df041b0c-2165-45c6-9d7b-8e981e0a26ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573663462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3573663462
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1386685304
Short name T141
Test name
Test status
Simulation time 114649938 ps
CPU time 5.21 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 198128 kb
Host smart-0c4165c7-4bec-47ce-897f-0513f1bf11e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386685304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1386685304
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3621891109
Short name T126
Test name
Test status
Simulation time 48182045 ps
CPU time 0.99 seconds
Started Feb 21 03:02:49 PM PST 24
Finished Feb 21 03:02:50 PM PST 24
Peak memory 195768 kb
Host smart-ac7f1ce3-aa58-4032-978c-6f275f1e8dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621891109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3621891109
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.962057080
Short name T224
Test name
Test status
Simulation time 78390935 ps
CPU time 1.51 seconds
Started Feb 21 03:03:06 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 196320 kb
Host smart-c83f8c17-caff-420c-8b55-3ae43925113d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962057080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.962057080
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1615779919
Short name T325
Test name
Test status
Simulation time 25001426076 ps
CPU time 171.58 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:06:00 PM PST 24
Peak memory 198396 kb
Host smart-1890b520-7c2e-48d3-831e-979b4520728a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615779919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1615779919
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.244129262
Short name T211
Test name
Test status
Simulation time 48825715 ps
CPU time 0.62 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 192864 kb
Host smart-32db709b-1638-400f-952c-ba10ed1a211a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244129262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.244129262
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1551867476
Short name T428
Test name
Test status
Simulation time 85439457 ps
CPU time 0.7 seconds
Started Feb 21 03:03:01 PM PST 24
Finished Feb 21 03:03:02 PM PST 24
Peak memory 194864 kb
Host smart-8d3ec3e0-4776-4629-afe5-490acea2c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551867476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1551867476
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2858224125
Short name T581
Test name
Test status
Simulation time 969983676 ps
CPU time 26.56 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:31 PM PST 24
Peak memory 196764 kb
Host smart-9e076685-3b14-4619-b7bd-a57c972d47fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858224125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2858224125
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1973398683
Short name T134
Test name
Test status
Simulation time 378702848 ps
CPU time 1.04 seconds
Started Feb 21 03:03:03 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 196644 kb
Host smart-00cf1b0a-8b3d-42a2-953d-e5a93b27d053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973398683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1973398683
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1530492354
Short name T251
Test name
Test status
Simulation time 266925301 ps
CPU time 0.73 seconds
Started Feb 21 03:03:09 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 195412 kb
Host smart-dd60c86c-b72e-4a05-83f8-561123b281f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530492354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1530492354
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1561443662
Short name T503
Test name
Test status
Simulation time 90259407 ps
CPU time 2.1 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 198192 kb
Host smart-55d297b7-542b-43ae-bcfd-97b2aa8239c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561443662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1561443662
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.532201650
Short name T575
Test name
Test status
Simulation time 602601724 ps
CPU time 1.23 seconds
Started Feb 21 03:03:09 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 195500 kb
Host smart-972669ec-c83e-4a75-93b5-90d6b7886922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532201650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
532201650
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.949464818
Short name T339
Test name
Test status
Simulation time 1088118707 ps
CPU time 1.22 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 195940 kb
Host smart-709495e9-56d9-481f-9808-a315ef9ad7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949464818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.949464818
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2458190645
Short name T384
Test name
Test status
Simulation time 167439601 ps
CPU time 0.71 seconds
Started Feb 21 03:03:03 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 195424 kb
Host smart-58e5dbe4-1519-4cca-8805-0d879655cfad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458190645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2458190645
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.785923385
Short name T334
Test name
Test status
Simulation time 99895294 ps
CPU time 1.67 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 198124 kb
Host smart-e4a35c55-9573-43c1-a37d-e2ea2f5bc7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785923385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.785923385
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3310648839
Short name T665
Test name
Test status
Simulation time 170595941 ps
CPU time 0.88 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:06 PM PST 24
Peak memory 195200 kb
Host smart-46041082-8d39-4a78-b9bc-ba5edf2bd3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310648839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3310648839
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3443307213
Short name T511
Test name
Test status
Simulation time 36172318 ps
CPU time 1.1 seconds
Started Feb 21 03:03:03 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 195912 kb
Host smart-5ffb6b42-8790-4b11-8679-56b34cd98dea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443307213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3443307213
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3401648077
Short name T593
Test name
Test status
Simulation time 53820556425 ps
CPU time 190.51 seconds
Started Feb 21 03:03:09 PM PST 24
Finished Feb 21 03:06:19 PM PST 24
Peak memory 198188 kb
Host smart-3ed3d785-e1ba-434a-99a3-768d7e7dc354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401648077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3401648077
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2587265151
Short name T402
Test name
Test status
Simulation time 22952945342 ps
CPU time 520.29 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:11:53 PM PST 24
Peak memory 198356 kb
Host smart-5d89c013-c8f4-482c-9d88-37caed12c8a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2587265151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2587265151
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.768163255
Short name T711
Test name
Test status
Simulation time 13275319 ps
CPU time 0.58 seconds
Started Feb 21 03:03:09 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 194120 kb
Host smart-21d4b42a-aac4-4c95-b630-4b6cf05a6694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768163255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.768163255
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1071966197
Short name T151
Test name
Test status
Simulation time 45985789 ps
CPU time 1.02 seconds
Started Feb 21 03:03:20 PM PST 24
Finished Feb 21 03:03:21 PM PST 24
Peak memory 196772 kb
Host smart-365def04-7f36-4671-aac6-b361fadea2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071966197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1071966197
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.867132885
Short name T204
Test name
Test status
Simulation time 129617225 ps
CPU time 3.21 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:09 PM PST 24
Peak memory 195948 kb
Host smart-051711a1-aa45-4d76-9ace-54ef8c5e29c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867132885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.867132885
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3804131613
Short name T301
Test name
Test status
Simulation time 75349016 ps
CPU time 0.76 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 194768 kb
Host smart-f46b1c67-f4a8-4065-8280-a3262ebc401b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804131613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3804131613
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1585907845
Short name T449
Test name
Test status
Simulation time 134694710 ps
CPU time 1.27 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:14 PM PST 24
Peak memory 196756 kb
Host smart-05c426b5-ff48-4ccf-8d8b-253f6fca1bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585907845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1585907845
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3757819085
Short name T415
Test name
Test status
Simulation time 60561579 ps
CPU time 2.34 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 198184 kb
Host smart-c15dd5d2-cc0c-440b-a2d8-cb16b8028cfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757819085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3757819085
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3773644263
Short name T321
Test name
Test status
Simulation time 323604146 ps
CPU time 3.63 seconds
Started Feb 21 03:03:13 PM PST 24
Finished Feb 21 03:03:17 PM PST 24
Peak memory 197504 kb
Host smart-9cc0c4fe-d833-413f-8d52-35e48e0c43e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773644263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3773644263
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2811141984
Short name T256
Test name
Test status
Simulation time 42463175 ps
CPU time 0.96 seconds
Started Feb 21 03:03:14 PM PST 24
Finished Feb 21 03:03:15 PM PST 24
Peak memory 195904 kb
Host smart-81936e9a-eecf-4082-85b3-b854a10f9528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811141984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2811141984
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3960150514
Short name T104
Test name
Test status
Simulation time 162149763 ps
CPU time 1.41 seconds
Started Feb 21 03:03:11 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 197076 kb
Host smart-dd5881b1-ac2f-4c96-8038-547c528c6c97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960150514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3960150514
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.422102393
Short name T109
Test name
Test status
Simulation time 169593094 ps
CPU time 1.22 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 198112 kb
Host smart-7040802f-011d-4d3b-9b19-a4215bcc2626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422102393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.422102393
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2617996603
Short name T201
Test name
Test status
Simulation time 139193226 ps
CPU time 0.85 seconds
Started Feb 21 03:03:04 PM PST 24
Finished Feb 21 03:03:06 PM PST 24
Peak memory 195988 kb
Host smart-8258e043-9b94-4b7d-984f-61319e6298e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617996603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2617996603
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.4175701290
Short name T170
Test name
Test status
Simulation time 99925736 ps
CPU time 1.07 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:12 PM PST 24
Peak memory 196308 kb
Host smart-c4fdd080-0c27-4a46-84c9-476765185baa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175701290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.4175701290
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.523056728
Short name T429
Test name
Test status
Simulation time 10576351521 ps
CPU time 118.66 seconds
Started Feb 21 03:03:13 PM PST 24
Finished Feb 21 03:05:12 PM PST 24
Peak memory 197748 kb
Host smart-124934be-4c2c-41f7-b2bb-91969c1c8587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523056728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.523056728
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2994843509
Short name T552
Test name
Test status
Simulation time 13239952 ps
CPU time 0.58 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:14 PM PST 24
Peak memory 193936 kb
Host smart-bef6dfe3-f0a4-4c2b-816b-ab7b8976e244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994843509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2994843509
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1409503953
Short name T499
Test name
Test status
Simulation time 25296141 ps
CPU time 0.67 seconds
Started Feb 21 03:03:06 PM PST 24
Finished Feb 21 03:03:07 PM PST 24
Peak memory 194772 kb
Host smart-4773c2c4-c750-4fee-9a8f-e1311edc7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409503953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1409503953
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.574337804
Short name T148
Test name
Test status
Simulation time 298379066 ps
CPU time 10.79 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:22 PM PST 24
Peak memory 198128 kb
Host smart-a6be36b8-52e1-4f11-b820-b8fc93101282
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574337804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.574337804
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1160329048
Short name T567
Test name
Test status
Simulation time 138210732 ps
CPU time 0.64 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 194532 kb
Host smart-3a8ec5d7-416d-4184-95c4-b528a77ea2d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160329048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1160329048
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1733286903
Short name T682
Test name
Test status
Simulation time 117877998 ps
CPU time 0.74 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 195480 kb
Host smart-9e6bdc98-489c-449c-b218-981e5fd30b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733286903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1733286903
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.870417012
Short name T107
Test name
Test status
Simulation time 313588935 ps
CPU time 3.42 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 197948 kb
Host smart-11f4af6b-75fb-4c48-be7a-1aafb6cf6a96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870417012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.870417012
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.842222281
Short name T604
Test name
Test status
Simulation time 177121343 ps
CPU time 2.93 seconds
Started Feb 21 03:03:11 PM PST 24
Finished Feb 21 03:03:15 PM PST 24
Peak memory 195904 kb
Host smart-e224857d-0270-4745-a0d5-a1993e41e636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842222281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
842222281
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3244567913
Short name T242
Test name
Test status
Simulation time 67231845 ps
CPU time 1.37 seconds
Started Feb 21 03:03:11 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 198168 kb
Host smart-a46c7fba-bb45-4abb-a18f-86de305822e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244567913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3244567913
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.630079281
Short name T614
Test name
Test status
Simulation time 86677313 ps
CPU time 1.11 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:03:09 PM PST 24
Peak memory 196312 kb
Host smart-175b0638-62b1-4061-b641-af17468ff96e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630079281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.630079281
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2609618890
Short name T470
Test name
Test status
Simulation time 967193705 ps
CPU time 4.04 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:16 PM PST 24
Peak memory 198068 kb
Host smart-f8a09623-1b50-4faa-a157-5a617777cd20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609618890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2609618890
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3845725276
Short name T399
Test name
Test status
Simulation time 135962017 ps
CPU time 1.14 seconds
Started Feb 21 03:03:15 PM PST 24
Finished Feb 21 03:03:17 PM PST 24
Peak memory 195888 kb
Host smart-b8595c68-9b98-4809-a2e7-e1951477e173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845725276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3845725276
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3229975995
Short name T121
Test name
Test status
Simulation time 193569333 ps
CPU time 1.07 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:09 PM PST 24
Peak memory 195656 kb
Host smart-5ea5f533-1cdc-447e-a5dd-f80b4964f867
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229975995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3229975995
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.196159969
Short name T624
Test name
Test status
Simulation time 9927699218 ps
CPU time 28.17 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 198284 kb
Host smart-10199fcb-0e85-4a63-9ec8-de1c518d2468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196159969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.196159969
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.610890054
Short name T487
Test name
Test status
Simulation time 24070322 ps
CPU time 0.62 seconds
Started Feb 21 03:03:27 PM PST 24
Finished Feb 21 03:03:28 PM PST 24
Peak memory 193944 kb
Host smart-fc70ca51-9726-4783-b229-7cffb39417b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610890054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.610890054
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3587574642
Short name T680
Test name
Test status
Simulation time 23260631 ps
CPU time 0.75 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 194792 kb
Host smart-d99cb030-b50c-4754-9d2e-870ffdd25472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587574642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3587574642
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2764909871
Short name T623
Test name
Test status
Simulation time 1467351866 ps
CPU time 4.75 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:15 PM PST 24
Peak memory 196052 kb
Host smart-5e44fd4f-9381-44bc-a768-d45e60d0dc02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764909871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2764909871
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3456316171
Short name T637
Test name
Test status
Simulation time 133978012 ps
CPU time 1.24 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 196496 kb
Host smart-2a04d29c-1d36-4f6b-8272-890180dbda88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456316171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3456316171
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.183283895
Short name T550
Test name
Test status
Simulation time 67948300 ps
CPU time 0.83 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:09 PM PST 24
Peak memory 195572 kb
Host smart-ebaf6c88-e417-43ac-b729-cb7fb434d28c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183283895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.183283895
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1649563955
Short name T537
Test name
Test status
Simulation time 383940371 ps
CPU time 2.52 seconds
Started Feb 21 03:03:08 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 198216 kb
Host smart-43cd927d-1f8c-46c6-b032-dbcd6e825f8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649563955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1649563955
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2493436527
Short name T638
Test name
Test status
Simulation time 32287472 ps
CPU time 0.92 seconds
Started Feb 21 03:03:11 PM PST 24
Finished Feb 21 03:03:12 PM PST 24
Peak memory 196228 kb
Host smart-46be557e-c1bb-4987-bd7e-e2529e1f1b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493436527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2493436527
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2467685520
Short name T263
Test name
Test status
Simulation time 27290158 ps
CPU time 0.72 seconds
Started Feb 21 03:03:15 PM PST 24
Finished Feb 21 03:03:17 PM PST 24
Peak memory 195364 kb
Host smart-4f31462d-7f13-4efe-8454-8b224738ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467685520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2467685520
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.996176364
Short name T576
Test name
Test status
Simulation time 103273641 ps
CPU time 1.13 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 195904 kb
Host smart-a7a03daa-561c-4a32-92d6-6215f1a2dbad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996176364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.996176364
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1100761173
Short name T619
Test name
Test status
Simulation time 158935236 ps
CPU time 2.74 seconds
Started Feb 21 03:03:24 PM PST 24
Finished Feb 21 03:03:28 PM PST 24
Peak memory 198080 kb
Host smart-d33270bd-f7aa-4f78-8574-5f4da6879a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100761173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1100761173
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.4169854875
Short name T536
Test name
Test status
Simulation time 419729910 ps
CPU time 0.93 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 197220 kb
Host smart-09f824b6-98ac-4bdb-9add-bf97541cf392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169854875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.4169854875
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.991410561
Short name T447
Test name
Test status
Simulation time 274551435 ps
CPU time 1.42 seconds
Started Feb 21 03:03:13 PM PST 24
Finished Feb 21 03:03:15 PM PST 24
Peak memory 196832 kb
Host smart-50629fbc-b111-4b4b-83cd-d2857c27b340
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991410561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.991410561
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2186614656
Short name T315
Test name
Test status
Simulation time 3416239966 ps
CPU time 86 seconds
Started Feb 21 03:03:13 PM PST 24
Finished Feb 21 03:04:40 PM PST 24
Peak memory 198208 kb
Host smart-ab03ae2a-d02f-490b-af44-7834dbbbdb04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186614656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2186614656
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.757906614
Short name T481
Test name
Test status
Simulation time 116447221850 ps
CPU time 910.46 seconds
Started Feb 21 03:03:13 PM PST 24
Finished Feb 21 03:18:24 PM PST 24
Peak memory 197852 kb
Host smart-65db9003-36d2-4b1f-a2a5-fd5d8cff46d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=757906614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.757906614
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.894091514
Short name T369
Test name
Test status
Simulation time 12457986 ps
CPU time 0.61 seconds
Started Feb 21 03:03:11 PM PST 24
Finished Feb 21 03:03:12 PM PST 24
Peak memory 194652 kb
Host smart-c7651201-6285-489a-9e0a-5d721116d72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894091514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.894091514
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3956520189
Short name T314
Test name
Test status
Simulation time 183224489 ps
CPU time 0.94 seconds
Started Feb 21 03:03:06 PM PST 24
Finished Feb 21 03:03:07 PM PST 24
Peak memory 195912 kb
Host smart-250035ae-e8f9-4857-ae6e-43659c569778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956520189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3956520189
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2930442831
Short name T454
Test name
Test status
Simulation time 1735716439 ps
CPU time 22.92 seconds
Started Feb 21 03:03:10 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 196684 kb
Host smart-645a097e-6a4b-4dd9-ab2e-d0656c4c45e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930442831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2930442831
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2277241481
Short name T330
Test name
Test status
Simulation time 51293283 ps
CPU time 0.92 seconds
Started Feb 21 03:03:21 PM PST 24
Finished Feb 21 03:03:22 PM PST 24
Peak memory 196940 kb
Host smart-472d9653-2937-4a92-96cf-7dfeb18c5de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277241481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2277241481
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1581451842
Short name T691
Test name
Test status
Simulation time 97569693 ps
CPU time 1.41 seconds
Started Feb 21 03:03:05 PM PST 24
Finished Feb 21 03:03:07 PM PST 24
Peak memory 197008 kb
Host smart-282adc93-32e4-495b-be8d-e37d98493a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581451842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1581451842
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1594187402
Short name T698
Test name
Test status
Simulation time 369394063 ps
CPU time 3.29 seconds
Started Feb 21 03:03:23 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 196364 kb
Host smart-50c2f3d4-1dea-4d1e-99c6-909b4184171e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594187402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1594187402
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1453928906
Short name T506
Test name
Test status
Simulation time 446593955 ps
CPU time 2.73 seconds
Started Feb 21 03:03:07 PM PST 24
Finished Feb 21 03:03:10 PM PST 24
Peak memory 198120 kb
Host smart-8e7e2501-fe39-4a0a-a719-b85050b48c11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453928906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1453928906
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3661515882
Short name T602
Test name
Test status
Simulation time 67251451 ps
CPU time 1.23 seconds
Started Feb 21 03:03:23 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 196004 kb
Host smart-ae85d421-06b6-45cd-bbf1-0c47f9006ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661515882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3661515882
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3545283148
Short name T419
Test name
Test status
Simulation time 18839172 ps
CPU time 0.68 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:03:13 PM PST 24
Peak memory 194944 kb
Host smart-b22ade9c-638c-4c17-81aa-7e17ec8f318d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545283148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3545283148
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2629314033
Short name T689
Test name
Test status
Simulation time 596468440 ps
CPU time 2.12 seconds
Started Feb 21 03:03:17 PM PST 24
Finished Feb 21 03:03:19 PM PST 24
Peak memory 198080 kb
Host smart-3ef39372-4ea2-4a2b-99a0-ff806b1ee9a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629314033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2629314033
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2536915078
Short name T358
Test name
Test status
Simulation time 77421253 ps
CPU time 1.08 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 195632 kb
Host smart-6f84872a-c9bc-47e4-8456-bb7a7dc69356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536915078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2536915078
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2245322738
Short name T293
Test name
Test status
Simulation time 150704646 ps
CPU time 1.07 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 195812 kb
Host smart-ae81a790-2a73-458f-8fea-4434b66431f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245322738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2245322738
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2079081572
Short name T441
Test name
Test status
Simulation time 7683633514 ps
CPU time 62.43 seconds
Started Feb 21 03:03:12 PM PST 24
Finished Feb 21 03:04:15 PM PST 24
Peak memory 198188 kb
Host smart-7e8f4cbf-56ed-4c49-aab9-69b4ca7ce640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079081572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2079081572
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.516284517
Short name T166
Test name
Test status
Simulation time 24915092 ps
CPU time 0.56 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:41 PM PST 24
Peak memory 194596 kb
Host smart-72dadcb0-0e13-4710-b923-8e73fb207b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516284517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.516284517
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1081371980
Short name T617
Test name
Test status
Simulation time 55408769 ps
CPU time 0.6 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:36 PM PST 24
Peak memory 194628 kb
Host smart-3e2a3018-278f-4f8e-9e9c-5a539d1421d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081371980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1081371980
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1510422379
Short name T154
Test name
Test status
Simulation time 223586254 ps
CPU time 5.58 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:28 PM PST 24
Peak memory 196920 kb
Host smart-c5cc58b4-775a-4282-b4c0-7611dee5617d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510422379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1510422379
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2674851683
Short name T228
Test name
Test status
Simulation time 243909895 ps
CPU time 0.93 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:45 PM PST 24
Peak memory 197844 kb
Host smart-16725ffe-49f7-42b7-83f7-2887070cca05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674851683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2674851683
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.919359386
Short name T214
Test name
Test status
Simulation time 37852441 ps
CPU time 0.71 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 194352 kb
Host smart-60865f46-eef1-4bcd-b498-60e088b7589b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919359386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.919359386
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2167078151
Short name T618
Test name
Test status
Simulation time 53291133 ps
CPU time 2.12 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 198096 kb
Host smart-e575c454-3e47-477e-b8c5-f8a524803ee1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167078151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2167078151
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.166043858
Short name T110
Test name
Test status
Simulation time 1657798411 ps
CPU time 2.27 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 196864 kb
Host smart-5bb9558e-dc8b-4f42-9806-ec02c0571ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166043858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
166043858
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.173818737
Short name T186
Test name
Test status
Simulation time 197990514 ps
CPU time 1.03 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 195852 kb
Host smart-6b81df16-e90d-4381-aa60-afafef85e88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173818737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.173818737
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3457849221
Short name T320
Test name
Test status
Simulation time 204810410 ps
CPU time 0.88 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 196728 kb
Host smart-8cdbc373-49d9-48ae-acf4-9b58d2c8ab4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457849221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3457849221
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.205111209
Short name T252
Test name
Test status
Simulation time 484662463 ps
CPU time 3.9 seconds
Started Feb 21 03:03:29 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 198080 kb
Host smart-69d85cf6-5e01-4d74-a3f2-02527921adca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205111209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.205111209
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3632972704
Short name T626
Test name
Test status
Simulation time 122012998 ps
CPU time 1.05 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:24 PM PST 24
Peak memory 196336 kb
Host smart-54df1637-1ee2-4d59-818a-1a0df4286d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632972704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3632972704
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3259900485
Short name T145
Test name
Test status
Simulation time 265148963 ps
CPU time 1.46 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:24 PM PST 24
Peak memory 196812 kb
Host smart-5536e2aa-9683-4280-87ef-d472ea006636
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259900485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3259900485
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3587503157
Short name T523
Test name
Test status
Simulation time 16253120804 ps
CPU time 92.37 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:05:05 PM PST 24
Peak memory 198192 kb
Host smart-c688a63b-4376-46e5-bc49-e1b6c282eb4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587503157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3587503157
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.477938903
Short name T62
Test name
Test status
Simulation time 73795031805 ps
CPU time 1777.83 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:33:18 PM PST 24
Peak memory 198348 kb
Host smart-abd42450-080e-4c3a-b4f5-50907f72c675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=477938903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.477938903
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.853145717
Short name T688
Test name
Test status
Simulation time 45585388 ps
CPU time 0.6 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 194128 kb
Host smart-d7966d19-03ec-46b4-a794-e824c8e49f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853145717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.853145717
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1241906203
Short name T673
Test name
Test status
Simulation time 30372731 ps
CPU time 0.86 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 196340 kb
Host smart-34f24175-f19c-44c0-b04a-37039c084c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241906203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1241906203
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2815591436
Short name T105
Test name
Test status
Simulation time 358572426 ps
CPU time 4.11 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:39 PM PST 24
Peak memory 196092 kb
Host smart-8f838e76-9b76-4b54-ac18-d193c30545a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815591436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2815591436
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2312653787
Short name T649
Test name
Test status
Simulation time 18460538 ps
CPU time 0.62 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 195208 kb
Host smart-07a57c15-a175-400e-b4ad-b181025414a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312653787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2312653787
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2771698750
Short name T55
Test name
Test status
Simulation time 377117490 ps
CPU time 1.55 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 198172 kb
Host smart-b00d86a1-9ab8-49a2-9eae-aecfcc4a753f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771698750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2771698750
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.385033313
Short name T438
Test name
Test status
Simulation time 25234085 ps
CPU time 1.04 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:36 PM PST 24
Peak memory 196068 kb
Host smart-7f203287-b5bb-470b-8ac1-2cb0cb37940a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385033313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.385033313
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2485572289
Short name T159
Test name
Test status
Simulation time 110856588 ps
CPU time 1.78 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 196840 kb
Host smart-3e44771a-ba0b-4499-8b3a-2b32103f6762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485572289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2485572289
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1556208884
Short name T240
Test name
Test status
Simulation time 74305583 ps
CPU time 0.9 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 196732 kb
Host smart-4ba17728-cf46-421b-b5d6-9a90a6c17be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556208884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1556208884
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2173876626
Short name T119
Test name
Test status
Simulation time 57309420 ps
CPU time 1.27 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 196716 kb
Host smart-ef82837d-be8b-4b42-bddc-02afbb00febe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173876626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2173876626
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2106731136
Short name T625
Test name
Test status
Simulation time 111049259 ps
CPU time 1.95 seconds
Started Feb 21 03:03:34 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 198076 kb
Host smart-1e141d04-aa38-4d65-9435-8cf2f4bfa80d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106731136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2106731136
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3231744033
Short name T337
Test name
Test status
Simulation time 92881939 ps
CPU time 0.96 seconds
Started Feb 21 03:03:20 PM PST 24
Finished Feb 21 03:03:21 PM PST 24
Peak memory 196424 kb
Host smart-e1089551-e26d-4c40-852d-992ffca66e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231744033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3231744033
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3492082254
Short name T488
Test name
Test status
Simulation time 65424627 ps
CPU time 1.17 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 195852 kb
Host smart-d3bfdb41-938d-4dc8-9dce-740350896473
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492082254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3492082254
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2418266719
Short name T563
Test name
Test status
Simulation time 9068458848 ps
CPU time 102.66 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:05:20 PM PST 24
Peak memory 198284 kb
Host smart-3895e72a-a3a9-420d-bf52-9e8b465146b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418266719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2418266719
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3082440511
Short name T286
Test name
Test status
Simulation time 24711335 ps
CPU time 0.56 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:10 PM PST 24
Peak memory 193900 kb
Host smart-21e966c4-e8ab-48e6-aa90-b2655f6a3047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082440511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3082440511
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3213955648
Short name T412
Test name
Test status
Simulation time 172762198 ps
CPU time 0.91 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 197080 kb
Host smart-82d94059-e7ca-4837-8f65-b2ee031a91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213955648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3213955648
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3115971102
Short name T529
Test name
Test status
Simulation time 898971401 ps
CPU time 5.88 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 196344 kb
Host smart-d0cd6d15-fb70-4fe7-a0ef-9ee50b712791
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115971102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3115971102
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3351151007
Short name T115
Test name
Test status
Simulation time 272768878 ps
CPU time 0.94 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 197752 kb
Host smart-5cb36bd0-73f9-4318-9dca-10e4039c09e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351151007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3351151007
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2054714672
Short name T475
Test name
Test status
Simulation time 59799327 ps
CPU time 0.94 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 196196 kb
Host smart-df554c53-8805-4b01-8dec-851b4da27b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054714672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2054714672
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2425790135
Short name T32
Test name
Test status
Simulation time 75365140 ps
CPU time 3.17 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 198168 kb
Host smart-6b8e537a-f21b-4441-9d25-de8a58a7fd41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425790135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2425790135
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.607604519
Short name T114
Test name
Test status
Simulation time 93896031 ps
CPU time 2.5 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 197268 kb
Host smart-f9b9e5a9-c186-4d95-b4cf-f9dd7f5f8c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607604519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.607604519
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2338849805
Short name T512
Test name
Test status
Simulation time 63912904 ps
CPU time 1.37 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 196604 kb
Host smart-8a70075f-cefe-48a2-b748-266ce8117df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338849805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2338849805
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1144734130
Short name T188
Test name
Test status
Simulation time 43006041 ps
CPU time 0.97 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 196100 kb
Host smart-cbccbdbb-4b38-48b6-9f43-51e5b7e97ec8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144734130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1144734130
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1688913278
Short name T150
Test name
Test status
Simulation time 66691135 ps
CPU time 1.65 seconds
Started Feb 21 03:02:11 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 198024 kb
Host smart-da8131ad-6316-4477-ade9-21f7ff5e164f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688913278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1688913278
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.120990755
Short name T40
Test name
Test status
Simulation time 34568551 ps
CPU time 0.81 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 213780 kb
Host smart-72dadbae-7458-4743-9e5b-82ca11118c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120990755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.120990755
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.927208924
Short name T282
Test name
Test status
Simulation time 93953614 ps
CPU time 1.26 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 195960 kb
Host smart-c7f4ae6c-c9ff-411c-8495-547dafd20165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927208924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.927208924
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.399588501
Short name T465
Test name
Test status
Simulation time 276420444 ps
CPU time 1.26 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 195884 kb
Host smart-1609a3f9-0fd6-4e30-9b5b-8dbbd596e9db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399588501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.399588501
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3038466110
Short name T2
Test name
Test status
Simulation time 37781925388 ps
CPU time 199.81 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:05:37 PM PST 24
Peak memory 198204 kb
Host smart-61292297-f8f8-401b-8fc3-ca654f6cd47d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038466110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3038466110
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2965468718
Short name T535
Test name
Test status
Simulation time 171555181844 ps
CPU time 1172.92 seconds
Started Feb 21 03:02:09 PM PST 24
Finished Feb 21 03:21:43 PM PST 24
Peak memory 198412 kb
Host smart-dcffabbe-9419-4d10-a718-6222100c5d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2965468718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2965468718
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2651575111
Short name T287
Test name
Test status
Simulation time 42639592 ps
CPU time 0.58 seconds
Started Feb 21 03:03:19 PM PST 24
Finished Feb 21 03:03:20 PM PST 24
Peak memory 193976 kb
Host smart-0146f849-4300-4237-a23d-940b84c4c1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651575111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2651575111
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1723648414
Short name T120
Test name
Test status
Simulation time 24490565 ps
CPU time 0.75 seconds
Started Feb 21 03:03:28 PM PST 24
Finished Feb 21 03:03:29 PM PST 24
Peak memory 195900 kb
Host smart-8fe2ba41-849f-46cd-819a-d39920e5c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723648414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1723648414
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3074229731
Short name T373
Test name
Test status
Simulation time 1792831492 ps
CPU time 12.53 seconds
Started Feb 21 03:03:29 PM PST 24
Finished Feb 21 03:03:41 PM PST 24
Peak memory 195628 kb
Host smart-3b5903ad-2471-4302-9427-28892c0913b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074229731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3074229731
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.4182289576
Short name T676
Test name
Test status
Simulation time 202751321 ps
CPU time 0.74 seconds
Started Feb 21 03:03:24 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 194740 kb
Host smart-dd913805-0fc6-44f7-9cee-c998d795996e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182289576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4182289576
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.18822332
Short name T479
Test name
Test status
Simulation time 87538551 ps
CPU time 1.27 seconds
Started Feb 21 03:03:18 PM PST 24
Finished Feb 21 03:03:20 PM PST 24
Peak memory 196308 kb
Host smart-38d78fc9-9f9d-4aa6-b0d7-ff05a62b9be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.18822332
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.368461876
Short name T708
Test name
Test status
Simulation time 51742286 ps
CPU time 1.86 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 198228 kb
Host smart-c6325062-e8ae-40e2-b0e8-97ec4652ef9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368461876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.368461876
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1517028665
Short name T278
Test name
Test status
Simulation time 388359242 ps
CPU time 2.38 seconds
Started Feb 21 03:03:23 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 195852 kb
Host smart-363051d4-e68b-4575-8ab0-e7530cbcbca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517028665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1517028665
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.134968814
Short name T172
Test name
Test status
Simulation time 132176783 ps
CPU time 1.21 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 197184 kb
Host smart-28557b87-ee95-47ce-b614-dec2f61e3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134968814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.134968814
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2367126216
Short name T123
Test name
Test status
Simulation time 116361588 ps
CPU time 1.32 seconds
Started Feb 21 03:03:29 PM PST 24
Finished Feb 21 03:03:31 PM PST 24
Peak memory 198168 kb
Host smart-6a173fab-3b0e-4398-b453-144b8a2d164a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367126216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2367126216
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2264547235
Short name T173
Test name
Test status
Simulation time 102813187 ps
CPU time 4.5 seconds
Started Feb 21 03:03:28 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 198056 kb
Host smart-3123da39-a13a-4814-accb-c7b42cb3fe6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264547235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2264547235
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1509620967
Short name T670
Test name
Test status
Simulation time 90518000 ps
CPU time 0.98 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 195980 kb
Host smart-963a47e0-c970-4b64-91ea-41f7057f44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509620967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1509620967
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1415724215
Short name T52
Test name
Test status
Simulation time 57906027 ps
CPU time 1.06 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 196316 kb
Host smart-e87ad994-f028-4e1d-b926-ce4e166a62a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415724215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1415724215
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1924945391
Short name T265
Test name
Test status
Simulation time 6521204307 ps
CPU time 83.1 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:04:49 PM PST 24
Peak memory 198220 kb
Host smart-0e56c131-be51-472d-b22b-2d8b3d880840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924945391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1924945391
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4079802701
Short name T180
Test name
Test status
Simulation time 72687097 ps
CPU time 0.57 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 194636 kb
Host smart-c979acbc-6906-4ccc-afc1-8141d0e61568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079802701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4079802701
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3206633120
Short name T696
Test name
Test status
Simulation time 57339996 ps
CPU time 0.77 seconds
Started Feb 21 03:03:29 PM PST 24
Finished Feb 21 03:03:30 PM PST 24
Peak memory 195276 kb
Host smart-beb7fe7a-81a1-4594-aadc-8c93043683bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206633120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3206633120
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1495521033
Short name T421
Test name
Test status
Simulation time 3177959909 ps
CPU time 24.4 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:04:05 PM PST 24
Peak memory 198220 kb
Host smart-b3524724-acb4-4cba-bfcf-62225ad7675d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495521033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1495521033
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3608950307
Short name T526
Test name
Test status
Simulation time 271655165 ps
CPU time 0.84 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:36 PM PST 24
Peak memory 196048 kb
Host smart-62c62ab7-e547-42d2-9e07-1313762ed77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608950307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3608950307
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.466950680
Short name T335
Test name
Test status
Simulation time 108256500 ps
CPU time 1.47 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:03:43 PM PST 24
Peak memory 197240 kb
Host smart-009f1db7-f0d2-4b1f-be1a-07bf70622d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466950680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.466950680
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3693782787
Short name T608
Test name
Test status
Simulation time 53777408 ps
CPU time 2.13 seconds
Started Feb 21 03:03:31 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 198152 kb
Host smart-f1618813-5f3b-478c-9d36-b00c6f1cb236
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693782787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3693782787
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3007455395
Short name T222
Test name
Test status
Simulation time 375115583 ps
CPU time 2.26 seconds
Started Feb 21 03:03:21 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 198216 kb
Host smart-00de5b3f-5ef8-4e6c-92ac-9673151ea639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007455395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3007455395
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2611753595
Short name T647
Test name
Test status
Simulation time 44783583 ps
CPU time 1.15 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 196976 kb
Host smart-27733355-ec66-4a59-8d85-0bb4dae22d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611753595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2611753595
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.733027374
Short name T516
Test name
Test status
Simulation time 90797758 ps
CPU time 1.04 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 196060 kb
Host smart-846548a0-e0ab-4145-a350-d574cb5ab757
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733027374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.733027374
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.508172198
Short name T184
Test name
Test status
Simulation time 195787984 ps
CPU time 2.61 seconds
Started Feb 21 03:03:22 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 198296 kb
Host smart-e4de9dbe-b568-42d3-bb22-ee16cc260f64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508172198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.508172198
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2409772825
Short name T381
Test name
Test status
Simulation time 159356718 ps
CPU time 0.97 seconds
Started Feb 21 03:03:26 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 195784 kb
Host smart-98371f0d-6063-4393-99fd-2b7474eaa281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409772825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2409772825
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2247543923
Short name T372
Test name
Test status
Simulation time 132195904 ps
CPU time 1.03 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:36 PM PST 24
Peak memory 195756 kb
Host smart-c9e40dc1-ac67-4224-94da-fdc21e04bbf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247543923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2247543923
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3319588746
Short name T257
Test name
Test status
Simulation time 15689765490 ps
CPU time 193.65 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:06:39 PM PST 24
Peak memory 198228 kb
Host smart-5d004f02-aaec-44d8-be78-38f00b44692f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319588746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3319588746
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.51533976
Short name T451
Test name
Test status
Simulation time 47689549 ps
CPU time 0.55 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:41 PM PST 24
Peak memory 193932 kb
Host smart-7257206b-bd23-4291-94b1-3e0594694df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51533976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.51533976
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1291634750
Short name T100
Test name
Test status
Simulation time 215445777 ps
CPU time 0.91 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 195968 kb
Host smart-6a8bde61-cf4f-417f-8c04-3f0aca2df903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291634750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1291634750
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.989626640
Short name T298
Test name
Test status
Simulation time 3359455841 ps
CPU time 27.05 seconds
Started Feb 21 03:03:27 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 196696 kb
Host smart-21f2b213-3001-4bf9-a577-2aae5a118285
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989626640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.989626640
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3072132389
Short name T343
Test name
Test status
Simulation time 199296072 ps
CPU time 0.84 seconds
Started Feb 21 03:03:29 PM PST 24
Finished Feb 21 03:03:30 PM PST 24
Peak memory 195908 kb
Host smart-1b422e09-70ce-4937-85fc-f11551a9651d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072132389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3072132389
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1387437243
Short name T436
Test name
Test status
Simulation time 197319881 ps
CPU time 1.39 seconds
Started Feb 21 03:03:28 PM PST 24
Finished Feb 21 03:03:30 PM PST 24
Peak memory 197056 kb
Host smart-65891ed2-f232-41d3-8c09-d1ec992c3940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387437243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1387437243
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1387101231
Short name T15
Test name
Test status
Simulation time 78397870 ps
CPU time 3.06 seconds
Started Feb 21 03:03:34 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 196412 kb
Host smart-ec5e34a0-1b78-49ba-972b-1e9e4e75e61a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387101231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1387101231
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3610705703
Short name T519
Test name
Test status
Simulation time 211493971 ps
CPU time 1.19 seconds
Started Feb 21 03:03:26 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 195764 kb
Host smart-27c40ba9-9b7c-472c-9eb6-ac380d78d4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610705703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3610705703
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1945507323
Short name T133
Test name
Test status
Simulation time 49382058 ps
CPU time 1.11 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:44 PM PST 24
Peak memory 196608 kb
Host smart-106a501e-dfe2-4cfa-a3af-2a1bd3386534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945507323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1945507323
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1720217013
Short name T243
Test name
Test status
Simulation time 67461259 ps
CPU time 0.68 seconds
Started Feb 21 03:03:35 PM PST 24
Finished Feb 21 03:03:36 PM PST 24
Peak memory 195160 kb
Host smart-e17170cb-b7b7-4a34-9414-9c5bf1e964c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720217013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1720217013
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.858561842
Short name T574
Test name
Test status
Simulation time 377203950 ps
CPU time 4.59 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 198116 kb
Host smart-2388d51a-3363-4a9b-a421-18fd5c888c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858561842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.858561842
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1210851436
Short name T571
Test name
Test status
Simulation time 51980105 ps
CPU time 0.95 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 195636 kb
Host smart-6c3a2230-220b-4cb0-ba64-7ee360cdca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210851436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1210851436
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3933821429
Short name T564
Test name
Test status
Simulation time 84723192 ps
CPU time 1.16 seconds
Started Feb 21 03:03:37 PM PST 24
Finished Feb 21 03:03:39 PM PST 24
Peak memory 195580 kb
Host smart-52f197fb-2086-4661-843f-6b37f600e2b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933821429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3933821429
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.447368835
Short name T60
Test name
Test status
Simulation time 6786602439 ps
CPU time 114.03 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:05:19 PM PST 24
Peak memory 198236 kb
Host smart-1848f806-a765-4554-8d68-8acec149d8a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447368835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.447368835
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1318744346
Short name T508
Test name
Test status
Simulation time 29227599360 ps
CPU time 715.96 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:15:36 PM PST 24
Peak memory 198372 kb
Host smart-820c88df-2f84-4a4b-ad8f-b5330ecfedc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1318744346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1318744346
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1476306891
Short name T528
Test name
Test status
Simulation time 41177475 ps
CPU time 0.57 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 193976 kb
Host smart-2d31dc52-f5df-4f1c-9ab3-79b485b70dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476306891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1476306891
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.926706399
Short name T394
Test name
Test status
Simulation time 60980870 ps
CPU time 0.65 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 194004 kb
Host smart-48c0d725-0a4b-4cc2-bab8-1f14c3f2611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926706399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.926706399
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3500869728
Short name T504
Test name
Test status
Simulation time 1711239397 ps
CPU time 11.7 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:04:04 PM PST 24
Peak memory 196980 kb
Host smart-bb672bd7-a6c4-42f0-8f86-c9fcae483c56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500869728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3500869728
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2572812572
Short name T687
Test name
Test status
Simulation time 61625896 ps
CPU time 0.94 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 196700 kb
Host smart-c94c38eb-8fe2-4a46-abfa-a8fc1224884d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572812572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2572812572
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.420316889
Short name T336
Test name
Test status
Simulation time 41916881 ps
CPU time 0.86 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 197556 kb
Host smart-b235e5dc-59e2-4ef7-bacd-d71ff541321c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420316889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.420316889
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.303111071
Short name T380
Test name
Test status
Simulation time 213253089 ps
CPU time 2.16 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 198140 kb
Host smart-5223acff-226b-49cc-9d02-4b37adb70371
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303111071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.303111071
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2125952357
Short name T398
Test name
Test status
Simulation time 593251290 ps
CPU time 3.01 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 197176 kb
Host smart-2c714737-4e5d-47d4-81b4-106e8085aa7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125952357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2125952357
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3919034885
Short name T697
Test name
Test status
Simulation time 80151826 ps
CPU time 1 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 196060 kb
Host smart-16c35cdb-fc46-4e21-baaa-434fc171cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919034885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3919034885
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.452965615
Short name T153
Test name
Test status
Simulation time 223949376 ps
CPU time 1.09 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 196068 kb
Host smart-efb468e3-e7f9-4280-9605-0101842cd271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452965615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.452965615
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1391545283
Short name T3
Test name
Test status
Simulation time 2174763040 ps
CPU time 6.64 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 198156 kb
Host smart-dd8936b4-1098-41a1-b454-364340c0f09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391545283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1391545283
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4123566836
Short name T279
Test name
Test status
Simulation time 142227524 ps
CPU time 1.12 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 195604 kb
Host smart-41249a72-3229-4f56-813b-c566fb45ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123566836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4123566836
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.22707927
Short name T333
Test name
Test status
Simulation time 56420419 ps
CPU time 1.03 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 196324 kb
Host smart-0631f3ac-97af-4a0a-b4b4-009388981459
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.22707927
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3341367386
Short name T139
Test name
Test status
Simulation time 15318520949 ps
CPU time 95.25 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:05:25 PM PST 24
Peak memory 198300 kb
Host smart-16c015da-d84c-4cb4-8c83-92719366e32f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341367386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3341367386
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.439444806
Short name T359
Test name
Test status
Simulation time 29122468 ps
CPU time 0.59 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 193936 kb
Host smart-fc0c0201-0b31-4c1a-825e-9336229d0c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439444806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.439444806
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2275786619
Short name T466
Test name
Test status
Simulation time 30864050 ps
CPU time 0.93 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 195932 kb
Host smart-04e358e9-68e0-4e9e-a1be-ce63434161fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275786619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2275786619
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1984337570
Short name T206
Test name
Test status
Simulation time 1207279165 ps
CPU time 20.47 seconds
Started Feb 21 03:03:24 PM PST 24
Finished Feb 21 03:03:45 PM PST 24
Peak memory 197264 kb
Host smart-33531e0f-bd89-489b-b7f5-544400464a28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984337570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1984337570
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.303170459
Short name T370
Test name
Test status
Simulation time 37128494 ps
CPU time 0.71 seconds
Started Feb 21 03:03:24 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 194752 kb
Host smart-9952e5f8-8e19-4504-9ca6-436d2dbd0844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303170459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.303170459
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1298481347
Short name T309
Test name
Test status
Simulation time 576858472 ps
CPU time 1.55 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 198100 kb
Host smart-012f72ee-f996-4797-9fd2-48b3a4f53925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298481347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1298481347
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2600944634
Short name T434
Test name
Test status
Simulation time 59701224 ps
CPU time 2.49 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 198192 kb
Host smart-d0c8f86a-a0e8-4e05-b34a-4f7f992eea68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600944634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2600944634
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2033104703
Short name T213
Test name
Test status
Simulation time 276593478 ps
CPU time 1.52 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 196500 kb
Host smart-b652064c-0bef-4afb-896f-61c228bf45bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033104703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2033104703
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.946727452
Short name T596
Test name
Test status
Simulation time 253310989 ps
CPU time 1.23 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 195928 kb
Host smart-9f0ec482-8eff-48e7-a556-9db9c2464ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946727452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.946727452
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1252547775
Short name T667
Test name
Test status
Simulation time 98913564 ps
CPU time 0.7 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 196164 kb
Host smart-c9ee6281-c82a-493c-8041-88d4f3dc951b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252547775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1252547775
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4060380470
Short name T254
Test name
Test status
Simulation time 235858601 ps
CPU time 4.22 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 198084 kb
Host smart-134ceb15-a8ca-400f-add9-2e3b2f0efadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060380470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4060380470
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.314989582
Short name T132
Test name
Test status
Simulation time 318722170 ps
CPU time 1.09 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 195816 kb
Host smart-017c634c-c5d6-45b5-85a6-53208fb7a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314989582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.314989582
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.611620059
Short name T269
Test name
Test status
Simulation time 131196918 ps
CPU time 1 seconds
Started Feb 21 03:03:26 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 195852 kb
Host smart-3e62292d-78f3-465a-b2a4-0d341ecc66c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611620059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.611620059
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3876147187
Short name T239
Test name
Test status
Simulation time 67023593396 ps
CPU time 180.37 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:06:51 PM PST 24
Peak memory 198260 kb
Host smart-1f40f4d4-e064-4789-af87-e759de24293e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876147187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3876147187
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3183290224
Short name T357
Test name
Test status
Simulation time 35477140 ps
CPU time 0.6 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 193984 kb
Host smart-eccf685b-66c3-4ccb-bb7d-afa5fac05a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183290224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3183290224
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2402171503
Short name T248
Test name
Test status
Simulation time 33806915 ps
CPU time 0.63 seconds
Started Feb 21 03:03:24 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 193980 kb
Host smart-292802f6-51ea-4bf2-ad24-f48aeb51b7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402171503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2402171503
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2441690147
Short name T332
Test name
Test status
Simulation time 625381140 ps
CPU time 5.08 seconds
Started Feb 21 03:03:26 PM PST 24
Finished Feb 21 03:03:31 PM PST 24
Peak memory 196848 kb
Host smart-513d6f2c-00c8-46bf-871d-b8aa6ec70d7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441690147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2441690147
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.258417222
Short name T460
Test name
Test status
Simulation time 122309202 ps
CPU time 0.88 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:40 PM PST 24
Peak memory 197264 kb
Host smart-f90d11bc-a0ea-41f5-a4f4-132152fb4265
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258417222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.258417222
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2707896593
Short name T168
Test name
Test status
Simulation time 343128037 ps
CPU time 1 seconds
Started Feb 21 03:03:26 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 196576 kb
Host smart-f7f2a3cc-29b0-4417-b138-271304c721db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707896593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2707896593
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3216329551
Short name T223
Test name
Test status
Simulation time 332765355 ps
CPU time 3.53 seconds
Started Feb 21 03:03:27 PM PST 24
Finished Feb 21 03:03:31 PM PST 24
Peak memory 198168 kb
Host smart-01cf5be6-327b-43e2-b1e8-2b91f44a61c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216329551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3216329551
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1846792387
Short name T264
Test name
Test status
Simulation time 66903137 ps
CPU time 1.44 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:44 PM PST 24
Peak memory 196952 kb
Host smart-151d9fd4-03b8-4be7-9743-fc8cc83b1711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846792387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1846792387
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1254168433
Short name T171
Test name
Test status
Simulation time 31680266 ps
CPU time 1.18 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 197164 kb
Host smart-8fcb3897-8b3e-4393-860d-38d5a5fbec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254168433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1254168433
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3362082961
Short name T706
Test name
Test status
Simulation time 23235670 ps
CPU time 0.73 seconds
Started Feb 21 03:03:32 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 194420 kb
Host smart-b6f37089-99ca-446a-878d-cf767ef2fb65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362082961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3362082961
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3397464094
Short name T631
Test name
Test status
Simulation time 152634136 ps
CPU time 1.5 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 198100 kb
Host smart-4082cfee-80e5-4110-8c58-e9962e9d72e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397464094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3397464094
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2975429473
Short name T169
Test name
Test status
Simulation time 99036389 ps
CPU time 1.42 seconds
Started Feb 21 03:03:27 PM PST 24
Finished Feb 21 03:03:29 PM PST 24
Peak memory 195680 kb
Host smart-ec81608d-aee0-4d5e-9bd5-737f6183e1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975429473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2975429473
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4238180034
Short name T376
Test name
Test status
Simulation time 239352881 ps
CPU time 0.9 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 195368 kb
Host smart-5f19ac90-2a25-4a21-8b16-0561e3168153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238180034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4238180034
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1298136014
Short name T351
Test name
Test status
Simulation time 28387997874 ps
CPU time 175.98 seconds
Started Feb 21 03:03:25 PM PST 24
Finished Feb 21 03:06:21 PM PST 24
Peak memory 198412 kb
Host smart-0cdfbc44-3930-4403-8a96-049bd303479e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298136014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1298136014
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4131229702
Short name T34
Test name
Test status
Simulation time 167732332480 ps
CPU time 1382.58 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:26:52 PM PST 24
Peak memory 198436 kb
Host smart-8bf48fd3-94ee-4e9b-a392-ca3564d95a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4131229702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4131229702
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.636271415
Short name T236
Test name
Test status
Simulation time 17958685 ps
CPU time 0.57 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:41 PM PST 24
Peak memory 194660 kb
Host smart-ccdf277d-1e06-409d-93cb-3eb86616b84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636271415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.636271415
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.321016429
Short name T580
Test name
Test status
Simulation time 52280717 ps
CPU time 1.06 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 195860 kb
Host smart-f06ef7b7-0213-4ec4-ba4b-6e362c8c6c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321016429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.321016429
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3528277814
Short name T198
Test name
Test status
Simulation time 747711842 ps
CPU time 19.67 seconds
Started Feb 21 03:03:36 PM PST 24
Finished Feb 21 03:03:56 PM PST 24
Peak memory 196840 kb
Host smart-8184c7b2-01b1-4a1f-9590-31779ebb966c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528277814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3528277814
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4267989470
Short name T636
Test name
Test status
Simulation time 229111974 ps
CPU time 0.82 seconds
Started Feb 21 03:03:36 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 195872 kb
Host smart-fdeb0fd3-fbae-4390-9985-ae964bbd546d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267989470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4267989470
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.747949759
Short name T469
Test name
Test status
Simulation time 289120051 ps
CPU time 1.24 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 196180 kb
Host smart-b33e20fd-7538-4eec-b378-9de6ff17bc04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747949759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.747949759
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1097880099
Short name T585
Test name
Test status
Simulation time 344783264 ps
CPU time 1.94 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 198112 kb
Host smart-3a5b302d-2f62-453a-94dc-06fce91fccaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097880099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1097880099
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3438923383
Short name T177
Test name
Test status
Simulation time 310766969 ps
CPU time 1.78 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 197020 kb
Host smart-15def18d-8f18-4912-8f4b-59719a78a4cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438923383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3438923383
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.417094996
Short name T383
Test name
Test status
Simulation time 46100314 ps
CPU time 0.85 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 195552 kb
Host smart-881c2cee-4bcf-437a-904d-616c3332d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417094996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.417094996
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.422692776
Short name T456
Test name
Test status
Simulation time 35765714 ps
CPU time 1.05 seconds
Started Feb 21 03:03:36 PM PST 24
Finished Feb 21 03:03:37 PM PST 24
Peak memory 196132 kb
Host smart-890009a8-35bf-4c84-84c5-22cc5c5d7c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422692776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.422692776
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2313156406
Short name T299
Test name
Test status
Simulation time 1043142337 ps
CPU time 4.3 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 198136 kb
Host smart-b9aed012-dea6-4dd5-a529-20a11bf54d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313156406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2313156406
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3651263137
Short name T437
Test name
Test status
Simulation time 86894560 ps
CPU time 0.89 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 195836 kb
Host smart-c7ca0a89-1e77-43eb-9652-c890368ac2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651263137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3651263137
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1898707235
Short name T117
Test name
Test status
Simulation time 126072684 ps
CPU time 0.76 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:03:45 PM PST 24
Peak memory 196060 kb
Host smart-1cc92756-c10b-4617-9c96-1702f74234dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898707235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1898707235
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.756404946
Short name T378
Test name
Test status
Simulation time 7054030502 ps
CPU time 108.92 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:05:39 PM PST 24
Peak memory 198256 kb
Host smart-0d819f61-078a-4a8e-9918-46f6d9a212a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756404946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.756404946
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.941408388
Short name T392
Test name
Test status
Simulation time 41706797554 ps
CPU time 968.63 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:19:58 PM PST 24
Peak memory 198428 kb
Host smart-a0068594-2306-4c3c-a05d-bbf748a4279e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=941408388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.941408388
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2516525039
Short name T364
Test name
Test status
Simulation time 17230060 ps
CPU time 0.57 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 193932 kb
Host smart-85641177-08be-4888-a6cb-49d72928bbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516525039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2516525039
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3400697783
Short name T233
Test name
Test status
Simulation time 276175057 ps
CPU time 0.73 seconds
Started Feb 21 03:03:41 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 195152 kb
Host smart-23c1bea2-30a2-4638-b131-ef77c08f7d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400697783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3400697783
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1766123914
Short name T103
Test name
Test status
Simulation time 420246308 ps
CPU time 21.52 seconds
Started Feb 21 03:03:36 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 197060 kb
Host smart-7b4bf315-1b96-4f25-8fd1-108f557dc026
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766123914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1766123914
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3295866433
Short name T344
Test name
Test status
Simulation time 144916237 ps
CPU time 1.06 seconds
Started Feb 21 03:03:31 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 196700 kb
Host smart-c3cd4025-f539-4911-89d4-1cfad46961fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295866433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3295866433
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3561791597
Short name T296
Test name
Test status
Simulation time 83584633 ps
CPU time 1.32 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:45 PM PST 24
Peak memory 196632 kb
Host smart-34f9b0d7-a1d2-477d-acbc-282c577b2034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561791597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3561791597
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2935808096
Short name T261
Test name
Test status
Simulation time 309934949 ps
CPU time 3.13 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 198244 kb
Host smart-3b3fad22-431a-48a3-894a-4884e969c949
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935808096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2935808096
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1996740988
Short name T407
Test name
Test status
Simulation time 361009466 ps
CPU time 2.63 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 198100 kb
Host smart-4ead2399-d59c-40f0-b0e3-5f3e1e0eb82a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996740988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1996740988
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.959508521
Short name T568
Test name
Test status
Simulation time 219486916 ps
CPU time 1.29 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 198080 kb
Host smart-66107e41-374c-43ae-b7e7-dce45b3f47ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959508521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.959508521
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.372689410
Short name T277
Test name
Test status
Simulation time 181641491 ps
CPU time 0.76 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 195568 kb
Host smart-624161d2-236f-4475-997b-d5f57ff8baf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372689410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.372689410
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.207894172
Short name T632
Test name
Test status
Simulation time 481664831 ps
CPU time 2.99 seconds
Started Feb 21 03:03:38 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 198072 kb
Host smart-b13ac1c2-56c5-44e2-962c-b6c81d5f2ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207894172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.207894172
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1872561463
Short name T11
Test name
Test status
Simulation time 176480306 ps
CPU time 1.27 seconds
Started Feb 21 03:03:34 PM PST 24
Finished Feb 21 03:03:35 PM PST 24
Peak memory 195684 kb
Host smart-c4a16b63-675c-4e55-9a33-9c02f5f3146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872561463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1872561463
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1242179950
Short name T572
Test name
Test status
Simulation time 130004627 ps
CPU time 1.01 seconds
Started Feb 21 03:03:41 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 195656 kb
Host smart-13edf492-6d04-4092-8d83-f671e7fb09cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242179950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1242179950
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.141335717
Short name T194
Test name
Test status
Simulation time 7397485845 ps
CPU time 99.06 seconds
Started Feb 21 03:03:34 PM PST 24
Finished Feb 21 03:05:13 PM PST 24
Peak memory 198268 kb
Host smart-72970f9e-d903-44ce-8e62-32ba0a8d06c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141335717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.141335717
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3928290078
Short name T61
Test name
Test status
Simulation time 96927343492 ps
CPU time 1157.02 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:23:05 PM PST 24
Peak memory 198336 kb
Host smart-c1b21d13-9671-42ee-993d-cc850058a00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3928290078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3928290078
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2898381398
Short name T541
Test name
Test status
Simulation time 48673523 ps
CPU time 0.59 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 194132 kb
Host smart-7f095fce-baf6-4233-a92a-048275f83666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898381398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2898381398
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.681161656
Short name T355
Test name
Test status
Simulation time 138473072 ps
CPU time 0.84 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 195504 kb
Host smart-720d6bc3-dc07-4027-9d72-cd524fe71181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681161656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.681161656
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.113385744
Short name T414
Test name
Test status
Simulation time 518155552 ps
CPU time 7.25 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:58 PM PST 24
Peak memory 197048 kb
Host smart-5af54524-ce4d-4814-b1b2-7a4e27016c1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113385744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.113385744
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3570367241
Short name T445
Test name
Test status
Simulation time 258356976 ps
CPU time 0.73 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 194764 kb
Host smart-19069e16-5cb7-41ad-b165-d70f73aa79f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570367241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3570367241
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1733033996
Short name T417
Test name
Test status
Simulation time 157802749 ps
CPU time 0.94 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:40 PM PST 24
Peak memory 196064 kb
Host smart-32b7d213-018f-4b39-b0e6-8bb48620984d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733033996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1733033996
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.978567437
Short name T524
Test name
Test status
Simulation time 161842588 ps
CPU time 3.39 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:54 PM PST 24
Peak memory 198092 kb
Host smart-6ace9034-0a1d-4cb7-b414-59a710df00ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978567437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.978567437
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2214344256
Short name T310
Test name
Test status
Simulation time 124499067 ps
CPU time 2.45 seconds
Started Feb 21 03:03:50 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 197224 kb
Host smart-61c07183-a344-4c40-863c-630599a37453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214344256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2214344256
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3715327106
Short name T328
Test name
Test status
Simulation time 36535538 ps
CPU time 0.88 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 197148 kb
Host smart-0f391114-e109-4fcc-ac1b-132549181b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715327106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3715327106
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.724450763
Short name T490
Test name
Test status
Simulation time 162426938 ps
CPU time 1.11 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 196100 kb
Host smart-7f62b6b2-f402-41e8-9e7b-84948738a453
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724450763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.724450763
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1544394580
Short name T612
Test name
Test status
Simulation time 1615292574 ps
CPU time 5.93 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:56 PM PST 24
Peak memory 198052 kb
Host smart-33cab540-0d75-499c-a196-9657ca0312bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544394580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1544394580
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2020577998
Short name T442
Test name
Test status
Simulation time 286015447 ps
CPU time 1.23 seconds
Started Feb 21 03:03:31 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 196900 kb
Host smart-392a292e-1e41-4992-ba8d-d14db2d91355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020577998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2020577998
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1704205046
Short name T703
Test name
Test status
Simulation time 171276563 ps
CPU time 1.18 seconds
Started Feb 21 03:03:33 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 195672 kb
Host smart-7040c5c5-68f0-4cd6-918b-aee813f8d330
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704205046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1704205046
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3930151036
Short name T439
Test name
Test status
Simulation time 47052279807 ps
CPU time 154.4 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:06:15 PM PST 24
Peak memory 198236 kb
Host smart-bee13765-3ea7-4eb8-8c88-942d5ef355be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930151036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3930151036
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2293823198
Short name T531
Test name
Test status
Simulation time 16368370 ps
CPU time 0.57 seconds
Started Feb 21 03:03:39 PM PST 24
Finished Feb 21 03:03:40 PM PST 24
Peak memory 194640 kb
Host smart-450ad7e6-8301-4cbf-a395-b1582e1dd871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293823198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2293823198
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2701314116
Short name T28
Test name
Test status
Simulation time 144231621 ps
CPU time 0.96 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 196120 kb
Host smart-dbddcfd8-9ca4-4761-9a4c-c526d019d99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701314116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2701314116
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1203105085
Short name T249
Test name
Test status
Simulation time 664386759 ps
CPU time 17.15 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:04:08 PM PST 24
Peak memory 197332 kb
Host smart-cb474150-37b4-4712-912a-be77aceb7081
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203105085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1203105085
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3768752887
Short name T262
Test name
Test status
Simulation time 178428541 ps
CPU time 0.98 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 196716 kb
Host smart-820584b2-ded3-4cf3-aeef-ae7ee78ee1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768752887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3768752887
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2726587442
Short name T686
Test name
Test status
Simulation time 82321747 ps
CPU time 1.29 seconds
Started Feb 21 03:03:30 PM PST 24
Finished Feb 21 03:03:32 PM PST 24
Peak memory 196204 kb
Host smart-c40d5da3-0a16-4e41-85e8-14fcc17515c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726587442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2726587442
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2759179736
Short name T156
Test name
Test status
Simulation time 58162050 ps
CPU time 1.39 seconds
Started Feb 21 03:03:41 PM PST 24
Finished Feb 21 03:03:43 PM PST 24
Peak memory 198024 kb
Host smart-a42fd521-b01b-41e1-88ae-358d9d9331b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759179736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2759179736
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3889459987
Short name T544
Test name
Test status
Simulation time 135768880 ps
CPU time 2.9 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 198132 kb
Host smart-4b9ea1e1-8c2c-4cb5-82d0-647794780bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889459987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3889459987
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.561046189
Short name T390
Test name
Test status
Simulation time 33980811 ps
CPU time 0.95 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 195880 kb
Host smart-d4219baf-d56e-4156-9066-9b2be03868d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561046189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.561046189
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3713903753
Short name T628
Test name
Test status
Simulation time 61881138 ps
CPU time 1.34 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 198140 kb
Host smart-7c8be1a9-91d9-46c1-ae76-f338c11b36cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713903753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3713903753
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.883518973
Short name T368
Test name
Test status
Simulation time 102444873 ps
CPU time 4.75 seconds
Started Feb 21 03:03:40 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 197232 kb
Host smart-8b53b389-ec1e-40a2-8988-70c7d4ac4461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883518973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.883518973
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1857403512
Short name T290
Test name
Test status
Simulation time 174628157 ps
CPU time 1 seconds
Started Feb 21 03:03:33 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 196452 kb
Host smart-b81ad8ee-4529-4328-a308-ce8d619da901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857403512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1857403512
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2164056764
Short name T130
Test name
Test status
Simulation time 105959542 ps
CPU time 1.09 seconds
Started Feb 21 03:03:45 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 196568 kb
Host smart-b5d77e45-095d-4c55-b10e-b874ab6e13a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164056764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2164056764
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3016696326
Short name T175
Test name
Test status
Simulation time 3949182131 ps
CPU time 104.01 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:05:35 PM PST 24
Peak memory 198244 kb
Host smart-3f6c85db-17cc-4dd6-b2c0-a389658c4a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016696326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3016696326
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3621761115
Short name T65
Test name
Test status
Simulation time 26820915470 ps
CPU time 800.77 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:17:12 PM PST 24
Peak memory 198368 kb
Host smart-d0227a2f-2c4b-4894-a6f3-c2c039d9be7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3621761115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3621761115
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.4291428513
Short name T663
Test name
Test status
Simulation time 45885628 ps
CPU time 0.56 seconds
Started Feb 21 03:02:11 PM PST 24
Finished Feb 21 03:02:12 PM PST 24
Peak memory 193920 kb
Host smart-3d58edcb-965f-4b8c-b372-d4652be27285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291428513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.4291428513
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4065319649
Short name T316
Test name
Test status
Simulation time 37157225 ps
CPU time 0.68 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 194828 kb
Host smart-7ccf77f3-8ac2-4f95-bdd5-b8393309357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065319649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4065319649
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2800964676
Short name T476
Test name
Test status
Simulation time 1784007865 ps
CPU time 22.03 seconds
Started Feb 21 03:02:07 PM PST 24
Finished Feb 21 03:02:30 PM PST 24
Peak memory 198056 kb
Host smart-51e37344-6c37-4a74-af28-70356a5011d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800964676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2800964676
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3644238579
Short name T569
Test name
Test status
Simulation time 32852266 ps
CPU time 0.73 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:11 PM PST 24
Peak memory 194840 kb
Host smart-a85c4bd8-9be3-4e3c-9c5c-9b74612780d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644238579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3644238579
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2714547825
Short name T566
Test name
Test status
Simulation time 248459840 ps
CPU time 1.26 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 197280 kb
Host smart-96be7b2b-b85a-4227-95a3-8f8f6dcfb72a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714547825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2714547825
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2017567527
Short name T385
Test name
Test status
Simulation time 89324216 ps
CPU time 3.32 seconds
Started Feb 21 03:02:11 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 198296 kb
Host smart-e48bb137-6d68-41c2-983a-4d75e6f4aa81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017567527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2017567527
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2631064249
Short name T560
Test name
Test status
Simulation time 816818578 ps
CPU time 1.2 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 195676 kb
Host smart-4d122476-7315-441f-9495-ee6daec5913c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631064249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2631064249
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2443497654
Short name T404
Test name
Test status
Simulation time 50853291 ps
CPU time 1.14 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 196036 kb
Host smart-cf7c41b3-46a0-4c9c-a3ff-3baddc744d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443497654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2443497654
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1290048846
Short name T226
Test name
Test status
Simulation time 51873319 ps
CPU time 1.11 seconds
Started Feb 21 03:02:08 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 196832 kb
Host smart-a1f9241c-8653-41bc-8654-37cad2e1a443
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290048846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1290048846
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.881554643
Short name T365
Test name
Test status
Simulation time 202505683 ps
CPU time 3.44 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 198040 kb
Host smart-2ed80027-c84a-4da2-a83e-1c9ebf616226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881554643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.881554643
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3884252151
Short name T39
Test name
Test status
Simulation time 217342727 ps
CPU time 0.89 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 213812 kb
Host smart-1ffa8952-12b2-44fb-8521-5b9209758216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884252151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3884252151
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2429048613
Short name T555
Test name
Test status
Simulation time 56886844 ps
CPU time 0.77 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 195220 kb
Host smart-61bc82dc-7d65-44a0-866a-1461bf8278b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429048613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2429048613
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2521645148
Short name T592
Test name
Test status
Simulation time 55693251 ps
CPU time 0.8 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 196056 kb
Host smart-ac2c5334-8a69-4956-a506-557494ffc66d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521645148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2521645148
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1060936237
Short name T679
Test name
Test status
Simulation time 34673633276 ps
CPU time 177.52 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:05:13 PM PST 24
Peak memory 198240 kb
Host smart-0362219a-f47b-4160-bc0e-5e8748308053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060936237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1060936237
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2092320404
Short name T400
Test name
Test status
Simulation time 30965984683 ps
CPU time 801.35 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:15:31 PM PST 24
Peak memory 198304 kb
Host smart-e122d4a6-ff42-4407-9474-9cf0fdceceb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2092320404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2092320404
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.917696999
Short name T494
Test name
Test status
Simulation time 42840722 ps
CPU time 0.62 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 194660 kb
Host smart-8d8f0ec7-e048-424d-b571-b0342cbbe995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917696999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.917696999
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.887538614
Short name T549
Test name
Test status
Simulation time 39447328 ps
CPU time 0.74 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 195296 kb
Host smart-ac850f1d-95ea-4609-8056-6afc0f63337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887538614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.887538614
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3539846827
Short name T678
Test name
Test status
Simulation time 762310428 ps
CPU time 24.83 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:04:09 PM PST 24
Peak memory 196380 kb
Host smart-c3b600d0-2f1c-41dd-bef6-17d1b3a67bd5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539846827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3539846827
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3928259274
Short name T306
Test name
Test status
Simulation time 219305611 ps
CPU time 0.95 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 197056 kb
Host smart-63914381-4994-447d-811e-61cf166bd11a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928259274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3928259274
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3103943599
Short name T532
Test name
Test status
Simulation time 70352538 ps
CPU time 1.05 seconds
Started Feb 21 03:03:31 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 196148 kb
Host smart-7b5947b1-c914-4462-95b2-234fe5bb3a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103943599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3103943599
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4253520644
Short name T633
Test name
Test status
Simulation time 79003781 ps
CPU time 3.14 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 196432 kb
Host smart-59ac10f0-ad2e-4ef0-b69b-c60fdd844979
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253520644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4253520644
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.76888334
Short name T538
Test name
Test status
Simulation time 181475476 ps
CPU time 2.37 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 198132 kb
Host smart-72c13344-aeac-4c90-9410-fc19de02d6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76888334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.76888334
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2674887618
Short name T58
Test name
Test status
Simulation time 93804989 ps
CPU time 0.76 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 195468 kb
Host smart-15c25d2f-5250-4c8a-af93-510a74c08055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674887618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2674887618
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3324962712
Short name T717
Test name
Test status
Simulation time 31403222 ps
CPU time 1.17 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196136 kb
Host smart-d534e10c-4c91-4645-ad13-0b153baf1054
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324962712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3324962712
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2531267004
Short name T291
Test name
Test status
Simulation time 438262490 ps
CPU time 2.11 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 198072 kb
Host smart-a8b708b3-d193-49ef-a7a8-fa289a9af6f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531267004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2531267004
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2921274061
Short name T354
Test name
Test status
Simulation time 164491377 ps
CPU time 0.85 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:47 PM PST 24
Peak memory 195936 kb
Host smart-d8043832-9a5b-44e8-9506-f1be97b4537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921274061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2921274061
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1356086650
Short name T685
Test name
Test status
Simulation time 65810787 ps
CPU time 1.15 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:03:49 PM PST 24
Peak memory 195568 kb
Host smart-d73b5615-b67b-46d6-90a8-1c6123fcb757
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356086650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1356086650
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3169677689
Short name T273
Test name
Test status
Simulation time 14893616175 ps
CPU time 150.24 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:06:22 PM PST 24
Peak memory 198292 kb
Host smart-4a7156cc-1175-4ca4-b461-77b7c2e2a0ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169677689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3169677689
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2305826108
Short name T27
Test name
Test status
Simulation time 53114831 ps
CPU time 0.58 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 194104 kb
Host smart-f6acb76c-91d4-4b8c-9807-a93b4e30e8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305826108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2305826108
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3906028879
Short name T235
Test name
Test status
Simulation time 91268958 ps
CPU time 0.81 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 196072 kb
Host smart-729a85a4-0d78-4db6-9b35-ef24ce6d91df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906028879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3906028879
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2747250437
Short name T492
Test name
Test status
Simulation time 324832297 ps
CPU time 6.26 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 196396 kb
Host smart-ce867f0c-9c23-4751-b1a0-3bc941a47b5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747250437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2747250437
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2737324028
Short name T525
Test name
Test status
Simulation time 99233937 ps
CPU time 0.75 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196752 kb
Host smart-ca0d4438-f8ea-40c8-911b-38f51aed2908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737324028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2737324028
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2328933212
Short name T502
Test name
Test status
Simulation time 63467666 ps
CPU time 1.18 seconds
Started Feb 21 03:03:52 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 196888 kb
Host smart-a26cd1fa-761c-44c0-8560-f03b0d4e9f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328933212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2328933212
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3123397352
Short name T701
Test name
Test status
Simulation time 81583121 ps
CPU time 1.67 seconds
Started Feb 21 03:03:36 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 196612 kb
Host smart-a9a82225-8c97-4ac8-92e7-b2d796cd5d43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123397352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3123397352
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3281350262
Short name T266
Test name
Test status
Simulation time 334559883 ps
CPU time 2.72 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:53 PM PST 24
Peak memory 198196 kb
Host smart-f9bed471-5204-4e31-9de8-de92bccd0c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281350262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3281350262
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.572953985
Short name T553
Test name
Test status
Simulation time 22307433 ps
CPU time 0.88 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 197480 kb
Host smart-fc0eeddf-d849-4110-91fa-567a9f12874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572953985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.572953985
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.164662170
Short name T189
Test name
Test status
Simulation time 39231518 ps
CPU time 0.6 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 194340 kb
Host smart-38974488-7dc9-41d9-8ad7-5f7b61335735
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164662170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.164662170
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1750295078
Short name T653
Test name
Test status
Simulation time 1278147068 ps
CPU time 4.07 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 198080 kb
Host smart-64506b50-0bae-45e1-b957-43354aa56194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750295078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1750295078
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1747833956
Short name T677
Test name
Test status
Simulation time 227787681 ps
CPU time 1.18 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 196984 kb
Host smart-c22c9b4d-7f88-4dff-9e0b-4884fa8fc88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747833956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1747833956
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3797722507
Short name T285
Test name
Test status
Simulation time 280699201 ps
CPU time 1.4 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196860 kb
Host smart-09dc5e01-6583-4379-8848-7a5b9d2b9926
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797722507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3797722507
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2853807880
Short name T326
Test name
Test status
Simulation time 8857478339 ps
CPU time 95.49 seconds
Started Feb 21 03:03:44 PM PST 24
Finished Feb 21 03:05:22 PM PST 24
Peak memory 198260 kb
Host smart-de12e13d-64dd-43e8-b126-9464cb09b5d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853807880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2853807880
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3629458042
Short name T21
Test name
Test status
Simulation time 17695162 ps
CPU time 0.57 seconds
Started Feb 21 03:03:41 PM PST 24
Finished Feb 21 03:03:42 PM PST 24
Peak memory 193996 kb
Host smart-8416a72f-6304-4dc1-b9a2-ebd276ca5d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629458042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3629458042
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1384862527
Short name T122
Test name
Test status
Simulation time 141572741 ps
CPU time 0.83 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 197076 kb
Host smart-a87e4e88-52a7-4f45-916e-51a63e1f9e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384862527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1384862527
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4051536731
Short name T603
Test name
Test status
Simulation time 811265559 ps
CPU time 12.21 seconds
Started Feb 21 03:03:46 PM PST 24
Finished Feb 21 03:04:01 PM PST 24
Peak memory 198052 kb
Host smart-5c9a2987-ec61-4ac3-8037-81bb3fd83fe5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051536731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4051536731
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2666738720
Short name T5
Test name
Test status
Simulation time 676382752 ps
CPU time 0.9 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 195988 kb
Host smart-84b3e2d6-e06d-4851-8e6b-64df86b253a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666738720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2666738720
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.629281029
Short name T116
Test name
Test status
Simulation time 42164664 ps
CPU time 1.2 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 196216 kb
Host smart-d881c0cb-9723-4ffd-b6a5-6885779d91bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629281029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.629281029
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.681064856
Short name T435
Test name
Test status
Simulation time 127407825 ps
CPU time 1.32 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196768 kb
Host smart-d6cde2f8-b82c-4518-b509-0a08ccabd7f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681064856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.681064856
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.804436773
Short name T710
Test name
Test status
Simulation time 222852712 ps
CPU time 3.18 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:54 PM PST 24
Peak memory 195908 kb
Host smart-ecb99afd-bf83-4325-be42-1c6a1db9c582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804436773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
804436773
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3494351722
Short name T497
Test name
Test status
Simulation time 29756317 ps
CPU time 0.71 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196276 kb
Host smart-2de0ca97-8e49-4f95-ac69-10a1d4e99001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494351722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3494351722
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.402045862
Short name T409
Test name
Test status
Simulation time 476743812 ps
CPU time 0.95 seconds
Started Feb 21 03:03:43 PM PST 24
Finished Feb 21 03:03:45 PM PST 24
Peak memory 196100 kb
Host smart-440e14f4-6e08-472d-9494-8821f82d0a3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402045862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.402045862
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.418566261
Short name T230
Test name
Test status
Simulation time 82591250 ps
CPU time 3.81 seconds
Started Feb 21 03:03:41 PM PST 24
Finished Feb 21 03:03:46 PM PST 24
Peak memory 198076 kb
Host smart-818a8ce4-a072-4a50-92e9-8f988906b97b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418566261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.418566261
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2869023139
Short name T20
Test name
Test status
Simulation time 51897200 ps
CPU time 0.93 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:43 PM PST 24
Peak memory 197148 kb
Host smart-11ced64b-7adf-4b4e-8a74-0f4597c5098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869023139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2869023139
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1152833966
Short name T690
Test name
Test status
Simulation time 288634035 ps
CPU time 0.8 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 196076 kb
Host smart-e097cdb3-9d71-4c79-88d5-893add9c74b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152833966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1152833966
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.74076105
Short name T533
Test name
Test status
Simulation time 54761989779 ps
CPU time 174.77 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:06:46 PM PST 24
Peak memory 198128 kb
Host smart-9f9e4dba-9c55-4ccb-ad48-e3ad51157d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74076105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gp
io_stress_all.74076105
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2470240686
Short name T674
Test name
Test status
Simulation time 28598779420 ps
CPU time 803.58 seconds
Started Feb 21 03:03:49 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 198328 kb
Host smart-47940d5a-b518-4a92-8493-0b7485aeb175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2470240686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2470240686
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2939548875
Short name T621
Test name
Test status
Simulation time 25919278 ps
CPU time 0.59 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 194152 kb
Host smart-0323a67e-2197-405a-b323-85812185dbf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939548875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2939548875
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1167555303
Short name T200
Test name
Test status
Simulation time 29655923 ps
CPU time 0.84 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 197172 kb
Host smart-d0770720-baae-412b-ae73-7c6508df4857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167555303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1167555303
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2664553627
Short name T651
Test name
Test status
Simulation time 1284863154 ps
CPU time 18.21 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:04:13 PM PST 24
Peak memory 196924 kb
Host smart-8d512081-43d9-4096-bfba-efe75bc7ea37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664553627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2664553627
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1145129344
Short name T388
Test name
Test status
Simulation time 367425340 ps
CPU time 1.09 seconds
Started Feb 21 03:03:58 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 196688 kb
Host smart-ce19e410-4e9a-4b06-88a3-37b6b550fd85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145129344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1145129344
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2749456402
Short name T137
Test name
Test status
Simulation time 58074989 ps
CPU time 1.05 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:03:56 PM PST 24
Peak memory 196700 kb
Host smart-edb4c516-0411-4009-a294-8c7d4f626d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749456402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2749456402
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2878168812
Short name T377
Test name
Test status
Simulation time 607845202 ps
CPU time 3.31 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:03:58 PM PST 24
Peak memory 196540 kb
Host smart-6cd4e3b7-a599-423c-94ff-e0b4fcade1e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878168812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2878168812
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4210745944
Short name T17
Test name
Test status
Simulation time 26969059 ps
CPU time 1 seconds
Started Feb 21 03:04:01 PM PST 24
Finished Feb 21 03:04:02 PM PST 24
Peak memory 195636 kb
Host smart-723d4f9a-b212-4f39-88ea-d250d03fe627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210745944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4210745944
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.609677811
Short name T450
Test name
Test status
Simulation time 135148501 ps
CPU time 1.17 seconds
Started Feb 21 03:03:48 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 197156 kb
Host smart-ae8fa654-887b-4e30-9b7b-a1e6dfab2c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609677811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.609677811
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2813410853
Short name T659
Test name
Test status
Simulation time 46805274 ps
CPU time 1.02 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:44 PM PST 24
Peak memory 195948 kb
Host smart-fa6c50ec-bd53-40a4-a4e6-5c188a71dd4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813410853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2813410853
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1772177117
Short name T342
Test name
Test status
Simulation time 540464079 ps
CPU time 2.02 seconds
Started Feb 21 03:03:57 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 198080 kb
Host smart-d32cd8cd-644f-4b50-826a-4bd712ca1261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772177117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1772177117
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2181824939
Short name T452
Test name
Test status
Simulation time 37696051 ps
CPU time 0.95 seconds
Started Feb 21 03:03:42 PM PST 24
Finished Feb 21 03:03:43 PM PST 24
Peak memory 196484 kb
Host smart-470c47d4-795b-49e2-b108-b5a6d51cf23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181824939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2181824939
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2435101078
Short name T425
Test name
Test status
Simulation time 54363725 ps
CPU time 1.32 seconds
Started Feb 21 03:03:47 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 195620 kb
Host smart-3aa3a75a-2cab-4aaa-9829-ddaad73677e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435101078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2435101078
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4049354693
Short name T143
Test name
Test status
Simulation time 22310341512 ps
CPU time 151.64 seconds
Started Feb 21 03:04:01 PM PST 24
Finished Feb 21 03:06:33 PM PST 24
Peak memory 198152 kb
Host smart-ef3a4e11-4298-4382-b53f-0327636cde28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049354693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4049354693
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.639210838
Short name T635
Test name
Test status
Simulation time 23405886 ps
CPU time 0.57 seconds
Started Feb 21 03:04:00 PM PST 24
Finished Feb 21 03:04:01 PM PST 24
Peak memory 194104 kb
Host smart-6aaed15d-ec55-48dd-b8c8-93313da29986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639210838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.639210838
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1003964814
Short name T125
Test name
Test status
Simulation time 99387926 ps
CPU time 0.79 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 195512 kb
Host smart-81e5b85b-80b6-470a-a508-536e7e573ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003964814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1003964814
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2840110067
Short name T467
Test name
Test status
Simulation time 592364683 ps
CPU time 10.12 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:04:06 PM PST 24
Peak memory 196584 kb
Host smart-84ae9ec9-548d-4992-9fe6-b91a64c370d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840110067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2840110067
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2021221145
Short name T498
Test name
Test status
Simulation time 497691802 ps
CPU time 1.11 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:58 PM PST 24
Peak memory 197016 kb
Host smart-9a5ac5ec-a3d1-4332-847d-a0f12285750b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021221145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2021221145
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1890271443
Short name T43
Test name
Test status
Simulation time 48143455 ps
CPU time 1.32 seconds
Started Feb 21 03:03:58 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 197260 kb
Host smart-ffc8cbd8-c3a8-45c3-8ad5-6efdcb7a4326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890271443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1890271443
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.551135179
Short name T24
Test name
Test status
Simulation time 45676085 ps
CPU time 1.68 seconds
Started Feb 21 03:03:59 PM PST 24
Finished Feb 21 03:04:01 PM PST 24
Peak memory 198164 kb
Host smart-891f8fcc-a555-42e7-887c-1f46772b27d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551135179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.551135179
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1000414346
Short name T118
Test name
Test status
Simulation time 125236665 ps
CPU time 2.91 seconds
Started Feb 21 03:04:01 PM PST 24
Finished Feb 21 03:04:05 PM PST 24
Peak memory 196636 kb
Host smart-d17eb906-0009-4fa9-acbb-330f8f8a4689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000414346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1000414346
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1163788867
Short name T178
Test name
Test status
Simulation time 49237483 ps
CPU time 1.21 seconds
Started Feb 21 03:04:06 PM PST 24
Finished Feb 21 03:04:07 PM PST 24
Peak memory 196180 kb
Host smart-830748ae-f3fc-4a45-8998-7ac6c9d53dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163788867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1163788867
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1131861936
Short name T165
Test name
Test status
Simulation time 123542100 ps
CPU time 1.32 seconds
Started Feb 21 03:04:04 PM PST 24
Finished Feb 21 03:04:06 PM PST 24
Peak memory 197076 kb
Host smart-6eecc032-c7d3-45d2-969d-ab89d7adb31f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131861936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1131861936
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.574562150
Short name T7
Test name
Test status
Simulation time 900744867 ps
CPU time 2.98 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:03:58 PM PST 24
Peak memory 198092 kb
Host smart-d0d7ea6d-f1ca-499f-955b-515caef37a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574562150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.574562150
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1949591415
Short name T408
Test name
Test status
Simulation time 317324266 ps
CPU time 1.29 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 196556 kb
Host smart-65604e25-ee7a-40bc-b35d-9688aec82c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949591415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1949591415
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2509353506
Short name T594
Test name
Test status
Simulation time 32920282 ps
CPU time 0.85 seconds
Started Feb 21 03:04:05 PM PST 24
Finished Feb 21 03:04:06 PM PST 24
Peak memory 195360 kb
Host smart-52fa06f2-0f6f-433a-a403-ea4da95228b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509353506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2509353506
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3366692887
Short name T545
Test name
Test status
Simulation time 24947935035 ps
CPU time 173.02 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:06:47 PM PST 24
Peak memory 198252 kb
Host smart-69606f1d-f184-4fcd-a40e-9934f04a1f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366692887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3366692887
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2610969223
Short name T664
Test name
Test status
Simulation time 34059589 ps
CPU time 0.57 seconds
Started Feb 21 03:04:02 PM PST 24
Finished Feb 21 03:04:03 PM PST 24
Peak memory 193984 kb
Host smart-ceedd4c0-f215-4d7c-8217-b13d8f02edd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610969223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2610969223
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3725620430
Short name T253
Test name
Test status
Simulation time 31599173 ps
CPU time 0.86 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 196116 kb
Host smart-2dbb06a8-a834-4e9f-a7fd-afdd41fbad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725620430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3725620430
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3714130425
Short name T346
Test name
Test status
Simulation time 815141631 ps
CPU time 11.59 seconds
Started Feb 21 03:04:06 PM PST 24
Finished Feb 21 03:04:18 PM PST 24
Peak memory 198116 kb
Host smart-a3b598fa-4319-4f77-8a81-5ce4dbfba122
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714130425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3714130425
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2597668469
Short name T208
Test name
Test status
Simulation time 332442036 ps
CPU time 0.75 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 196044 kb
Host smart-18e01c92-d0ef-49af-b183-e5ce4cf1df61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597668469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2597668469
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1684034599
Short name T426
Test name
Test status
Simulation time 499031696 ps
CPU time 1.34 seconds
Started Feb 21 03:04:01 PM PST 24
Finished Feb 21 03:04:03 PM PST 24
Peak memory 197212 kb
Host smart-80a369d6-4a9b-456f-b78b-72d78848a81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684034599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1684034599
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.417388390
Short name T129
Test name
Test status
Simulation time 168231462 ps
CPU time 1.62 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 198244 kb
Host smart-85b8412c-6e06-4525-928f-717f5c65a432
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417388390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.417388390
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1224417431
Short name T522
Test name
Test status
Simulation time 94351019 ps
CPU time 2.36 seconds
Started Feb 21 03:04:03 PM PST 24
Finished Feb 21 03:04:06 PM PST 24
Peak memory 195888 kb
Host smart-63765d44-3ed3-40cf-8da8-b0e36246b088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224417431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1224417431
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2784059427
Short name T155
Test name
Test status
Simulation time 56269873 ps
CPU time 0.68 seconds
Started Feb 21 03:03:58 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 194312 kb
Host smart-6ab808b4-8240-42dd-9bbb-f040808313a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784059427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2784059427
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.776809065
Short name T238
Test name
Test status
Simulation time 27977764 ps
CPU time 0.78 seconds
Started Feb 21 03:04:03 PM PST 24
Finished Feb 21 03:04:04 PM PST 24
Peak memory 195420 kb
Host smart-33cebbb4-b914-4b97-a8eb-b5be7dfdb386
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776809065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.776809065
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2667980031
Short name T655
Test name
Test status
Simulation time 436887000 ps
CPU time 5.46 seconds
Started Feb 21 03:03:59 PM PST 24
Finished Feb 21 03:04:05 PM PST 24
Peak memory 198092 kb
Host smart-abd8e412-98ab-4420-9043-1f976d0cffae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667980031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2667980031
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2031978040
Short name T606
Test name
Test status
Simulation time 178625154 ps
CPU time 1.08 seconds
Started Feb 21 03:03:57 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 196048 kb
Host smart-2515fd21-2285-4dec-acdf-f8615b55ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031978040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2031978040
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3399571302
Short name T486
Test name
Test status
Simulation time 132732848 ps
CPU time 0.85 seconds
Started Feb 21 03:04:05 PM PST 24
Finished Feb 21 03:04:06 PM PST 24
Peak memory 195364 kb
Host smart-93eb0245-ae91-4079-9fb2-d01c97b803a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399571302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3399571302
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.17814234
Short name T295
Test name
Test status
Simulation time 4753432804 ps
CPU time 38.04 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:04:34 PM PST 24
Peak memory 198276 kb
Host smart-ea62ee1d-06cd-4a0e-a277-fbc8ca16c384
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gp
io_stress_all.17814234
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.991095374
Short name T205
Test name
Test status
Simulation time 13669775 ps
CPU time 0.6 seconds
Started Feb 21 03:04:03 PM PST 24
Finished Feb 21 03:04:04 PM PST 24
Peak memory 194648 kb
Host smart-dbdd3184-8714-4368-ae34-cb4081ed7d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991095374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.991095374
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2105808575
Short name T496
Test name
Test status
Simulation time 29233876 ps
CPU time 0.78 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:03:56 PM PST 24
Peak memory 196060 kb
Host smart-0ab7e216-614f-4f04-9414-f5ac6d1557be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105808575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2105808575
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2089003069
Short name T515
Test name
Test status
Simulation time 1465143612 ps
CPU time 22.39 seconds
Started Feb 21 03:04:05 PM PST 24
Finished Feb 21 03:04:27 PM PST 24
Peak memory 195672 kb
Host smart-1a64a116-846a-4b43-bad7-0b6688d3f7dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089003069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2089003069
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.587559106
Short name T570
Test name
Test status
Simulation time 65970397 ps
CPU time 0.96 seconds
Started Feb 21 03:04:03 PM PST 24
Finished Feb 21 03:04:05 PM PST 24
Peak memory 197188 kb
Host smart-3a1026fc-1398-44a3-8d91-929e7a437337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587559106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.587559106
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1952486320
Short name T471
Test name
Test status
Simulation time 25849160 ps
CPU time 0.72 seconds
Started Feb 21 03:03:58 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 195368 kb
Host smart-515cba3f-10dd-4671-bfa2-46b3b293d31f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952486320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1952486320
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.698986912
Short name T216
Test name
Test status
Simulation time 84594535 ps
CPU time 1.8 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:03:56 PM PST 24
Peak memory 197328 kb
Host smart-ecb5ae0b-df66-4c77-9c5b-ececf42cead6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698986912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.698986912
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2703752561
Short name T23
Test name
Test status
Simulation time 503043083 ps
CPU time 3.71 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:04:01 PM PST 24
Peak memory 197312 kb
Host smart-3f5e9f59-1e86-4d53-a900-84a7b172c8d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703752561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2703752561
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3889572264
Short name T187
Test name
Test status
Simulation time 95204386 ps
CPU time 0.98 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 195936 kb
Host smart-270fca77-b941-4791-b21f-83362839623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889572264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3889572264
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1947887270
Short name T584
Test name
Test status
Simulation time 26222401 ps
CPU time 0.75 seconds
Started Feb 21 03:03:54 PM PST 24
Finished Feb 21 03:03:55 PM PST 24
Peak memory 195388 kb
Host smart-f8df947c-97f7-471b-9055-d63dd1be7831
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947887270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1947887270
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2119623412
Short name T272
Test name
Test status
Simulation time 144260206 ps
CPU time 1.87 seconds
Started Feb 21 03:03:57 PM PST 24
Finished Feb 21 03:04:00 PM PST 24
Peak memory 198164 kb
Host smart-57d40fd0-e481-4129-8a6e-2b968317b1e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119623412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2119623412
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2480844875
Short name T374
Test name
Test status
Simulation time 118901873 ps
CPU time 0.92 seconds
Started Feb 21 03:03:58 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 196540 kb
Host smart-490f8e13-6dd4-4b41-a15a-cfc152e3c12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480844875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2480844875
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4218513953
Short name T715
Test name
Test status
Simulation time 42624594 ps
CPU time 0.94 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 197180 kb
Host smart-4012e58e-ba15-448d-b916-0f3abd908b64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218513953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4218513953
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.158764971
Short name T527
Test name
Test status
Simulation time 28030112442 ps
CPU time 206.75 seconds
Started Feb 21 03:04:04 PM PST 24
Finished Feb 21 03:07:31 PM PST 24
Peak memory 198288 kb
Host smart-2ed46f61-7424-4069-bd80-9ed608cbe51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158764971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.158764971
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3318894884
Short name T367
Test name
Test status
Simulation time 952700511848 ps
CPU time 2314.72 seconds
Started Feb 21 03:03:56 PM PST 24
Finished Feb 21 03:42:32 PM PST 24
Peak memory 206572 kb
Host smart-b5f62e79-e3ff-4f2e-a049-46ada3edb1b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3318894884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3318894884
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3350548956
Short name T406
Test name
Test status
Simulation time 15518050 ps
CPU time 0.58 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:04:31 PM PST 24
Peak memory 193908 kb
Host smart-aa809d31-fdd5-428d-b5fa-00793ece8813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350548956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3350548956
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.123316906
Short name T643
Test name
Test status
Simulation time 42808584 ps
CPU time 0.75 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:27 PM PST 24
Peak memory 195228 kb
Host smart-f33f64f9-d224-4d59-82c8-720ed3907593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123316906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.123316906
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3466415009
Short name T704
Test name
Test status
Simulation time 3310483790 ps
CPU time 21 seconds
Started Feb 21 03:04:33 PM PST 24
Finished Feb 21 03:04:54 PM PST 24
Peak memory 196948 kb
Host smart-10a97fe4-c932-4171-bba1-2677333d3ed5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466415009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3466415009
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1018132278
Short name T98
Test name
Test status
Simulation time 56126056 ps
CPU time 0.92 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:28 PM PST 24
Peak memory 197936 kb
Host smart-d2627a38-8a28-496f-b467-b6a1a6467156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018132278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1018132278
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.769612787
Short name T654
Test name
Test status
Simulation time 292878016 ps
CPU time 1.12 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:27 PM PST 24
Peak memory 196180 kb
Host smart-490adfac-cf10-4221-adb1-3032d9612aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769612787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.769612787
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2815950039
Short name T112
Test name
Test status
Simulation time 59697824 ps
CPU time 2.22 seconds
Started Feb 21 03:04:40 PM PST 24
Finished Feb 21 03:04:42 PM PST 24
Peak memory 196512 kb
Host smart-d7601cba-4e49-42db-a840-8f14c34afb31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815950039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2815950039
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1979576351
Short name T440
Test name
Test status
Simulation time 122874964 ps
CPU time 2.69 seconds
Started Feb 21 03:04:33 PM PST 24
Finished Feb 21 03:04:36 PM PST 24
Peak memory 198200 kb
Host smart-a4041dac-16f0-42e1-8f50-a23f6a824749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979576351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1979576351
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2249863049
Short name T106
Test name
Test status
Simulation time 234448043 ps
CPU time 0.88 seconds
Started Feb 21 03:03:57 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 196640 kb
Host smart-40500e2d-6cf0-4c05-b4af-036d20eb99a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249863049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2249863049
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3935527828
Short name T662
Test name
Test status
Simulation time 28664581 ps
CPU time 1.03 seconds
Started Feb 21 03:03:57 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 196892 kb
Host smart-1c8f74cf-89ba-42ed-80df-3367dbffa3df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935527828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3935527828
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2795364672
Short name T305
Test name
Test status
Simulation time 280947444 ps
CPU time 3.59 seconds
Started Feb 21 03:04:28 PM PST 24
Finished Feb 21 03:04:32 PM PST 24
Peak memory 198048 kb
Host smart-5a544a3e-2ca3-49e9-af9b-8112a9dab98f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795364672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2795364672
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1425050192
Short name T427
Test name
Test status
Simulation time 373903292 ps
CPU time 1.4 seconds
Started Feb 21 03:03:55 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 196800 kb
Host smart-59072b59-3447-4d11-a4c6-010485a88160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425050192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1425050192
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.463885008
Short name T458
Test name
Test status
Simulation time 591034256 ps
CPU time 1.2 seconds
Started Feb 21 03:04:00 PM PST 24
Finished Feb 21 03:04:01 PM PST 24
Peak memory 196360 kb
Host smart-3af03bab-5c9f-4bb3-a43d-0e1e6a9ad3fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463885008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.463885008
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1207062552
Short name T318
Test name
Test status
Simulation time 8434504887 ps
CPU time 113.99 seconds
Started Feb 21 03:04:29 PM PST 24
Finished Feb 21 03:06:24 PM PST 24
Peak memory 198312 kb
Host smart-4f526051-f188-449c-968c-809f6548527b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207062552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1207062552
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3405732658
Short name T517
Test name
Test status
Simulation time 61141541 ps
CPU time 0.58 seconds
Started Feb 21 03:04:15 PM PST 24
Finished Feb 21 03:04:17 PM PST 24
Peak memory 194620 kb
Host smart-d0a416ea-ba7b-4ed0-a7db-b1587bd9811c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405732658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3405732658
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1531883772
Short name T521
Test name
Test status
Simulation time 17811012 ps
CPU time 0.68 seconds
Started Feb 21 03:04:28 PM PST 24
Finished Feb 21 03:04:29 PM PST 24
Peak memory 194128 kb
Host smart-1c2dee1e-08e7-430d-b0ab-a2068ffb6c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531883772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1531883772
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.394039888
Short name T613
Test name
Test status
Simulation time 673571357 ps
CPU time 23.26 seconds
Started Feb 21 03:04:28 PM PST 24
Finished Feb 21 03:04:52 PM PST 24
Peak memory 198084 kb
Host smart-6cab3b85-e388-46d7-a908-11bdd182c781
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394039888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.394039888
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.124158258
Short name T311
Test name
Test status
Simulation time 326287597 ps
CPU time 0.83 seconds
Started Feb 21 03:04:34 PM PST 24
Finished Feb 21 03:04:35 PM PST 24
Peak memory 196060 kb
Host smart-cdb9c5c6-6ca4-44cf-959a-7463f0845cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124158258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.124158258
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3696915799
Short name T144
Test name
Test status
Simulation time 164325554 ps
CPU time 1.18 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:27 PM PST 24
Peak memory 195944 kb
Host smart-d01b02c4-85d0-4a72-bf70-3563319a1f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696915799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3696915799
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2498187136
Short name T302
Test name
Test status
Simulation time 300817321 ps
CPU time 3.37 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:04:34 PM PST 24
Peak memory 197252 kb
Host smart-ea23fc2a-f592-4363-8666-43595a5c5091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498187136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2498187136
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3720780158
Short name T300
Test name
Test status
Simulation time 222215241 ps
CPU time 1.14 seconds
Started Feb 21 03:04:16 PM PST 24
Finished Feb 21 03:04:18 PM PST 24
Peak memory 196028 kb
Host smart-bf85fa21-4f8f-438d-a97b-5260d029f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720780158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3720780158
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2054619524
Short name T578
Test name
Test status
Simulation time 146196569 ps
CPU time 0.88 seconds
Started Feb 21 03:04:28 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 196596 kb
Host smart-f0b7602f-52db-46d5-859c-259130cd5da8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054619524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2054619524
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1221233916
Short name T361
Test name
Test status
Simulation time 373807344 ps
CPU time 4.84 seconds
Started Feb 21 03:04:25 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 198092 kb
Host smart-ff62dd6e-e2dd-464e-acde-d386a59189b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221233916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1221233916
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1601519702
Short name T595
Test name
Test status
Simulation time 39832612 ps
CPU time 1 seconds
Started Feb 21 03:04:32 PM PST 24
Finished Feb 21 03:04:33 PM PST 24
Peak memory 195688 kb
Host smart-681a69fd-31b6-4911-b264-33dd8f72ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601519702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1601519702
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2723832281
Short name T363
Test name
Test status
Simulation time 36307772 ps
CPU time 1.04 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:04:32 PM PST 24
Peak memory 195864 kb
Host smart-a90848f9-6ca7-4c5f-b1d7-c3af7587a961
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723832281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2723832281
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1798284241
Short name T599
Test name
Test status
Simulation time 18623829136 ps
CPU time 215.17 seconds
Started Feb 21 03:04:32 PM PST 24
Finished Feb 21 03:08:07 PM PST 24
Peak memory 198248 kb
Host smart-b55187fe-27a9-40dd-aacc-371b88761da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798284241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1798284241
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.197100048
Short name T590
Test name
Test status
Simulation time 265589193912 ps
CPU time 2512.27 seconds
Started Feb 21 03:04:29 PM PST 24
Finished Feb 21 03:46:22 PM PST 24
Peak memory 198356 kb
Host smart-2f3f65df-d2ab-48cd-aaec-dbb5777a30e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=197100048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.197100048
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.858364071
Short name T195
Test name
Test status
Simulation time 20464580 ps
CPU time 0.57 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:04:31 PM PST 24
Peak memory 193964 kb
Host smart-c92ed47f-5e6b-4328-bffc-ef8d2fcc68e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858364071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.858364071
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1345844293
Short name T185
Test name
Test status
Simulation time 52491072 ps
CPU time 0.84 seconds
Started Feb 21 03:04:29 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 195296 kb
Host smart-c0dc2a15-5b59-4405-9980-80864f38696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345844293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1345844293
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2510784996
Short name T656
Test name
Test status
Simulation time 1573044970 ps
CPU time 26.97 seconds
Started Feb 21 03:04:26 PM PST 24
Finished Feb 21 03:04:53 PM PST 24
Peak memory 197072 kb
Host smart-62566a7d-66d9-4f5b-87e2-09ce628be87d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510784996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2510784996
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3029156746
Short name T393
Test name
Test status
Simulation time 216289628 ps
CPU time 0.82 seconds
Started Feb 21 03:04:32 PM PST 24
Finished Feb 21 03:04:33 PM PST 24
Peak memory 196004 kb
Host smart-afc51a97-d90e-4763-b040-037d76098e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029156746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3029156746
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2296541929
Short name T661
Test name
Test status
Simulation time 325500540 ps
CPU time 1.23 seconds
Started Feb 21 03:04:24 PM PST 24
Finished Feb 21 03:04:26 PM PST 24
Peak memory 196220 kb
Host smart-01c31e30-87dd-47f8-b45b-ecffee512dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296541929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2296541929
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2695184260
Short name T620
Test name
Test status
Simulation time 91778626 ps
CPU time 3.52 seconds
Started Feb 21 03:04:37 PM PST 24
Finished Feb 21 03:04:41 PM PST 24
Peak memory 198200 kb
Host smart-53a5bc55-4060-44cb-a9ef-12e35eebd718
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695184260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2695184260
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4158008738
Short name T405
Test name
Test status
Simulation time 44839930 ps
CPU time 1.37 seconds
Started Feb 21 03:04:32 PM PST 24
Finished Feb 21 03:04:34 PM PST 24
Peak memory 196544 kb
Host smart-6365ce93-ec61-4c41-b734-bd01f4b60d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158008738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4158008738
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2140147552
Short name T131
Test name
Test status
Simulation time 56586714 ps
CPU time 1.12 seconds
Started Feb 21 03:04:19 PM PST 24
Finished Feb 21 03:04:20 PM PST 24
Peak memory 196620 kb
Host smart-cc9c62e6-5f8e-4a1b-a3d7-424972ed34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140147552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2140147552
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1461470258
Short name T573
Test name
Test status
Simulation time 121921295 ps
CPU time 1.27 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:04:32 PM PST 24
Peak memory 197300 kb
Host smart-c38bee80-fbc7-44e2-b1d3-a0a9dd748098
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461470258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1461470258
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1421745797
Short name T274
Test name
Test status
Simulation time 297880542 ps
CPU time 4.67 seconds
Started Feb 21 03:04:33 PM PST 24
Finished Feb 21 03:04:38 PM PST 24
Peak memory 198112 kb
Host smart-685d8809-fbab-4e0d-82ed-1f0440ca8618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421745797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1421745797
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.433769262
Short name T99
Test name
Test status
Simulation time 120098993 ps
CPU time 0.93 seconds
Started Feb 21 03:04:20 PM PST 24
Finished Feb 21 03:04:23 PM PST 24
Peak memory 196468 kb
Host smart-59e0d1d1-c58b-4bd0-bf9d-db600019fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433769262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.433769262
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1525487407
Short name T53
Test name
Test status
Simulation time 60366030 ps
CPU time 1.02 seconds
Started Feb 21 03:04:39 PM PST 24
Finished Feb 21 03:04:41 PM PST 24
Peak memory 195568 kb
Host smart-741e2344-3bcf-4a19-90e2-0ed5d6bc3454
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525487407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1525487407
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1913001616
Short name T601
Test name
Test status
Simulation time 31933887148 ps
CPU time 206.93 seconds
Started Feb 21 03:04:30 PM PST 24
Finished Feb 21 03:07:57 PM PST 24
Peak memory 198248 kb
Host smart-3e59018e-05fd-4c2a-af7c-a7837da97c11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913001616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1913001616
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1242421509
Short name T33
Test name
Test status
Simulation time 480112765024 ps
CPU time 1731.82 seconds
Started Feb 21 03:04:20 PM PST 24
Finished Feb 21 03:33:12 PM PST 24
Peak memory 198420 kb
Host smart-2b7e9f2d-91e9-42c9-a1e0-b384922bf1c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1242421509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1242421509
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2511894895
Short name T582
Test name
Test status
Simulation time 22450420 ps
CPU time 0.56 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 194016 kb
Host smart-242904d0-a367-4c0b-b6ab-7f632f7eef36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511894895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2511894895
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1150122839
Short name T423
Test name
Test status
Simulation time 81164297 ps
CPU time 0.85 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 195396 kb
Host smart-2591bbc1-746d-4e62-a6a8-578d8c5b6b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150122839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1150122839
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3376629298
Short name T714
Test name
Test status
Simulation time 149244417 ps
CPU time 5.85 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 196912 kb
Host smart-2fade882-9617-43f6-b301-2170e2309004
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376629298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3376629298
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.201065421
Short name T227
Test name
Test status
Simulation time 69682710 ps
CPU time 0.81 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196688 kb
Host smart-abc42061-ed22-4f6a-a06c-8a983c27b630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201065421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.201065421
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1571796130
Short name T491
Test name
Test status
Simulation time 63834826 ps
CPU time 0.91 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 197456 kb
Host smart-9fb74f76-a4d5-45fb-8faf-099527e175d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571796130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1571796130
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3949665126
Short name T294
Test name
Test status
Simulation time 89571556 ps
CPU time 3.58 seconds
Started Feb 21 03:02:11 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 197200 kb
Host smart-09d2ca08-1396-45b8-ab6d-d73f5c3db628
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949665126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3949665126
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.214869580
Short name T288
Test name
Test status
Simulation time 152663100 ps
CPU time 1.49 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:14 PM PST 24
Peak memory 195828 kb
Host smart-4ebcc695-7345-468a-924b-8fb73df21485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214869580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.214869580
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1571303006
Short name T16
Test name
Test status
Simulation time 260191094 ps
CPU time 1.23 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 195976 kb
Host smart-e239c115-6b88-4172-a8ea-a498a9aa9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571303006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1571303006
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3221373111
Short name T176
Test name
Test status
Simulation time 396539074 ps
CPU time 1.17 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 196168 kb
Host smart-efc89e52-431c-407a-9443-d9e0ba472bc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221373111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3221373111
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2733079706
Short name T9
Test name
Test status
Simulation time 1142283771 ps
CPU time 1.21 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 198096 kb
Host smart-0d56c0a2-9291-4cc1-ba5e-7480a16b534e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733079706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2733079706
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1227154304
Short name T231
Test name
Test status
Simulation time 93765952 ps
CPU time 1.01 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:14 PM PST 24
Peak memory 196644 kb
Host smart-544f4d3f-4550-4197-87c3-527190dad939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227154304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1227154304
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.676648573
Short name T684
Test name
Test status
Simulation time 32008275 ps
CPU time 0.88 seconds
Started Feb 21 03:02:10 PM PST 24
Finished Feb 21 03:02:11 PM PST 24
Peak memory 196516 kb
Host smart-27231413-1259-4286-a2e5-7096458665ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676648573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.676648573
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3791152452
Short name T237
Test name
Test status
Simulation time 2834689253 ps
CPU time 34.2 seconds
Started Feb 21 03:02:09 PM PST 24
Finished Feb 21 03:02:44 PM PST 24
Peak memory 198248 kb
Host smart-90ac0b8b-7a28-4651-94cf-91b6ac6305ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791152452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3791152452
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1474047598
Short name T64
Test name
Test status
Simulation time 116249385007 ps
CPU time 1289.67 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:23:50 PM PST 24
Peak memory 198404 kb
Host smart-fbabb533-ccd4-4e0c-aaeb-25969fddfde2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1474047598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1474047598
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3562883825
Short name T362
Test name
Test status
Simulation time 76684072 ps
CPU time 0.61 seconds
Started Feb 21 03:02:14 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 193956 kb
Host smart-b9dcb2da-5d70-4587-a380-1f3b319a24aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562883825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3562883825
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3520942123
Short name T587
Test name
Test status
Simulation time 21343115 ps
CPU time 0.64 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 193976 kb
Host smart-0e7fe3cb-1cc2-473c-a473-b1e0698fcaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520942123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3520942123
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3608415941
Short name T634
Test name
Test status
Simulation time 248794057 ps
CPU time 11.82 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:34 PM PST 24
Peak memory 197172 kb
Host smart-6d01923a-e4e1-4e94-83a4-827813e41cb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608415941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3608415941
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1712803452
Short name T694
Test name
Test status
Simulation time 142994152 ps
CPU time 1.02 seconds
Started Feb 21 03:02:27 PM PST 24
Finished Feb 21 03:02:28 PM PST 24
Peak memory 197884 kb
Host smart-c43c9a98-2ee6-4f35-8b27-1697bd18f1c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712803452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1712803452
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2557651298
Short name T457
Test name
Test status
Simulation time 576343524 ps
CPU time 1.08 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 195864 kb
Host smart-e8b6fe44-2611-46e6-8f57-f33d09c1d390
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557651298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2557651298
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3722495485
Short name T338
Test name
Test status
Simulation time 56186509 ps
CPU time 2.34 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 196488 kb
Host smart-36218eae-cd19-440d-ac6b-2daa6aa575c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722495485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3722495485
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1744222623
Short name T157
Test name
Test status
Simulation time 529031494 ps
CPU time 2.3 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 197060 kb
Host smart-afa9ee6b-656c-4b65-a2c0-37f0fda47e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744222623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1744222623
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3516574697
Short name T386
Test name
Test status
Simulation time 199139725 ps
CPU time 1.22 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 196932 kb
Host smart-a6c63c17-b01e-496a-bde0-0acac6dfcdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516574697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3516574697
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.590088281
Short name T59
Test name
Test status
Simulation time 50135948 ps
CPU time 0.66 seconds
Started Feb 21 03:02:13 PM PST 24
Finished Feb 21 03:02:15 PM PST 24
Peak memory 194268 kb
Host smart-c469c31b-0081-4a0c-8354-6b6cafd1acda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590088281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.590088281
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3713753859
Short name T616
Test name
Test status
Simulation time 2000653404 ps
CPU time 6.38 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 198032 kb
Host smart-0cbeb68d-a8c9-4b38-8d98-cbe8582f6ddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713753859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3713753859
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1030042912
Short name T347
Test name
Test status
Simulation time 231823699 ps
CPU time 1.34 seconds
Started Feb 21 03:02:12 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 198044 kb
Host smart-5fca7bde-f58e-4296-b965-4a6f63904b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030042912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1030042912
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1205964810
Short name T482
Test name
Test status
Simulation time 90935166 ps
CPU time 1.18 seconds
Started Feb 21 03:02:09 PM PST 24
Finished Feb 21 03:02:11 PM PST 24
Peak memory 196400 kb
Host smart-e1328ef5-fb28-422b-ab4e-d5ad736b21d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205964810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1205964810
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.977754032
Short name T540
Test name
Test status
Simulation time 12670237025 ps
CPU time 76.65 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:03:35 PM PST 24
Peak memory 198228 kb
Host smart-cdc2c39e-f7bf-4def-b04e-7487905dd96e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977754032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.977754032
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3959794301
Short name T461
Test name
Test status
Simulation time 93595643243 ps
CPU time 584.88 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:12:02 PM PST 24
Peak memory 198580 kb
Host smart-13391814-e9cd-434c-8d56-400e890e279a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3959794301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3959794301
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2988998039
Short name T485
Test name
Test status
Simulation time 43530051 ps
CPU time 0.59 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 194692 kb
Host smart-20bd0b16-8378-4df8-b91e-8d7f80d3a2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988998039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2988998039
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.90173372
Short name T25
Test name
Test status
Simulation time 31830203 ps
CPU time 0.7 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 194144 kb
Host smart-6ac14221-6069-42f7-8218-48c3b5d5262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90173372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.90173372
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3507014367
Short name T179
Test name
Test status
Simulation time 877308697 ps
CPU time 6.59 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 196376 kb
Host smart-5c7f3598-98a2-419e-8c30-ed71094bde0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507014367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3507014367
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3875161794
Short name T210
Test name
Test status
Simulation time 35083110 ps
CPU time 0.8 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196732 kb
Host smart-8f6b8a61-4c46-4904-897c-7555c5d6e187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875161794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3875161794
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2920643910
Short name T31
Test name
Test status
Simulation time 64133453 ps
CPU time 1.18 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196156 kb
Host smart-e9770112-a65a-410d-bfc8-160f6bebc81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920643910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2920643910
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2874935142
Short name T260
Test name
Test status
Simulation time 301128897 ps
CPU time 2.79 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 196436 kb
Host smart-d6701b86-7ffc-47c4-8e3f-90417a747bb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874935142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2874935142
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3621719883
Short name T422
Test name
Test status
Simulation time 266871438 ps
CPU time 2.16 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 197268 kb
Host smart-94cdc8d2-f41a-4ffa-823e-78ce83193773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621719883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3621719883
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.934227364
Short name T245
Test name
Test status
Simulation time 106961210 ps
CPU time 1.28 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 195988 kb
Host smart-f8e708ac-06e0-4e5d-9eba-a5027864e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934227364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.934227364
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3946231192
Short name T161
Test name
Test status
Simulation time 40939028 ps
CPU time 0.99 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 196820 kb
Host smart-c1c82a81-bf13-4d38-a4b2-0ae561feb47d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946231192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3946231192
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3422423211
Short name T652
Test name
Test status
Simulation time 108218277 ps
CPU time 2.65 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 198076 kb
Host smart-e842d1c9-56fc-404d-8129-182779c7beb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422423211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3422423211
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2917900714
Short name T246
Test name
Test status
Simulation time 135858876 ps
CPU time 1.09 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 196868 kb
Host smart-da38b8ed-e641-4261-b9b2-b87daa724247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917900714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2917900714
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1958400069
Short name T212
Test name
Test status
Simulation time 23282629 ps
CPU time 0.77 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 195212 kb
Host smart-d76f7945-c65b-419a-aa90-453e122c12b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958400069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1958400069
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2933679106
Short name T539
Test name
Test status
Simulation time 8445740585 ps
CPU time 99.82 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:03:59 PM PST 24
Peak memory 198188 kb
Host smart-1903c2a4-79f6-44d8-8a59-c5b4685bc30c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933679106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2933679106
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2537170238
Short name T67
Test name
Test status
Simulation time 61990556903 ps
CPU time 1654.27 seconds
Started Feb 21 03:02:19 PM PST 24
Finished Feb 21 03:29:55 PM PST 24
Peak memory 198428 kb
Host smart-2fa83e17-0579-4990-ab5a-3b57c25c296b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2537170238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2537170238
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2551870310
Short name T108
Test name
Test status
Simulation time 45598918 ps
CPU time 0.55 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 194144 kb
Host smart-7a8707ff-f51a-4554-a1a5-92b0657cc04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551870310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2551870310
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.402421140
Short name T281
Test name
Test status
Simulation time 66843148 ps
CPU time 0.8 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 194116 kb
Host smart-843cb673-34b2-4a73-9cd9-2da2ddd2fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402421140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.402421140
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2306223911
Short name T483
Test name
Test status
Simulation time 192854328 ps
CPU time 8.65 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:30 PM PST 24
Peak memory 198072 kb
Host smart-890bbef7-71ed-4e3e-85bf-0c4d4842376e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306223911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2306223911
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1977621818
Short name T323
Test name
Test status
Simulation time 326188977 ps
CPU time 0.78 seconds
Started Feb 21 03:02:24 PM PST 24
Finished Feb 21 03:02:25 PM PST 24
Peak memory 196024 kb
Host smart-cd4b1790-fcab-4e3b-8d12-7b49aca73991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977621818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1977621818
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3461197819
Short name T658
Test name
Test status
Simulation time 90308144 ps
CPU time 0.8 seconds
Started Feb 21 03:02:23 PM PST 24
Finished Feb 21 03:02:25 PM PST 24
Peak memory 195400 kb
Host smart-3d4e4a1f-06a5-4176-a321-3d567f0dd9ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461197819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3461197819
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2569655048
Short name T42
Test name
Test status
Simulation time 152833145 ps
CPU time 3.02 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 198208 kb
Host smart-93d8be47-3657-4c42-9238-e46fdb713dd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569655048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2569655048
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4162462951
Short name T557
Test name
Test status
Simulation time 49581774 ps
CPU time 1.16 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 195532 kb
Host smart-b0c7f544-6462-4ce5-a13d-01fc130badd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162462951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4162462951
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2392795016
Short name T546
Test name
Test status
Simulation time 332444582 ps
CPU time 1 seconds
Started Feb 21 03:02:22 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 196044 kb
Host smart-0695cc9d-0c22-4e54-8524-89eef066b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392795016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2392795016
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.852547116
Short name T348
Test name
Test status
Simulation time 53857437 ps
CPU time 1.16 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 197264 kb
Host smart-ba5f6928-390b-49d9-af2c-1b204828865b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852547116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.852547116
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2763969252
Short name T551
Test name
Test status
Simulation time 173952380 ps
CPU time 4.24 seconds
Started Feb 21 03:02:25 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 198284 kb
Host smart-9b91c9ef-8654-4a03-b352-ec9bd827141f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763969252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2763969252
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2370579103
Short name T234
Test name
Test status
Simulation time 232130546 ps
CPU time 0.9 seconds
Started Feb 21 03:02:20 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196240 kb
Host smart-02bc5c8e-355a-49a3-8131-a321e464d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370579103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2370579103
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3175571298
Short name T22
Test name
Test status
Simulation time 50581521 ps
CPU time 1.03 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 196516 kb
Host smart-18c7ddf7-1859-4b9f-8cfd-c2379cf18eb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175571298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3175571298
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3739875906
Short name T258
Test name
Test status
Simulation time 61823426106 ps
CPU time 221.59 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:06:03 PM PST 24
Peak memory 198164 kb
Host smart-e6aa268b-617e-4788-91d4-ebb5404c34eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739875906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3739875906
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3882861557
Short name T181
Test name
Test status
Simulation time 15147288 ps
CPU time 0.59 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 194152 kb
Host smart-05a89362-4c2c-43a4-8cc5-e2f7b3465045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882861557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3882861557
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.818973439
Short name T509
Test name
Test status
Simulation time 411888733 ps
CPU time 0.86 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:20 PM PST 24
Peak memory 196424 kb
Host smart-50e8c486-b735-4bd3-89a1-dc3074573974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818973439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.818973439
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2146021111
Short name T669
Test name
Test status
Simulation time 950294589 ps
CPU time 26.32 seconds
Started Feb 21 03:02:25 PM PST 24
Finished Feb 21 03:02:52 PM PST 24
Peak memory 195832 kb
Host smart-5204ee37-9c78-4764-b9ba-a7a56dd1a0b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146021111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2146021111
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3869717719
Short name T598
Test name
Test status
Simulation time 173051760 ps
CPU time 1 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 197996 kb
Host smart-ffb2067d-3fb3-49a2-ad78-86c18a1191c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869717719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3869717719
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4207756832
Short name T418
Test name
Test status
Simulation time 20794770 ps
CPU time 0.78 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 195724 kb
Host smart-87a59e76-ae02-48e5-8a4b-635b88c0ba6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207756832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4207756832
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1985169805
Short name T520
Test name
Test status
Simulation time 196500381 ps
CPU time 2.02 seconds
Started Feb 21 03:02:18 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 198128 kb
Host smart-6b31a583-8d28-43dc-bbdd-f710e4642f10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985169805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1985169805
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4012721873
Short name T111
Test name
Test status
Simulation time 74590447 ps
CPU time 2.32 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 196632 kb
Host smart-fd027a44-6ddc-4d86-9eb2-0a2d245a3c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012721873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4012721873
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1516348958
Short name T68
Test name
Test status
Simulation time 374264505 ps
CPU time 0.77 seconds
Started Feb 21 03:02:17 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 195608 kb
Host smart-d567d381-0ef1-4cb6-8eab-0f65f8b5fd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516348958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1516348958
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.177228583
Short name T207
Test name
Test status
Simulation time 99270050 ps
CPU time 1.2 seconds
Started Feb 21 03:02:21 PM PST 24
Finished Feb 21 03:02:23 PM PST 24
Peak memory 195780 kb
Host smart-54374d44-e065-4a3e-988e-f9bfe19974bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177228583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.177228583
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3197132942
Short name T387
Test name
Test status
Simulation time 88552119 ps
CPU time 1.09 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 198116 kb
Host smart-d64c82bf-bc32-4f40-a2fc-4eab6b20cd50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197132942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3197132942
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1614658924
Short name T650
Test name
Test status
Simulation time 36203118 ps
CPU time 1.14 seconds
Started Feb 21 03:02:16 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 195880 kb
Host smart-d6057439-8a29-4dbe-8750-60e8979def03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614658924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1614658924
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2827307425
Short name T660
Test name
Test status
Simulation time 411378934 ps
CPU time 1.32 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 196980 kb
Host smart-10fde395-df30-48bf-aee7-a6547201efa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827307425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2827307425
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2611556629
Short name T356
Test name
Test status
Simulation time 633356578 ps
CPU time 12.27 seconds
Started Feb 21 03:02:15 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 198188 kb
Host smart-ce939986-5dcf-4884-a020-7b40da250eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611556629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2611556629
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2076827814
Short name T858
Test name
Test status
Simulation time 173341513 ps
CPU time 1.01 seconds
Started Feb 21 12:41:41 PM PST 24
Finished Feb 21 12:41:42 PM PST 24
Peak memory 198328 kb
Host smart-6da3c098-fd4c-4beb-a7c0-09fab2408112
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2076827814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2076827814
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3564007082
Short name T896
Test name
Test status
Simulation time 368400222 ps
CPU time 1.34 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 197124 kb
Host smart-2da07ece-42aa-4013-a349-19af87909210
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564007082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3564007082
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.29394954
Short name T938
Test name
Test status
Simulation time 25764287 ps
CPU time 0.89 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:43:21 PM PST 24
Peak memory 195516 kb
Host smart-dad26b3e-9d89-413b-970f-873ce32314f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=29394954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.29394954
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2042996133
Short name T899
Test name
Test status
Simulation time 31288390 ps
CPU time 0.8 seconds
Started Feb 21 12:41:56 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 195544 kb
Host smart-73e499f7-d160-4982-8989-628c0e2f0ec5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042996133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2042996133
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2373418131
Short name T923
Test name
Test status
Simulation time 116144995 ps
CPU time 1.1 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 196984 kb
Host smart-9f0f1cc5-b66f-425f-b6ec-e2b2820a0dbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2373418131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2373418131
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2089100404
Short name T877
Test name
Test status
Simulation time 83595546 ps
CPU time 0.85 seconds
Started Feb 21 12:41:48 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 195836 kb
Host smart-2a8e1359-3e6e-4fd3-a6a9-5211d41adad2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089100404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2089100404
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.639988872
Short name T880
Test name
Test status
Simulation time 78944331 ps
CPU time 1.34 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 196948 kb
Host smart-8fe47c30-1629-4735-9bf6-bc81b2c1faba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=639988872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.639988872
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545988766
Short name T852
Test name
Test status
Simulation time 43804675 ps
CPU time 0.94 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 196084 kb
Host smart-11fdd0c5-8962-45e9-b87c-8c9a2636dfb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545988766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.545988766
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2783707184
Short name T933
Test name
Test status
Simulation time 34295116 ps
CPU time 0.81 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 196556 kb
Host smart-6e65a7b8-d3b8-4566-900b-720e270c3fc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2783707184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2783707184
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918539277
Short name T906
Test name
Test status
Simulation time 239024758 ps
CPU time 1.31 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 197224 kb
Host smart-b28abe04-5e46-4dfd-8028-006d64977cdd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918539277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3918539277
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1471750507
Short name T848
Test name
Test status
Simulation time 82871825 ps
CPU time 0.83 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 195840 kb
Host smart-aef079a6-c9b6-4602-8ccc-6c27019bceb1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1471750507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1471750507
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.358310923
Short name T908
Test name
Test status
Simulation time 53195326 ps
CPU time 1.35 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 198496 kb
Host smart-55474552-334e-400d-a34e-938985697332
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358310923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.358310923
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2642872404
Short name T912
Test name
Test status
Simulation time 52037633 ps
CPU time 1.42 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 197076 kb
Host smart-58bca014-9e6d-41d8-9f5e-834caffbf618
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2642872404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2642872404
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.198346413
Short name T851
Test name
Test status
Simulation time 71860171 ps
CPU time 1.09 seconds
Started Feb 21 12:41:35 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 196900 kb
Host smart-48262471-938f-4a75-b81a-8654234f1023
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198346413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.198346413
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.410577617
Short name T888
Test name
Test status
Simulation time 17436307 ps
CPU time 0.69 seconds
Started Feb 21 12:41:36 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 195420 kb
Host smart-4af0f1c6-7285-45fd-8479-a9aef984d0c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=410577617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.410577617
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1755812618
Short name T898
Test name
Test status
Simulation time 118507521 ps
CPU time 1.01 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 196212 kb
Host smart-520b69ef-5938-4315-a98b-ab38454dec96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755812618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1755812618
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2097922329
Short name T849
Test name
Test status
Simulation time 70347612 ps
CPU time 0.8 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 196496 kb
Host smart-9f6f0b40-8b17-45a5-b117-fefc9490a9d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2097922329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2097922329
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258004828
Short name T863
Test name
Test status
Simulation time 27591798 ps
CPU time 0.88 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 196832 kb
Host smart-e6f87d1d-f54b-42e5-bbd7-fc2f3fc9abd4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258004828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3258004828
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1417153592
Short name T918
Test name
Test status
Simulation time 186169594 ps
CPU time 0.93 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 196076 kb
Host smart-1297c737-dc46-4146-963a-6a30151605bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1417153592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1417153592
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.816103831
Short name T857
Test name
Test status
Simulation time 62167928 ps
CPU time 0.7 seconds
Started Feb 21 12:41:47 PM PST 24
Finished Feb 21 12:41:48 PM PST 24
Peak memory 195508 kb
Host smart-5999d899-9c4a-4fff-a9ec-cb6f09b4063e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816103831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.816103831
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.975117456
Short name T917
Test name
Test status
Simulation time 61147610 ps
CPU time 1.31 seconds
Started Feb 21 12:41:42 PM PST 24
Finished Feb 21 12:41:44 PM PST 24
Peak memory 196960 kb
Host smart-9029f06d-a6ae-4cea-bbba-7fb21961489f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=975117456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.975117456
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2328720031
Short name T895
Test name
Test status
Simulation time 229387626 ps
CPU time 1.46 seconds
Started Feb 21 12:41:51 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 197236 kb
Host smart-d9580e8e-460f-488e-a6dd-f4c75f29f018
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328720031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2328720031
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2936876577
Short name T943
Test name
Test status
Simulation time 238663594 ps
CPU time 1.32 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 197012 kb
Host smart-6d041ec5-1e29-4f93-aa76-ab0b3e0b474f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2936876577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2936876577
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1432761043
Short name T859
Test name
Test status
Simulation time 247043751 ps
CPU time 1.11 seconds
Started Feb 21 12:42:23 PM PST 24
Finished Feb 21 12:42:25 PM PST 24
Peak memory 197020 kb
Host smart-beff9155-ce65-42ab-be3a-b27c0aa509ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432761043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1432761043
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2007243978
Short name T890
Test name
Test status
Simulation time 64400425 ps
CPU time 1.15 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:43:21 PM PST 24
Peak memory 195788 kb
Host smart-b09e17d4-61df-46a3-8c4f-6b50356ea28d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2007243978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2007243978
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4049557127
Short name T935
Test name
Test status
Simulation time 522163897 ps
CPU time 0.97 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:43 PM PST 24
Peak memory 196764 kb
Host smart-1b30c165-e7c2-4e32-948a-2609004db45c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049557127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4049557127
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.18526148
Short name T861
Test name
Test status
Simulation time 44203801 ps
CPU time 0.97 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 197280 kb
Host smart-8b22ae67-b6a8-48d3-96e2-c6be7b262ed5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=18526148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.18526148
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353766660
Short name T884
Test name
Test status
Simulation time 157126498 ps
CPU time 0.97 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:53 PM PST 24
Peak memory 197080 kb
Host smart-8df14070-b47b-433a-822f-7a6de4b321d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353766660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2353766660
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3745325554
Short name T855
Test name
Test status
Simulation time 217620857 ps
CPU time 1.14 seconds
Started Feb 21 12:41:59 PM PST 24
Finished Feb 21 12:42:02 PM PST 24
Peak memory 198480 kb
Host smart-ea672877-f26d-4284-ac38-cf38afc4cff9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3745325554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3745325554
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279851017
Short name T878
Test name
Test status
Simulation time 47379957 ps
CPU time 1.04 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 197620 kb
Host smart-0ea5bcf0-2485-4e13-8137-0baefdacd6b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279851017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1279851017
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2277649974
Short name T846
Test name
Test status
Simulation time 350788843 ps
CPU time 1.25 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 197096 kb
Host smart-378bbcd2-666f-43de-a0c1-e2408ea11832
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2277649974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2277649974
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2321026140
Short name T882
Test name
Test status
Simulation time 49394248 ps
CPU time 1.31 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 197272 kb
Host smart-5896b075-e186-4a83-888e-139d724adc6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321026140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2321026140
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.282511993
Short name T920
Test name
Test status
Simulation time 56249037 ps
CPU time 0.98 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 197204 kb
Host smart-50e1e10b-2c69-4663-b535-9d1a2e3cad0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=282511993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.282511993
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294516656
Short name T928
Test name
Test status
Simulation time 388333546 ps
CPU time 0.95 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 197096 kb
Host smart-6523f432-921b-45dd-a99f-336340a8aca8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294516656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.294516656
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4149362351
Short name T932
Test name
Test status
Simulation time 90860946 ps
CPU time 0.81 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 195900 kb
Host smart-74102121-8e26-453a-a36e-78d9c13b4b2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4149362351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4149362351
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1732853498
Short name T939
Test name
Test status
Simulation time 87872848 ps
CPU time 1.12 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 197056 kb
Host smart-56c6efb8-9f4b-4637-b43e-65680e58ca99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732853498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1732853498
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3761284061
Short name T885
Test name
Test status
Simulation time 49321205 ps
CPU time 0.95 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 197548 kb
Host smart-6d0fb79b-e290-4a60-9fc9-955d94ddfc1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3761284061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3761284061
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.698024399
Short name T881
Test name
Test status
Simulation time 270504259 ps
CPU time 1.17 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 196912 kb
Host smart-6315c125-f775-4851-b578-1f5d1d284eb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698024399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.698024399
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3784120305
Short name T915
Test name
Test status
Simulation time 54967770 ps
CPU time 1 seconds
Started Feb 21 12:41:42 PM PST 24
Finished Feb 21 12:41:44 PM PST 24
Peak memory 196260 kb
Host smart-c93715da-bb68-4adb-972a-605a4e203da8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3784120305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3784120305
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3797789201
Short name T873
Test name
Test status
Simulation time 47425652 ps
CPU time 1.09 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 196856 kb
Host smart-00c302b8-2cc6-4251-8b9e-7f8f9396c8da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797789201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3797789201
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1525737994
Short name T897
Test name
Test status
Simulation time 102357968 ps
CPU time 0.75 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 195708 kb
Host smart-7ff318d6-96d9-47f3-a268-2e12a0751044
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1525737994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1525737994
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2373773339
Short name T926
Test name
Test status
Simulation time 540940872 ps
CPU time 0.93 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 197812 kb
Host smart-61df1d07-6354-4c76-a0c3-04475920d5c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373773339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2373773339
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3327396579
Short name T853
Test name
Test status
Simulation time 36852970 ps
CPU time 0.86 seconds
Started Feb 21 12:42:01 PM PST 24
Finished Feb 21 12:42:04 PM PST 24
Peak memory 197300 kb
Host smart-ceb93812-377b-4d44-a58e-5afd262cdcfd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3327396579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3327396579
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4215360325
Short name T909
Test name
Test status
Simulation time 42184630 ps
CPU time 1.24 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 197024 kb
Host smart-eae00dec-cf0d-4457-a470-97bbc491422a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215360325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4215360325
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3094887088
Short name T905
Test name
Test status
Simulation time 106707238 ps
CPU time 0.83 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 195812 kb
Host smart-b86a303c-1799-488b-b1ba-eae445bcb49d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3094887088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3094887088
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.777743324
Short name T927
Test name
Test status
Simulation time 294253658 ps
CPU time 1.14 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 198360 kb
Host smart-42cce04e-9d7e-41ba-ae79-a4376b3447eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777743324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.777743324
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1535532265
Short name T860
Test name
Test status
Simulation time 675090717 ps
CPU time 1.45 seconds
Started Feb 21 12:41:31 PM PST 24
Finished Feb 21 12:41:33 PM PST 24
Peak memory 197116 kb
Host smart-060bf459-8a80-4985-b841-151dd6525da6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535532265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1535532265
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1610092724
Short name T887
Test name
Test status
Simulation time 83931726 ps
CPU time 1.45 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 198368 kb
Host smart-8593614e-6237-4772-94ad-48cadea8f8cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610092724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1610092724
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1647121783
Short name T904
Test name
Test status
Simulation time 250026549 ps
CPU time 1.22 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 197060 kb
Host smart-40943e2e-006a-4e61-a8fd-d831fd67805c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1647121783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1647121783
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1051011161
Short name T910
Test name
Test status
Simulation time 46120561 ps
CPU time 0.98 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 197024 kb
Host smart-7319e38c-480b-4b4c-8c16-1451908031c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051011161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1051011161
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3706430838
Short name T864
Test name
Test status
Simulation time 47088923 ps
CPU time 0.98 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 197020 kb
Host smart-e9df6230-9515-4c86-96da-cf5e7e81b4d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3706430838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3706430838
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233858089
Short name T868
Test name
Test status
Simulation time 130882891 ps
CPU time 0.87 seconds
Started Feb 21 12:42:14 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 196756 kb
Host smart-8abeb48b-fab3-46e3-a6ea-0e922ca16f73
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233858089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.233858089
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2595595044
Short name T850
Test name
Test status
Simulation time 53716729 ps
CPU time 1.52 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 197068 kb
Host smart-9d408933-d6d4-4907-80c9-27b1ec0c4ddc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2595595044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2595595044
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711421443
Short name T924
Test name
Test status
Simulation time 255535606 ps
CPU time 1.24 seconds
Started Feb 21 12:42:00 PM PST 24
Finished Feb 21 12:42:03 PM PST 24
Peak memory 196964 kb
Host smart-88b6d090-3472-4647-9e8c-54ef13dbbc8f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711421443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2711421443
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2675356668
Short name T894
Test name
Test status
Simulation time 136470250 ps
CPU time 1.28 seconds
Started Feb 21 12:42:00 PM PST 24
Finished Feb 21 12:42:03 PM PST 24
Peak memory 198460 kb
Host smart-9ea4a7c9-1e11-413e-b0fa-14fb89acb7fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2675356668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2675356668
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4248711317
Short name T869
Test name
Test status
Simulation time 150211652 ps
CPU time 0.91 seconds
Started Feb 21 12:41:48 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 196944 kb
Host smart-38fb85c6-1597-4eb4-88e6-7ee4553fda6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248711317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4248711317
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1056271641
Short name T862
Test name
Test status
Simulation time 41912427 ps
CPU time 0.91 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 196684 kb
Host smart-04a167a6-0ba5-49e6-aa72-76a0a73c34b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1056271641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1056271641
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671267331
Short name T903
Test name
Test status
Simulation time 685154364 ps
CPU time 0.86 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 195728 kb
Host smart-89e15eba-76d9-4454-9b2b-c45ca785e031
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671267331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3671267331
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.378000576
Short name T892
Test name
Test status
Simulation time 72240711 ps
CPU time 1.28 seconds
Started Feb 21 12:41:48 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 197044 kb
Host smart-d386abf3-1020-43d6-a82f-b0df77f118a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=378000576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.378000576
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399946058
Short name T847
Test name
Test status
Simulation time 60841334 ps
CPU time 1.23 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 196372 kb
Host smart-3b0012da-ea8f-4fc1-bd03-ac63badb9d4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399946058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1399946058
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3590143208
Short name T936
Test name
Test status
Simulation time 106236760 ps
CPU time 0.94 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 196908 kb
Host smart-364c799e-3be6-45ec-9224-612c3b09ec27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3590143208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3590143208
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.45295432
Short name T919
Test name
Test status
Simulation time 21185773 ps
CPU time 0.75 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 195864 kb
Host smart-ef3fd4ad-2047-4670-920f-401019187b58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45295432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.45295432
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1497721322
Short name T867
Test name
Test status
Simulation time 79338227 ps
CPU time 1.02 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 198428 kb
Host smart-7dc4b715-9560-4421-8810-2a0400f439e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1497721322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1497721322
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172978932
Short name T931
Test name
Test status
Simulation time 57539937 ps
CPU time 1.1 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 197096 kb
Host smart-a8526931-8a05-4a6c-a875-fc2f9cc34b9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172978932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2172978932
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1553097229
Short name T914
Test name
Test status
Simulation time 63296740 ps
CPU time 1.25 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 196952 kb
Host smart-3338b58d-9f7e-47ff-999f-5a5fbdf80ada
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1553097229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1553097229
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861428007
Short name T871
Test name
Test status
Simulation time 82062501 ps
CPU time 1.34 seconds
Started Feb 21 12:41:45 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 197052 kb
Host smart-acabf7c4-ceed-4500-b99f-fda0d272407e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861428007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.861428007
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3732064333
Short name T941
Test name
Test status
Simulation time 74549597 ps
CPU time 0.97 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 196948 kb
Host smart-7c1e7ea7-696d-4789-bef2-0c5104f34d83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3732064333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3732064333
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613804771
Short name T879
Test name
Test status
Simulation time 80276860 ps
CPU time 1.43 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 197252 kb
Host smart-e75f4592-f72d-4ffb-8b43-8528fde10b70
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613804771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2613804771
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.464473715
Short name T901
Test name
Test status
Simulation time 20912299 ps
CPU time 0.67 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 194592 kb
Host smart-2ad6da8a-1681-4b72-a8ab-d7dbb76495e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=464473715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.464473715
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511980528
Short name T929
Test name
Test status
Simulation time 73841369 ps
CPU time 1.28 seconds
Started Feb 21 12:41:41 PM PST 24
Finished Feb 21 12:41:43 PM PST 24
Peak memory 197192 kb
Host smart-ce1242b0-c4bc-45c5-819c-9f6edae65142
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511980528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1511980528
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1596569405
Short name T907
Test name
Test status
Simulation time 35267428 ps
CPU time 0.81 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 196452 kb
Host smart-d4583160-303d-477a-96de-e490e5594974
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1596569405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1596569405
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.683824350
Short name T872
Test name
Test status
Simulation time 75827953 ps
CPU time 1.26 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 197208 kb
Host smart-d3ae8e46-c418-4fa2-bec1-58200a7e4007
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683824350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.683824350
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1925204103
Short name T876
Test name
Test status
Simulation time 226276066 ps
CPU time 0.77 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 196400 kb
Host smart-c7c6e03d-bb2c-4430-b0eb-6c7114e871dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1925204103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1925204103
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1590768029
Short name T916
Test name
Test status
Simulation time 199842549 ps
CPU time 1.04 seconds
Started Feb 21 12:41:58 PM PST 24
Finished Feb 21 12:42:01 PM PST 24
Peak memory 198460 kb
Host smart-19d3e5f8-d52e-4b9d-8689-752ab8a4f871
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590768029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1590768029
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4248749269
Short name T942
Test name
Test status
Simulation time 171995005 ps
CPU time 1 seconds
Started Feb 21 12:42:14 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 198368 kb
Host smart-85452b8a-bd9e-4a00-a2b9-adff2b866bb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4248749269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4248749269
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63152799
Short name T902
Test name
Test status
Simulation time 96768869 ps
CPU time 1.38 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 197216 kb
Host smart-f13670f6-747f-49d8-8369-5c167e6317b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63152799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.63152799
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1108496477
Short name T886
Test name
Test status
Simulation time 38281697 ps
CPU time 1.12 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 196360 kb
Host smart-40394eaa-e0f0-4815-96bb-fa502ba3ca1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1108496477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1108496477
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1528070793
Short name T874
Test name
Test status
Simulation time 52910025 ps
CPU time 0.92 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 196768 kb
Host smart-1600598c-908c-4739-b877-93db6224d743
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528070793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1528070793
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2300689956
Short name T875
Test name
Test status
Simulation time 84638747 ps
CPU time 1.02 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:53 PM PST 24
Peak memory 196380 kb
Host smart-7055adcd-44fb-43cf-9266-3d3a6ae47265
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2300689956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2300689956
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.263062407
Short name T937
Test name
Test status
Simulation time 236371858 ps
CPU time 1.07 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 196260 kb
Host smart-bb2c5af6-b64c-44cc-af92-4e0deaa4df2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263062407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.263062407
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4148049067
Short name T883
Test name
Test status
Simulation time 54912661 ps
CPU time 1.07 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 197200 kb
Host smart-745b3b15-8836-4e3d-bbf1-15f4ab077281
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4148049067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4148049067
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2270175845
Short name T940
Test name
Test status
Simulation time 116451072 ps
CPU time 1.07 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 196880 kb
Host smart-e2ba910c-258b-4b41-84aa-0b56a80765cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270175845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2270175845
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.449659705
Short name T922
Test name
Test status
Simulation time 28167369 ps
CPU time 0.94 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 196924 kb
Host smart-cf2d2ea1-0640-4223-8eb4-afefb5646830
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=449659705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.449659705
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2448160476
Short name T913
Test name
Test status
Simulation time 199620829 ps
CPU time 1.24 seconds
Started Feb 21 12:42:14 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 197332 kb
Host smart-f29ac8ca-4c1b-453a-9a9f-44fc85d80056
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448160476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2448160476
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3178528072
Short name T911
Test name
Test status
Simulation time 108962100 ps
CPU time 0.93 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 198400 kb
Host smart-62e02e9d-b58d-480a-af3c-e4d658dcaf8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3178528072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3178528072
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3245135631
Short name T856
Test name
Test status
Simulation time 48648898 ps
CPU time 1.04 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 196312 kb
Host smart-13b17065-d17f-4424-b0ab-e1778d3e6f22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245135631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3245135631
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.806615384
Short name T900
Test name
Test status
Simulation time 95237080 ps
CPU time 0.93 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 196992 kb
Host smart-8a4d8f6f-467d-4df8-bc7f-f55b19ff1db8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=806615384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.806615384
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.523489981
Short name T893
Test name
Test status
Simulation time 70314730 ps
CPU time 0.69 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 194704 kb
Host smart-a10081c0-3542-4864-83bb-8091d8309136
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523489981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.523489981
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.510829921
Short name T891
Test name
Test status
Simulation time 189145713 ps
CPU time 1.22 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 197092 kb
Host smart-01e70b87-1171-4fbc-8ae6-4d857dba9818
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=510829921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.510829921
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550858728
Short name T866
Test name
Test status
Simulation time 55956949 ps
CPU time 1.01 seconds
Started Feb 21 12:41:56 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 196732 kb
Host smart-a8d2e5d9-c789-485c-a482-0daa2ffa4129
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550858728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3550858728
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2126608929
Short name T930
Test name
Test status
Simulation time 54901552 ps
CPU time 1.01 seconds
Started Feb 21 12:41:57 PM PST 24
Finished Feb 21 12:41:58 PM PST 24
Peak memory 195980 kb
Host smart-fb91981f-8ca2-44e7-ba59-a32de2062eb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2126608929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2126608929
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3724637305
Short name T944
Test name
Test status
Simulation time 33849438 ps
CPU time 1.12 seconds
Started Feb 21 12:41:39 PM PST 24
Finished Feb 21 12:41:40 PM PST 24
Peak memory 197000 kb
Host smart-d3d4b54e-4878-4682-bc20-7dc364b846d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724637305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3724637305
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.868906695
Short name T934
Test name
Test status
Simulation time 435375486 ps
CPU time 1.06 seconds
Started Feb 21 12:41:40 PM PST 24
Finished Feb 21 12:41:42 PM PST 24
Peak memory 196888 kb
Host smart-1dadd05b-6cda-4100-b477-f0ca38706d81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=868906695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.868906695
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.22329856
Short name T945
Test name
Test status
Simulation time 237248535 ps
CPU time 1.2 seconds
Started Feb 21 12:41:41 PM PST 24
Finished Feb 21 12:41:43 PM PST 24
Peak memory 198112 kb
Host smart-6c19fa45-26e5-42e6-bd40-1696c2eb2b6e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22329856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.22329856
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1510676545
Short name T870
Test name
Test status
Simulation time 151945874 ps
CPU time 1.28 seconds
Started Feb 21 12:41:40 PM PST 24
Finished Feb 21 12:41:42 PM PST 24
Peak memory 197388 kb
Host smart-634ba00e-4035-4f76-9bb4-2d742804a250
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1510676545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1510676545
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2108532389
Short name T889
Test name
Test status
Simulation time 132078682 ps
CPU time 1.11 seconds
Started Feb 21 12:41:31 PM PST 24
Finished Feb 21 12:41:32 PM PST 24
Peak memory 197244 kb
Host smart-69ad1c16-c945-4c4f-85ab-617bcd4c4c1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108532389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2108532389
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3738105018
Short name T925
Test name
Test status
Simulation time 493265929 ps
CPU time 1.14 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 196268 kb
Host smart-968a295a-2251-404a-ac0b-6e02ec809d26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3738105018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3738105018
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.182485991
Short name T854
Test name
Test status
Simulation time 150713562 ps
CPU time 1 seconds
Started Feb 21 12:41:59 PM PST 24
Finished Feb 21 12:42:03 PM PST 24
Peak memory 198340 kb
Host smart-60c1231c-9c0e-461e-900b-7f7cc11c064f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182485991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.182485991
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2959573003
Short name T921
Test name
Test status
Simulation time 47661688 ps
CPU time 0.94 seconds
Started Feb 21 12:41:57 PM PST 24
Finished Feb 21 12:41:59 PM PST 24
Peak memory 195992 kb
Host smart-98d51f51-1b0d-4b5b-ae41-3375f90a287c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2959573003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2959573003
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579063950
Short name T865
Test name
Test status
Simulation time 80912699 ps
CPU time 0.87 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 196520 kb
Host smart-7049025e-036b-4b0d-a418-32187fe3a583
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579063950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2579063950
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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