Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
32 |
0 |
32 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[1] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[2] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[3] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[4] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[5] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[6] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[7] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[8] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[9] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[10] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[11] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[12] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[13] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[14] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[15] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[16] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[17] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[18] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[19] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[20] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[21] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[22] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[23] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[24] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[25] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[26] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[27] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[28] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[29] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[30] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
all_pins[31] |
2976603 |
1 |
|
|
T20 |
1 |
|
T21 |
76 |
|
T22 |
1 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
59165878 |
1 |
|
|
T20 |
32 |
|
T21 |
1291 |
|
T22 |
32 |
values[0x1] |
36085418 |
1 |
|
|
T21 |
1141 |
|
T25 |
4967 |
|
T26 |
353 |
transitions[0x0=>0x1] |
21610679 |
1 |
|
|
T21 |
584 |
|
T25 |
2963 |
|
T26 |
199 |
transitions[0x1=>0x0] |
21610521 |
1 |
|
|
T21 |
583 |
|
T25 |
2962 |
|
T26 |
198 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
128 |
0 |
128 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
1846084 |
1 |
|
|
T20 |
1 |
|
T21 |
43 |
|
T22 |
1 |
all_pins[0] |
values[0x1] |
1130519 |
1 |
|
|
T21 |
33 |
|
T25 |
178 |
|
T26 |
18 |
all_pins[0] |
transitions[0x0=>0x1] |
697640 |
1 |
|
|
T21 |
19 |
|
T25 |
105 |
|
T26 |
15 |
all_pins[0] |
transitions[0x1=>0x0] |
695376 |
1 |
|
|
T21 |
15 |
|
T25 |
103 |
|
T26 |
2 |
all_pins[1] |
values[0x0] |
1850587 |
1 |
|
|
T20 |
1 |
|
T21 |
41 |
|
T22 |
1 |
all_pins[1] |
values[0x1] |
1126016 |
1 |
|
|
T21 |
35 |
|
T25 |
140 |
|
T26 |
4 |
all_pins[1] |
transitions[0x0=>0x1] |
671617 |
1 |
|
|
T21 |
21 |
|
T25 |
77 |
|
T26 |
1 |
all_pins[1] |
transitions[0x1=>0x0] |
676120 |
1 |
|
|
T21 |
19 |
|
T25 |
115 |
|
T26 |
15 |
all_pins[2] |
values[0x0] |
1851828 |
1 |
|
|
T20 |
1 |
|
T21 |
48 |
|
T22 |
1 |
all_pins[2] |
values[0x1] |
1124775 |
1 |
|
|
T21 |
28 |
|
T25 |
154 |
|
T26 |
3 |
all_pins[2] |
transitions[0x0=>0x1] |
673072 |
1 |
|
|
T21 |
11 |
|
T25 |
93 |
|
T26 |
3 |
all_pins[2] |
transitions[0x1=>0x0] |
674313 |
1 |
|
|
T21 |
18 |
|
T25 |
79 |
|
T26 |
4 |
all_pins[3] |
values[0x0] |
1847506 |
1 |
|
|
T20 |
1 |
|
T21 |
36 |
|
T22 |
1 |
all_pins[3] |
values[0x1] |
1129097 |
1 |
|
|
T21 |
40 |
|
T25 |
166 |
|
T26 |
17 |
all_pins[3] |
transitions[0x0=>0x1] |
677768 |
1 |
|
|
T21 |
24 |
|
T25 |
94 |
|
T26 |
17 |
all_pins[3] |
transitions[0x1=>0x0] |
673446 |
1 |
|
|
T21 |
12 |
|
T25 |
82 |
|
T26 |
3 |
all_pins[4] |
values[0x0] |
1849452 |
1 |
|
|
T20 |
1 |
|
T21 |
46 |
|
T22 |
1 |
all_pins[4] |
values[0x1] |
1127151 |
1 |
|
|
T21 |
30 |
|
T25 |
153 |
|
T26 |
10 |
all_pins[4] |
transitions[0x0=>0x1] |
673717 |
1 |
|
|
T21 |
12 |
|
T25 |
90 |
|
T26 |
4 |
all_pins[4] |
transitions[0x1=>0x0] |
675663 |
1 |
|
|
T21 |
22 |
|
T25 |
103 |
|
T26 |
11 |
all_pins[5] |
values[0x0] |
1850395 |
1 |
|
|
T20 |
1 |
|
T21 |
36 |
|
T22 |
1 |
all_pins[5] |
values[0x1] |
1126208 |
1 |
|
|
T21 |
40 |
|
T25 |
104 |
|
T26 |
8 |
all_pins[5] |
transitions[0x0=>0x1] |
671396 |
1 |
|
|
T21 |
25 |
|
T25 |
69 |
|
T26 |
5 |
all_pins[5] |
transitions[0x1=>0x0] |
672339 |
1 |
|
|
T21 |
15 |
|
T25 |
118 |
|
T26 |
7 |
all_pins[6] |
values[0x0] |
1844355 |
1 |
|
|
T20 |
1 |
|
T21 |
43 |
|
T22 |
1 |
all_pins[6] |
values[0x1] |
1132248 |
1 |
|
|
T21 |
33 |
|
T25 |
151 |
|
T26 |
9 |
all_pins[6] |
transitions[0x0=>0x1] |
678337 |
1 |
|
|
T21 |
14 |
|
T25 |
109 |
|
T26 |
9 |
all_pins[6] |
transitions[0x1=>0x0] |
672297 |
1 |
|
|
T21 |
21 |
|
T25 |
62 |
|
T26 |
8 |
all_pins[7] |
values[0x0] |
1849421 |
1 |
|
|
T20 |
1 |
|
T21 |
31 |
|
T22 |
1 |
all_pins[7] |
values[0x1] |
1127182 |
1 |
|
|
T21 |
45 |
|
T25 |
111 |
|
T26 |
9 |
all_pins[7] |
transitions[0x0=>0x1] |
673101 |
1 |
|
|
T21 |
25 |
|
T25 |
83 |
|
T26 |
6 |
all_pins[7] |
transitions[0x1=>0x0] |
678167 |
1 |
|
|
T21 |
13 |
|
T25 |
123 |
|
T26 |
6 |
all_pins[8] |
values[0x0] |
1849486 |
1 |
|
|
T20 |
1 |
|
T21 |
43 |
|
T22 |
1 |
all_pins[8] |
values[0x1] |
1127117 |
1 |
|
|
T21 |
33 |
|
T25 |
185 |
|
T26 |
10 |
all_pins[8] |
transitions[0x0=>0x1] |
672960 |
1 |
|
|
T21 |
15 |
|
T25 |
125 |
|
T26 |
6 |
all_pins[8] |
transitions[0x1=>0x0] |
673025 |
1 |
|
|
T21 |
27 |
|
T25 |
51 |
|
T26 |
5 |
all_pins[9] |
values[0x0] |
1846706 |
1 |
|
|
T20 |
1 |
|
T21 |
38 |
|
T22 |
1 |
all_pins[9] |
values[0x1] |
1129897 |
1 |
|
|
T21 |
38 |
|
T25 |
168 |
|
T26 |
11 |
all_pins[9] |
transitions[0x0=>0x1] |
678973 |
1 |
|
|
T21 |
23 |
|
T25 |
95 |
|
T26 |
4 |
all_pins[9] |
transitions[0x1=>0x0] |
676193 |
1 |
|
|
T21 |
18 |
|
T25 |
112 |
|
T26 |
3 |
all_pins[10] |
values[0x0] |
1849912 |
1 |
|
|
T20 |
1 |
|
T21 |
46 |
|
T22 |
1 |
all_pins[10] |
values[0x1] |
1126691 |
1 |
|
|
T21 |
30 |
|
T25 |
146 |
|
T26 |
21 |
all_pins[10] |
transitions[0x0=>0x1] |
675013 |
1 |
|
|
T21 |
12 |
|
T25 |
97 |
|
T26 |
13 |
all_pins[10] |
transitions[0x1=>0x0] |
678219 |
1 |
|
|
T21 |
20 |
|
T25 |
119 |
|
T26 |
3 |
all_pins[11] |
values[0x0] |
1852554 |
1 |
|
|
T20 |
1 |
|
T21 |
42 |
|
T22 |
1 |
all_pins[11] |
values[0x1] |
1124049 |
1 |
|
|
T21 |
34 |
|
T25 |
141 |
|
T26 |
12 |
all_pins[11] |
transitions[0x0=>0x1] |
675635 |
1 |
|
|
T21 |
20 |
|
T25 |
69 |
|
T26 |
1 |
all_pins[11] |
transitions[0x1=>0x0] |
678277 |
1 |
|
|
T21 |
16 |
|
T25 |
74 |
|
T26 |
10 |
all_pins[12] |
values[0x0] |
1848536 |
1 |
|
|
T20 |
1 |
|
T21 |
42 |
|
T22 |
1 |
all_pins[12] |
values[0x1] |
1128067 |
1 |
|
|
T21 |
34 |
|
T25 |
131 |
|
T26 |
3 |
all_pins[12] |
transitions[0x0=>0x1] |
673704 |
1 |
|
|
T21 |
16 |
|
T25 |
103 |
|
T26 |
3 |
all_pins[12] |
transitions[0x1=>0x0] |
669686 |
1 |
|
|
T21 |
16 |
|
T25 |
113 |
|
T26 |
12 |
all_pins[13] |
values[0x0] |
1853174 |
1 |
|
|
T20 |
1 |
|
T21 |
46 |
|
T22 |
1 |
all_pins[13] |
values[0x1] |
1123429 |
1 |
|
|
T21 |
30 |
|
T25 |
135 |
|
T26 |
9 |
all_pins[13] |
transitions[0x0=>0x1] |
671317 |
1 |
|
|
T21 |
16 |
|
T25 |
89 |
|
T26 |
9 |
all_pins[13] |
transitions[0x1=>0x0] |
675955 |
1 |
|
|
T21 |
20 |
|
T25 |
85 |
|
T26 |
3 |
all_pins[14] |
values[0x0] |
1848456 |
1 |
|
|
T20 |
1 |
|
T21 |
43 |
|
T22 |
1 |
all_pins[14] |
values[0x1] |
1128147 |
1 |
|
|
T21 |
33 |
|
T25 |
171 |
|
T26 |
6 |
all_pins[14] |
transitions[0x0=>0x1] |
677283 |
1 |
|
|
T21 |
18 |
|
T25 |
114 |
|
T26 |
2 |
all_pins[14] |
transitions[0x1=>0x0] |
672565 |
1 |
|
|
T21 |
15 |
|
T25 |
78 |
|
T26 |
5 |
all_pins[15] |
values[0x0] |
1850890 |
1 |
|
|
T20 |
1 |
|
T21 |
42 |
|
T22 |
1 |
all_pins[15] |
values[0x1] |
1125713 |
1 |
|
|
T21 |
34 |
|
T25 |
178 |
|
T26 |
14 |
all_pins[15] |
transitions[0x0=>0x1] |
672300 |
1 |
|
|
T21 |
19 |
|
T25 |
95 |
|
T26 |
10 |
all_pins[15] |
transitions[0x1=>0x0] |
674734 |
1 |
|
|
T21 |
18 |
|
T25 |
88 |
|
T26 |
2 |
all_pins[16] |
values[0x0] |
1847609 |
1 |
|
|
T20 |
1 |
|
T21 |
34 |
|
T22 |
1 |
all_pins[16] |
values[0x1] |
1128994 |
1 |
|
|
T21 |
42 |
|
T25 |
200 |
|
T26 |
12 |
all_pins[16] |
transitions[0x0=>0x1] |
674918 |
1 |
|
|
T21 |
21 |
|
T25 |
114 |
|
T26 |
4 |
all_pins[16] |
transitions[0x1=>0x0] |
671637 |
1 |
|
|
T21 |
13 |
|
T25 |
92 |
|
T26 |
6 |
all_pins[17] |
values[0x0] |
1846107 |
1 |
|
|
T20 |
1 |
|
T21 |
37 |
|
T22 |
1 |
all_pins[17] |
values[0x1] |
1130496 |
1 |
|
|
T21 |
39 |
|
T25 |
150 |
|
T26 |
14 |
all_pins[17] |
transitions[0x0=>0x1] |
675763 |
1 |
|
|
T21 |
19 |
|
T25 |
79 |
|
T26 |
6 |
all_pins[17] |
transitions[0x1=>0x0] |
674261 |
1 |
|
|
T21 |
22 |
|
T25 |
129 |
|
T26 |
4 |
all_pins[18] |
values[0x0] |
1850660 |
1 |
|
|
T20 |
1 |
|
T21 |
47 |
|
T22 |
1 |
all_pins[18] |
values[0x1] |
1125943 |
1 |
|
|
T21 |
29 |
|
T25 |
150 |
|
T26 |
11 |
all_pins[18] |
transitions[0x0=>0x1] |
672766 |
1 |
|
|
T21 |
11 |
|
T25 |
77 |
|
T26 |
2 |
all_pins[18] |
transitions[0x1=>0x0] |
677319 |
1 |
|
|
T21 |
21 |
|
T25 |
77 |
|
T26 |
5 |
all_pins[19] |
values[0x0] |
1848240 |
1 |
|
|
T20 |
1 |
|
T21 |
35 |
|
T22 |
1 |
all_pins[19] |
values[0x1] |
1128363 |
1 |
|
|
T21 |
41 |
|
T25 |
211 |
|
T26 |
15 |
all_pins[19] |
transitions[0x0=>0x1] |
676830 |
1 |
|
|
T21 |
25 |
|
T25 |
122 |
|
T26 |
8 |
all_pins[19] |
transitions[0x1=>0x0] |
674410 |
1 |
|
|
T21 |
13 |
|
T25 |
61 |
|
T26 |
4 |
all_pins[20] |
values[0x0] |
1843980 |
1 |
|
|
T20 |
1 |
|
T21 |
40 |
|
T22 |
1 |
all_pins[20] |
values[0x1] |
1132623 |
1 |
|
|
T21 |
36 |
|
T25 |
157 |
|
T26 |
12 |
all_pins[20] |
transitions[0x0=>0x1] |
675811 |
1 |
|
|
T21 |
18 |
|
T25 |
55 |
|
T26 |
4 |
all_pins[20] |
transitions[0x1=>0x0] |
671551 |
1 |
|
|
T21 |
23 |
|
T25 |
109 |
|
T26 |
7 |
all_pins[21] |
values[0x0] |
1850531 |
1 |
|
|
T20 |
1 |
|
T21 |
38 |
|
T22 |
1 |
all_pins[21] |
values[0x1] |
1126072 |
1 |
|
|
T21 |
38 |
|
T25 |
138 |
|
T26 |
8 |
all_pins[21] |
transitions[0x0=>0x1] |
674926 |
1 |
|
|
T21 |
18 |
|
T25 |
47 |
|
T26 |
7 |
all_pins[21] |
transitions[0x1=>0x0] |
681477 |
1 |
|
|
T21 |
16 |
|
T25 |
66 |
|
T26 |
11 |
all_pins[22] |
values[0x0] |
1847793 |
1 |
|
|
T20 |
1 |
|
T21 |
34 |
|
T22 |
1 |
all_pins[22] |
values[0x1] |
1128810 |
1 |
|
|
T21 |
42 |
|
T25 |
157 |
|
T26 |
13 |
all_pins[22] |
transitions[0x0=>0x1] |
676429 |
1 |
|
|
T21 |
20 |
|
T25 |
96 |
|
T26 |
7 |
all_pins[22] |
transitions[0x1=>0x0] |
673691 |
1 |
|
|
T21 |
16 |
|
T25 |
77 |
|
T26 |
2 |
all_pins[23] |
values[0x0] |
1848315 |
1 |
|
|
T20 |
1 |
|
T21 |
46 |
|
T22 |
1 |
all_pins[23] |
values[0x1] |
1128288 |
1 |
|
|
T21 |
30 |
|
T25 |
160 |
|
T26 |
7 |
all_pins[23] |
transitions[0x0=>0x1] |
675003 |
1 |
|
|
T21 |
13 |
|
T25 |
98 |
|
T26 |
1 |
all_pins[23] |
transitions[0x1=>0x0] |
675525 |
1 |
|
|
T21 |
25 |
|
T25 |
95 |
|
T26 |
7 |
all_pins[24] |
values[0x0] |
1848492 |
1 |
|
|
T20 |
1 |
|
T21 |
29 |
|
T22 |
1 |
all_pins[24] |
values[0x1] |
1128111 |
1 |
|
|
T21 |
47 |
|
T25 |
134 |
|
T26 |
18 |
all_pins[24] |
transitions[0x0=>0x1] |
672900 |
1 |
|
|
T21 |
28 |
|
T25 |
71 |
|
T26 |
11 |
all_pins[24] |
transitions[0x1=>0x0] |
673077 |
1 |
|
|
T21 |
11 |
|
T25 |
97 |
|
T28 |
21 |
all_pins[25] |
values[0x0] |
1850699 |
1 |
|
|
T20 |
1 |
|
T21 |
41 |
|
T22 |
1 |
all_pins[25] |
values[0x1] |
1125904 |
1 |
|
|
T21 |
35 |
|
T25 |
185 |
|
T26 |
12 |
all_pins[25] |
transitions[0x0=>0x1] |
673345 |
1 |
|
|
T21 |
14 |
|
T25 |
125 |
|
T26 |
4 |
all_pins[25] |
transitions[0x1=>0x0] |
675552 |
1 |
|
|
T21 |
26 |
|
T25 |
74 |
|
T26 |
10 |
all_pins[26] |
values[0x0] |
1851203 |
1 |
|
|
T20 |
1 |
|
T21 |
31 |
|
T22 |
1 |
all_pins[26] |
values[0x1] |
1125400 |
1 |
|
|
T21 |
45 |
|
T25 |
157 |
|
T26 |
2 |
all_pins[26] |
transitions[0x0=>0x1] |
671653 |
1 |
|
|
T21 |
29 |
|
T25 |
95 |
|
T28 |
12 |
all_pins[26] |
transitions[0x1=>0x0] |
672157 |
1 |
|
|
T21 |
19 |
|
T25 |
123 |
|
T26 |
10 |
all_pins[27] |
values[0x0] |
1851818 |
1 |
|
|
T20 |
1 |
|
T21 |
42 |
|
T22 |
1 |
all_pins[27] |
values[0x1] |
1124785 |
1 |
|
|
T21 |
34 |
|
T25 |
134 |
|
T26 |
18 |
all_pins[27] |
transitions[0x0=>0x1] |
674920 |
1 |
|
|
T21 |
11 |
|
T25 |
75 |
|
T26 |
17 |
all_pins[27] |
transitions[0x1=>0x0] |
675535 |
1 |
|
|
T21 |
22 |
|
T25 |
98 |
|
T26 |
1 |
all_pins[28] |
values[0x0] |
1844700 |
1 |
|
|
T20 |
1 |
|
T21 |
42 |
|
T22 |
1 |
all_pins[28] |
values[0x1] |
1131903 |
1 |
|
|
T21 |
34 |
|
T25 |
148 |
|
T26 |
14 |
all_pins[28] |
transitions[0x0=>0x1] |
680393 |
1 |
|
|
T21 |
18 |
|
T25 |
97 |
|
T26 |
4 |
all_pins[28] |
transitions[0x1=>0x0] |
673275 |
1 |
|
|
T21 |
18 |
|
T25 |
83 |
|
T26 |
8 |
all_pins[29] |
values[0x0] |
1853037 |
1 |
|
|
T20 |
1 |
|
T21 |
38 |
|
T22 |
1 |
all_pins[29] |
values[0x1] |
1123566 |
1 |
|
|
T21 |
38 |
|
T25 |
148 |
|
T26 |
13 |
all_pins[29] |
transitions[0x0=>0x1] |
669746 |
1 |
|
|
T21 |
21 |
|
T25 |
99 |
|
T26 |
7 |
all_pins[29] |
transitions[0x1=>0x0] |
678083 |
1 |
|
|
T21 |
17 |
|
T25 |
99 |
|
T26 |
8 |
all_pins[30] |
values[0x0] |
1845162 |
1 |
|
|
T20 |
1 |
|
T21 |
45 |
|
T22 |
1 |
all_pins[30] |
values[0x1] |
1131441 |
1 |
|
|
T21 |
31 |
|
T25 |
149 |
|
T26 |
14 |
all_pins[30] |
transitions[0x0=>0x1] |
676625 |
1 |
|
|
T21 |
12 |
|
T25 |
98 |
|
T26 |
6 |
all_pins[30] |
transitions[0x1=>0x0] |
668750 |
1 |
|
|
T21 |
19 |
|
T25 |
97 |
|
T26 |
5 |
all_pins[31] |
values[0x0] |
1848190 |
1 |
|
|
T20 |
1 |
|
T21 |
46 |
|
T22 |
1 |
all_pins[31] |
values[0x1] |
1128413 |
1 |
|
|
T21 |
30 |
|
T25 |
177 |
|
T26 |
6 |
all_pins[31] |
transitions[0x0=>0x1] |
674818 |
1 |
|
|
T21 |
16 |
|
T25 |
108 |
|
T26 |
3 |
all_pins[31] |
transitions[0x1=>0x0] |
677846 |
1 |
|
|
T21 |
17 |
|
T25 |
80 |
|
T26 |
11 |