Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[1]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[2]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[3]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[4]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[5]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[6]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[7]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[8]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[9]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[10]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[11]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[12]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[13]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[14]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[15]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[16]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[17]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[18]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[19]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[20]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[21]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[22]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[23]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[24]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[25]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[26]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[27]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[28]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[29]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[30]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[31]	10504307	1			T20	145		T21	38534		T22	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193737950

1

T20

3649

T21

608512

T22

32

auto[1]

142399874

1

T20

991

T21

624576

T23

3734

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271813428

1

T20

4096

T21

123308

T22

32

auto[1]

64324396

1

T20

544

T23

367

T24

10186

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252917158

1

T20

2267

T21

123308

T22

32

auto[1]

83220666

1

T20

2373

T23

2396

T24

10337

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3854529	1			T20	63		T21	17518		T22	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3037063	1			T20	14		T21	21016		T23	109
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1014324	1			T20	13		T23	14		T24	163
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1189986	1			T20	37		T24	154		T25	328
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	407646	1			T20	10		T23	2		T25	13
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1000759	1			T20	8		T24	182		T25	273
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3850479	1			T20	24		T21	18147		T22	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3035491	1			T20	6		T21	20387		T23	106
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1013285	1			T20	2		T23	18		T24	187
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1194880	1			T20	76		T24	134		T25	357
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	406844	1			T20	15		T25	15		T111	26
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1003328	1			T20	22		T24	146		T25	281
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3848749	1			T20	69		T21	19745		T22	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3044445	1			T20	16		T21	18789		T23	57
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1014566	1			T20	10		T24	134		T25	191
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1190471	1			T20	36		T23	13		T24	193
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	406536	1			T20	2		T23	62		T25	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	999540	1			T20	12		T23	4		T24	146
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3858945	1			T20	42		T21	19271		T22	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3038218	1			T20	19		T21	19263		T23	74
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1012283	1			T20	4		T23	9		T24	142
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1187814	1			T20	63		T23	7		T24	201
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	404510	1			T20	11		T23	32		T25	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1002537	1			T20	6		T23	2		T24	142
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3829669	1			T20	41		T21	18434		T22	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3055984	1			T20	2		T21	20100		T23	34
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1008458	1			T20	2		T23	4		T24	150
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1195751	1			T20	73		T23	17		T24	156
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	407648	1			T20	13		T23	76		T25	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1006797	1			T20	14		T23	12		T24	183
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3851505	1			T20	37		T21	18031		T22	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3038601	1			T20	7		T21	20503		T23	94
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1009438	1			T20	5		T23	10		T24	160
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1196483	1			T20	68		T23	2		T24	162
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	404781	1			T20	14		T23	15		T25	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1003499	1			T20	14		T23	5		T24	205
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3847960	1			T20	81		T21	20440		T22	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3048439	1			T20	19		T21	18094		T23	78
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1011727	1			T20	10		T23	6		T24	177
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1191192	1			T20	17		T23	10		T24	144
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	403344	1			T20	4		T23	31		T25	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1001645	1			T20	14		T23	2		T24	128
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3851154	1			T20	49		T21	19203		T22	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3040644	1			T20	5		T21	19331		T23	80
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1009854	1			T20	8		T23	8		T24	148
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1192529	1			T20	62		T23	10		T24	176
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	406784	1			T20	19		T23	24		T25	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1003342	1			T20	2		T23	7		T24	172
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3850214	1			T20	69		T21	18232		T22	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3041810	1			T20	8		T21	20302		T23	42
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1012025	1			T20	13		T24	176		T25	243
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1196366	1			T20	38		T23	24		T24	151
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	404703	1			T20	15		T23	71		T25	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	999189	1			T20	2		T23	6		T24	124
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3847060	1			T20	46		T21	19037		T22	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3044094	1			T20	5		T21	19497		T23	58
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1016271	1			T20	9		T23	4		T24	169
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1189741	1			T20	64		T23	15		T24	144
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	406129	1			T20	17		T23	46		T25	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1001012	1			T20	4		T23	2		T24	156
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3850777	1			T20	49		T21	19511		T22	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3045995	1			T20	13		T21	19023		T23	70
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1007839	1			T20	12		T23	4		T24	158
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1194294	1			T20	46		T23	6		T24	168
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	405773	1			T20	17		T23	49		T25	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	999629	1			T20	8		T23	8		T24	187
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3848085	1			T20	31		T21	16892		T22	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3042785	1			T20	13		T21	21642		T23	18
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1009423	1			T20	2		T23	2		T24	159
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1189495	1			T20	66		T23	16		T24	158
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	408428	1			T20	17		T23	90		T25	4
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1006091	1			T20	16		T23	11		T24	162
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3846027	1			T20	39		T21	19546		T22	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3038882	1			T20	6		T21	18988		T23	5
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1008330	1			T20	4		T24	128		T25	253
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1198940	1			T20	70		T23	17		T24	167
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	408596	1			T20	16		T23	117		T25	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1003532	1			T20	10		T23	9		T24	184
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3850273	1			T20	60		T21	19338		T22	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3042182	1			T20	13		T21	19196		T23	42
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1012417	1			T20	12		T23	6		T24	160
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1191557	1			T20	36		T23	23		T24	146
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	404867	1			T20	11		T23	68		T25	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1003011	1			T20	13		T23	2		T24	169
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3852897	1			T20	10		T21	19564		T22	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3036390	1			T20	1		T21	18970		T23	18
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1007676	1			T23	2		T24	158		T25	145
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1194595	1			T20	97		T23	24		T24	158
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	407259	1			T20	18		T23	95		T25	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1005490	1			T20	19		T23	7		T24	154
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3852884	1			T20	88		T21	18963		T22	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3047966	1			T20	18		T21	19571		T23	62
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1012027	1			T20	19		T23	4		T24	157
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1187846	1			T20	17		T23	11		T24	140
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	402644	1			T20	1		T23	61		T25	24
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1000940	1			T20	2		T23	3		T24	200
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3848703	1			T20	59		T21	20005		T22	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3041068	1			T20	11		T21	18529		T23	48
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1006494	1			T20	6		T23	6		T24	132
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1198497	1			T20	50		T23	13		T24	139
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	408826	1			T20	9		T23	72		T25	24
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1000719	1			T20	10		T23	5		T24	176
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3858304	1			T20	74		T21	19228		T22	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3040103	1			T20	20		T21	19306		T23	28
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1007922	1			T20	12		T23	8		T24	134
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1194161	1			T20	31		T23	16		T24	192
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	406392	1			T20	4		T23	79		T25	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	997425	1			T20	4		T23	7		T24	155
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3852617	1			T20	84		T21	19946		T22	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3043327	1			T20	13		T21	18588		T23	69
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1008563	1			T20	10		T23	4		T24	136
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1194338	1			T20	31		T23	11		T24	170
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	403774	1			T20	5		T23	34		T25	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1001688	1			T20	2		T23	12		T24	185
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3847131	1			T20	36		T21	18352		T22	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3053222	1			T20	4		T21	20182		T23	72
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1006697	1			T20	4		T23	8		T24	180
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1190188	1			T20	77		T23	10		T24	148
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	407457	1			T20	18		T23	30		T25	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	999612	1			T20	6		T23	8		T24	148
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3856572	1			T20	29		T21	20331		T22	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3040721	1			T20	5		T21	18203		T23	46
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1005711	1			T20	6		T23	2		T24	169
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1195824	1			T20	87		T23	21		T24	156
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	406593	1			T20	13		T23	66		T25	8
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	998886	1			T20	5		T23	6		T24	152
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3855486	1			T20	46		T21	18299		T22	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3045467	1			T20	12		T21	20235		T23	72
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1010234	1			T20	10		T23	9		T24	175
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1191230	1			T20	61		T23	5		T24	150
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	405532	1			T20	11		T23	37		T25	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	996358	1			T20	5		T23	8		T24	146
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3855569	1			T20	98		T21	17982		T22	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3040740	1			T20	21		T21	20552		T23	30
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1008403	1			T20	21		T23	4		T24	176
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1191912	1			T20	4		T23	11		T24	132
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	408654	1			T20	1		T23	84		T25	10
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	999029	1			T23	16		T24	176		T25	261
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3846267	1			T20	51		T21	20485		T22	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3039312	1			T20	8		T21	18049		T23	16
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1009692	1			T20	14		T24	155		T25	224
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1200209	1			T20	57		T23	31		T24	166
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	405980	1			T20	9		T23	90		T25	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1002847	1			T20	6		T23	9		T24	170
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3861098	1			T20	35		T21	17464		T22	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3037216	1			T20	4		T21	21070		T23	46
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1008851	1			T20	10		T23	4		T24	158
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1189524	1			T20	77		T23	22		T24	146
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	407980	1			T20	15		T23	61		T25	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	999638	1			T20	4		T23	8		T24	158
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3865721	1			T20	46		T21	19676		T22	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3029964	1			T20	8		T21	18858		T23	73
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1004317	1			T20	7		T23	4		T24	127
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1199278	1			T20	57		T23	7		T24	186
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	408157	1			T20	17		T23	37		T25	10
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	996870	1			T20	10		T24	166		T25	225
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3853276	1			T20	7		T21	20070		T22	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3046940	1			T20	2		T21	18464		T23	80
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1006966	1			T23	5		T24	158		T25	252
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1193208	1			T20	91		T23	15		T24	154
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	406020	1			T20	22		T23	28		T25	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	997897	1			T20	23		T23	7		T24	122
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3862083	1			T20	104		T21	18913		T22	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3038489	1			T20	28		T21	19621		T23	68
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1008214	1			T20	12		T23	2		T24	152
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1190135	1			T20	1		T23	13		T24	172
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	405338	1			T23	46		T25	18		T111	21
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1000048	1			T23	3		T24	148		T25	215
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3850779	1			T20	9		T21	19476		T22	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3048407	1			T20	1		T21	19058		T23	85
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1010779	1			T23	12		T24	122		T25	215
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1188401	1			T20	99		T23	2		T24	180
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	405721	1			T20	28		T23	25		T25	11
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1000220	1			T20	8		T24	195		T25	228
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3850309	1			T20	55		T21	18643		T22	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3050558	1			T20	12		T21	19891		T23	20
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1005756	1			T20	10		T23	2		T24	194
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1192485	1			T20	48		T23	19		T24	125
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	407243	1			T20	11		T23	97		T25	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	997956	1			T20	9		T23	10		T24	154
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3849702	1			T20	49		T21	19161		T22	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3047000	1			T20	11		T21	19373		T23	45
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1002954	1			T23	2		T24	126		T25	205
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1198051	1			T20	57		T23	19		T24	205
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	408865	1			T20	12		T23	58		T25	15
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	997735	1			T20	16		T23	12		T24	158
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3849654	1			T20	79		T21	18609		T22	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3044074	1			T20	13		T21	19925		T23	30
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1005587	1			T20	23		T23	2		T24	170
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1197008	1			T20	26		T23	27		T24	168
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	407940	1			T20	4		T23	74		T25	16
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1000044	1			T23	11		T24	147		T25	268

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal