Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[1]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[2]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[3]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[4]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[5]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[6]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[7]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[8]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[9]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[10]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[11]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[12]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[13]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[14]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[15]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[16]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[17]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[18]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[19]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[20]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[21]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[22]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[23]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[24]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[25]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[26]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[27]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[28]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[29]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[30]	10504307	1			T20	145		T21	38534		T22	1
bins_for_gpio_bits[31]	10504307	1			T20	145		T21	38534		T22	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193737950

1

T20

3649

T21

608512

T22

32

auto[1]

142399874

1

T20

991

T21

624576

T23

3734

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193730348

1

T20

3649

T21

608512

T22

32

auto[1]

142407476

1

T20

991

T21

624576

T23

3734

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	5879432	1			T20	110		T21	17518		T22	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	179160	1			T20	3		T23	5		T24	41
bins_for_gpio_bits[0]	auto[1]	auto[0]	179407	1			T20	3		T23	5		T24	41
bins_for_gpio_bits[0]	auto[1]	auto[1]	4266308	1			T20	29		T21	21016		T23	106
bins_for_gpio_bits[1]	auto[0]	auto[0]	5879367	1			T20	96		T21	18147		T22	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	179043	1			T20	6		T23	6		T24	42
bins_for_gpio_bits[1]	auto[1]	auto[0]	179277	1			T20	6		T23	6		T24	42
bins_for_gpio_bits[1]	auto[1]	auto[1]	4266620	1			T20	37		T21	20387		T23	100
bins_for_gpio_bits[2]	auto[0]	auto[0]	5874834	1			T20	111		T21	19745		T22	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	178719	1			T20	4		T24	44		T25	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	178952	1			T20	4		T24	44		T25	34
bins_for_gpio_bits[2]	auto[1]	auto[1]	4271802	1			T20	26		T21	18789		T23	123
bins_for_gpio_bits[3]	auto[0]	auto[0]	5879982	1			T20	107		T21	19271		T22	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	178834	1			T20	2		T23	4		T24	43
bins_for_gpio_bits[3]	auto[1]	auto[0]	179060	1			T20	2		T23	4		T24	43
bins_for_gpio_bits[3]	auto[1]	auto[1]	4266431	1			T20	34		T21	19263		T23	104
bins_for_gpio_bits[4]	auto[0]	auto[0]	5854131	1			T20	111		T21	18434		T22	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	179483	1			T20	5		T23	1		T24	40
bins_for_gpio_bits[4]	auto[1]	auto[0]	179747	1			T20	5		T23	1		T24	41
bins_for_gpio_bits[4]	auto[1]	auto[1]	4290946	1			T20	24		T21	20100		T23	121
bins_for_gpio_bits[5]	auto[0]	auto[0]	5878146	1			T20	105		T21	18031		T22	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	179066	1			T20	5		T23	4		T24	45
bins_for_gpio_bits[5]	auto[1]	auto[0]	179280	1			T20	5		T23	4		T24	46
bins_for_gpio_bits[5]	auto[1]	auto[1]	4267815	1			T20	30		T21	20503		T23	110
bins_for_gpio_bits[6]	auto[0]	auto[0]	5871581	1			T20	105		T21	20440		T22	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	179082	1			T20	3		T23	2		T24	34
bins_for_gpio_bits[6]	auto[1]	auto[0]	179298	1			T20	3		T23	2		T24	34
bins_for_gpio_bits[6]	auto[1]	auto[1]	4274346	1			T20	34		T21	18094		T23	109
bins_for_gpio_bits[7]	auto[0]	auto[0]	5874706	1			T20	118		T21	19203		T22	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	178626	1			T20	1		T23	3		T24	43
bins_for_gpio_bits[7]	auto[1]	auto[0]	178831	1			T20	1		T23	3		T24	43
bins_for_gpio_bits[7]	auto[1]	auto[1]	4272144	1			T20	25		T21	19331		T23	108
bins_for_gpio_bits[8]	auto[0]	auto[0]	5879922	1			T20	119		T21	18232		T22	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	178433	1			T20	1		T24	38		T25	40
bins_for_gpio_bits[8]	auto[1]	auto[0]	178683	1			T20	1		T24	38		T25	40
bins_for_gpio_bits[8]	auto[1]	auto[1]	4267269	1			T20	24		T21	20302		T23	119
bins_for_gpio_bits[9]	auto[0]	auto[0]	5873876	1			T20	117		T21	19037		T22	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	178937	1			T20	2		T23	2		T24	41
bins_for_gpio_bits[9]	auto[1]	auto[0]	179196	1			T20	2		T23	2		T24	41
bins_for_gpio_bits[9]	auto[1]	auto[1]	4272298	1			T20	24		T21	19497		T23	104
bins_for_gpio_bits[10]	auto[0]	auto[0]	5873810	1			T20	104		T21	19511		T22	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	178842	1			T20	3		T23	2		T24	40
bins_for_gpio_bits[10]	auto[1]	auto[0]	179100	1			T20	3		T23	2		T24	41
bins_for_gpio_bits[10]	auto[1]	auto[1]	4272555	1			T20	35		T21	19023		T23	125
bins_for_gpio_bits[11]	auto[0]	auto[0]	5867801	1			T20	93		T21	16892		T22	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	178955	1			T20	6		T23	1		T24	38
bins_for_gpio_bits[11]	auto[1]	auto[0]	179202	1			T20	6		T23	1		T24	38
bins_for_gpio_bits[11]	auto[1]	auto[1]	4278349	1			T20	40		T21	21642		T23	118
bins_for_gpio_bits[12]	auto[0]	auto[0]	5873840	1			T20	110		T21	19546		T22	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	179193	1			T20	3		T24	40		T25	34
bins_for_gpio_bits[12]	auto[1]	auto[0]	179457	1			T20	3		T24	40		T25	34
bins_for_gpio_bits[12]	auto[1]	auto[1]	4271817	1			T20	29		T21	18988		T23	131
bins_for_gpio_bits[13]	auto[0]	auto[0]	5874844	1			T20	104		T21	19338		T22	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	179126	1			T20	4		T23	2		T24	41
bins_for_gpio_bits[13]	auto[1]	auto[0]	179403	1			T20	4		T23	2		T24	42
bins_for_gpio_bits[13]	auto[1]	auto[1]	4270934	1			T20	33		T21	19196		T23	110
bins_for_gpio_bits[14]	auto[0]	auto[0]	5876187	1			T20	101		T21	19564		T22	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	178742	1			T20	6		T23	1		T24	39
bins_for_gpio_bits[14]	auto[1]	auto[0]	178981	1			T20	6		T23	1		T24	39
bins_for_gpio_bits[14]	auto[1]	auto[1]	4270397	1			T20	32		T21	18970		T23	119
bins_for_gpio_bits[15]	auto[0]	auto[0]	5873719	1			T20	123		T21	18963		T22	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	178819	1			T20	1		T23	2		T24	48
bins_for_gpio_bits[15]	auto[1]	auto[0]	179038	1			T20	1		T23	2		T24	48
bins_for_gpio_bits[15]	auto[1]	auto[1]	4272731	1			T20	20		T21	19571		T23	124
bins_for_gpio_bits[16]	auto[0]	auto[0]	5874647	1			T20	110		T21	20005		T22	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	178787	1			T20	5		T23	2		T24	37
bins_for_gpio_bits[16]	auto[1]	auto[0]	179047	1			T20	5		T23	2		T24	37
bins_for_gpio_bits[16]	auto[1]	auto[1]	4271826	1			T20	25		T21	18529		T23	123
bins_for_gpio_bits[17]	auto[0]	auto[0]	5881434	1			T20	115		T21	19228		T22	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	178727	1			T20	2		T23	2		T24	35
bins_for_gpio_bits[17]	auto[1]	auto[0]	178953	1			T20	2		T23	2		T24	36
bins_for_gpio_bits[17]	auto[1]	auto[1]	4265193	1			T20	26		T21	19306		T23	112
bins_for_gpio_bits[18]	auto[0]	auto[0]	5875942	1			T20	124		T21	19946		T22	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	179334	1			T20	1		T23	1		T24	38
bins_for_gpio_bits[18]	auto[1]	auto[0]	179576	1			T20	1		T23	1		T24	39
bins_for_gpio_bits[18]	auto[1]	auto[1]	4269455	1			T20	19		T21	18588		T23	114
bins_for_gpio_bits[19]	auto[0]	auto[0]	5865300	1			T20	115		T21	18352		T22	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	178517	1			T20	2		T23	3		T24	41
bins_for_gpio_bits[19]	auto[1]	auto[0]	178716	1			T20	2		T23	3		T24	41
bins_for_gpio_bits[19]	auto[1]	auto[1]	4281774	1			T20	26		T21	20182		T23	107
bins_for_gpio_bits[20]	auto[0]	auto[0]	5879108	1			T20	121		T21	20331		T22	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	178738	1			T20	1		T23	1		T24	46
bins_for_gpio_bits[20]	auto[1]	auto[0]	178999	1			T20	1		T23	1		T24	46
bins_for_gpio_bits[20]	auto[1]	auto[1]	4267462	1			T20	22		T21	18203		T23	117
bins_for_gpio_bits[21]	auto[0]	auto[0]	5878046	1			T20	116		T21	18299		T22	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	178648	1			T20	1		T23	4		T24	39
bins_for_gpio_bits[21]	auto[1]	auto[0]	178904	1			T20	1		T23	4		T24	39
bins_for_gpio_bits[21]	auto[1]	auto[1]	4268709	1			T20	27		T21	20235		T23	113
bins_for_gpio_bits[22]	auto[0]	auto[0]	5876932	1			T20	123		T21	17982		T22	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	178708	1			T23	1		T24	38		T25	31
bins_for_gpio_bits[22]	auto[1]	auto[0]	178952	1			T23	1		T24	38		T25	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	4269715	1			T20	22		T21	20552		T23	129
bins_for_gpio_bits[23]	auto[0]	auto[0]	5875912	1			T20	120		T21	20485		T22	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	180054	1			T20	2		T24	45		T25	29
bins_for_gpio_bits[23]	auto[1]	auto[0]	180256	1			T20	2		T24	45		T25	29
bins_for_gpio_bits[23]	auto[1]	auto[1]	4268085	1			T20	21		T21	18049		T23	115
bins_for_gpio_bits[24]	auto[0]	auto[0]	5880265	1			T20	121		T21	17464		T22	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	178981	1			T20	1		T23	2		T24	35
bins_for_gpio_bits[24]	auto[1]	auto[0]	179208	1			T20	1		T23	2		T24	35
bins_for_gpio_bits[24]	auto[1]	auto[1]	4265853	1			T20	22		T21	21070		T23	113
bins_for_gpio_bits[25]	auto[0]	auto[0]	5889942	1			T20	106		T21	19676		T22	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	179136	1			T20	4		T23	2		T24	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	179374	1			T20	4		T23	2		T24	41
bins_for_gpio_bits[25]	auto[1]	auto[1]	4255855	1			T20	31		T21	18858		T23	108
bins_for_gpio_bits[26]	auto[0]	auto[0]	5874127	1			T20	92		T21	20070		T22	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	179068	1			T20	6		T23	2		T24	40
bins_for_gpio_bits[26]	auto[1]	auto[0]	179323	1			T20	6		T23	2		T24	40
bins_for_gpio_bits[26]	auto[1]	auto[1]	4271789	1			T20	41		T21	18464		T23	113
bins_for_gpio_bits[27]	auto[0]	auto[0]	5881780	1			T20	117		T21	18913		T22	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	178416	1			T23	1		T24	38		T25	37
bins_for_gpio_bits[27]	auto[1]	auto[0]	178652	1			T23	1		T24	38		T25	37
bins_for_gpio_bits[27]	auto[1]	auto[1]	4265459	1			T20	28		T21	19621		T23	116
bins_for_gpio_bits[28]	auto[0]	auto[0]	5870862	1			T20	105		T21	19476		T22	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	178908	1			T20	3		T23	5		T24	40
bins_for_gpio_bits[28]	auto[1]	auto[0]	179097	1			T20	3		T23	5		T24	41
bins_for_gpio_bits[28]	auto[1]	auto[1]	4275440	1			T20	34		T21	19058		T23	105
bins_for_gpio_bits[29]	auto[0]	auto[0]	5869913	1			T20	111		T21	18643		T22	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	178410	1			T20	2		T23	1		T24	42
bins_for_gpio_bits[29]	auto[1]	auto[0]	178637	1			T20	2		T23	1		T24	42
bins_for_gpio_bits[29]	auto[1]	auto[1]	4277347	1			T20	30		T21	19891		T23	126
bins_for_gpio_bits[30]	auto[0]	auto[0]	5871341	1			T20	101		T21	19161		T22	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	179114	1			T20	5		T23	1		T24	44
bins_for_gpio_bits[30]	auto[1]	auto[0]	179366	1			T20	5		T23	1		T24	44
bins_for_gpio_bits[30]	auto[1]	auto[1]	4274486	1			T20	34		T21	19373		T23	114
bins_for_gpio_bits[31]	auto[0]	auto[0]	5872780	1			T20	128		T21	18609		T22	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	179233	1			T23	1		T24	42		T25	31
bins_for_gpio_bits[31]	auto[1]	auto[0]	179469	1			T23	1		T24	43		T25	31
bins_for_gpio_bits[31]	auto[1]	auto[1]	4272825	1			T20	17		T21	19925		T23	114