Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6414509 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4214962 |
1 |
|
|
T25 |
633 |
|
T26 |
37 |
|
T29 |
194 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10096198 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
533273 |
1 |
|
|
T25 |
21 |
|
T26 |
2 |
|
T29 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6393971 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4235500 |
1 |
|
|
T25 |
457 |
|
T26 |
40 |
|
T29 |
174 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1858668 |
1 |
|
|
T25 |
163 |
|
T26 |
18 |
|
T29 |
83 |
| auto[1] |
auto[0] |
auto[1] |
267786 |
1 |
|
|
T25 |
5 |
|
T29 |
5 |
|
T30 |
7881 |
| auto[1] |
auto[1] |
auto[0] |
1843559 |
1 |
|
|
T25 |
273 |
|
T26 |
20 |
|
T29 |
80 |
| auto[1] |
auto[1] |
auto[1] |
265487 |
1 |
|
|
T25 |
16 |
|
T26 |
2 |
|
T29 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6402320 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4227151 |
1 |
|
|
T25 |
509 |
|
T26 |
17 |
|
T29 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099164 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530307 |
1 |
|
|
T25 |
27 |
|
T29 |
8 |
|
T30 |
16188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416895 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4212576 |
1 |
|
|
T25 |
508 |
|
T26 |
30 |
|
T29 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1841322 |
1 |
|
|
T25 |
209 |
|
T26 |
24 |
|
T29 |
69 |
| auto[1] |
auto[0] |
auto[1] |
264350 |
1 |
|
|
T25 |
11 |
|
T29 |
2 |
|
T30 |
7731 |
| auto[1] |
auto[1] |
auto[0] |
1840947 |
1 |
|
|
T25 |
272 |
|
T26 |
6 |
|
T29 |
68 |
| auto[1] |
auto[1] |
auto[1] |
265957 |
1 |
|
|
T25 |
16 |
|
T29 |
6 |
|
T30 |
8457 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6406250 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4223221 |
1 |
|
|
T25 |
503 |
|
T26 |
33 |
|
T29 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10097178 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
532293 |
1 |
|
|
T25 |
19 |
|
T26 |
1 |
|
T29 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6407504 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4221967 |
1 |
|
|
T25 |
584 |
|
T26 |
15 |
|
T29 |
200 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1844733 |
1 |
|
|
T25 |
277 |
|
T26 |
4 |
|
T29 |
130 |
| auto[1] |
auto[0] |
auto[1] |
266958 |
1 |
|
|
T25 |
8 |
|
T29 |
13 |
|
T30 |
8081 |
| auto[1] |
auto[1] |
auto[0] |
1844941 |
1 |
|
|
T25 |
288 |
|
T26 |
10 |
|
T29 |
54 |
| auto[1] |
auto[1] |
auto[1] |
265335 |
1 |
|
|
T25 |
11 |
|
T26 |
1 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6414827 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4214644 |
1 |
|
|
T25 |
488 |
|
T26 |
25 |
|
T29 |
154 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10098884 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530587 |
1 |
|
|
T25 |
18 |
|
T26 |
3 |
|
T29 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6419499 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4209972 |
1 |
|
|
T25 |
446 |
|
T26 |
23 |
|
T29 |
213 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1835779 |
1 |
|
|
T25 |
207 |
|
T26 |
8 |
|
T29 |
108 |
| auto[1] |
auto[0] |
auto[1] |
264285 |
1 |
|
|
T25 |
9 |
|
T26 |
2 |
|
T29 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1843606 |
1 |
|
|
T25 |
221 |
|
T26 |
12 |
|
T29 |
86 |
| auto[1] |
auto[1] |
auto[1] |
266302 |
1 |
|
|
T25 |
9 |
|
T26 |
1 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413216 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4216255 |
1 |
|
|
T25 |
492 |
|
T26 |
17 |
|
T29 |
148 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10096163 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
533308 |
1 |
|
|
T25 |
19 |
|
T26 |
1 |
|
T29 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6409485 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4219986 |
1 |
|
|
T25 |
388 |
|
T26 |
18 |
|
T29 |
221 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1843824 |
1 |
|
|
T25 |
183 |
|
T26 |
6 |
|
T29 |
113 |
| auto[1] |
auto[0] |
auto[1] |
266650 |
1 |
|
|
T25 |
10 |
|
T29 |
10 |
|
T30 |
8622 |
| auto[1] |
auto[1] |
auto[0] |
1842854 |
1 |
|
|
T25 |
186 |
|
T26 |
11 |
|
T29 |
90 |
| auto[1] |
auto[1] |
auto[1] |
266658 |
1 |
|
|
T25 |
9 |
|
T26 |
1 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6431014 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4198457 |
1 |
|
|
T25 |
459 |
|
T26 |
20 |
|
T29 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10096549 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
532922 |
1 |
|
|
T25 |
20 |
|
T26 |
1 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6401815 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4227656 |
1 |
|
|
T25 |
452 |
|
T26 |
17 |
|
T29 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1864925 |
1 |
|
|
T25 |
268 |
|
T26 |
16 |
|
T29 |
38 |
| auto[1] |
auto[0] |
auto[1] |
268879 |
1 |
|
|
T25 |
14 |
|
T26 |
1 |
|
T30 |
8888 |
| auto[1] |
auto[1] |
auto[0] |
1829809 |
1 |
|
|
T25 |
164 |
|
T29 |
84 |
|
T30 |
50400 |
| auto[1] |
auto[1] |
auto[1] |
264043 |
1 |
|
|
T25 |
6 |
|
T29 |
6 |
|
T30 |
7750 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417496 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4211975 |
1 |
|
|
T25 |
578 |
|
T26 |
25 |
|
T29 |
203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10098282 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
531189 |
1 |
|
|
T25 |
20 |
|
T26 |
2 |
|
T29 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416582 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4212889 |
1 |
|
|
T25 |
477 |
|
T26 |
33 |
|
T29 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845980 |
1 |
|
|
T25 |
188 |
|
T26 |
17 |
|
T29 |
65 |
| auto[1] |
auto[0] |
auto[1] |
266772 |
1 |
|
|
T25 |
11 |
|
T29 |
2 |
|
T30 |
8748 |
| auto[1] |
auto[1] |
auto[0] |
1835720 |
1 |
|
|
T25 |
269 |
|
T26 |
14 |
|
T29 |
81 |
| auto[1] |
auto[1] |
auto[1] |
264417 |
1 |
|
|
T25 |
9 |
|
T26 |
2 |
|
T29 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6420637 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4208834 |
1 |
|
|
T25 |
544 |
|
T26 |
28 |
|
T29 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10102155 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
527316 |
1 |
|
|
T25 |
24 |
|
T26 |
2 |
|
T29 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430728 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4198743 |
1 |
|
|
T25 |
622 |
|
T26 |
34 |
|
T29 |
164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845102 |
1 |
|
|
T25 |
294 |
|
T26 |
17 |
|
T29 |
104 |
| auto[1] |
auto[0] |
auto[1] |
264677 |
1 |
|
|
T25 |
13 |
|
T26 |
1 |
|
T29 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1826325 |
1 |
|
|
T25 |
304 |
|
T26 |
15 |
|
T29 |
50 |
| auto[1] |
auto[1] |
auto[1] |
262639 |
1 |
|
|
T25 |
11 |
|
T26 |
1 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400431 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4229040 |
1 |
|
|
T25 |
651 |
|
T26 |
19 |
|
T29 |
228 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10097735 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
531736 |
1 |
|
|
T25 |
31 |
|
T26 |
2 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6415324 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4214147 |
1 |
|
|
T25 |
563 |
|
T26 |
13 |
|
T29 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1844573 |
1 |
|
|
T25 |
203 |
|
T26 |
11 |
|
T29 |
25 |
| auto[1] |
auto[0] |
auto[1] |
266377 |
1 |
|
|
T25 |
15 |
|
T26 |
2 |
|
T30 |
8378 |
| auto[1] |
auto[1] |
auto[0] |
1837838 |
1 |
|
|
T25 |
329 |
|
T29 |
74 |
|
T30 |
54234 |
| auto[1] |
auto[1] |
auto[1] |
265359 |
1 |
|
|
T25 |
16 |
|
T29 |
4 |
|
T30 |
8560 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6394252 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4235219 |
1 |
|
|
T25 |
625 |
|
T26 |
46 |
|
T29 |
128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10098574 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530897 |
1 |
|
|
T25 |
15 |
|
T26 |
1 |
|
T29 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6415608 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4213863 |
1 |
|
|
T25 |
404 |
|
T26 |
16 |
|
T29 |
176 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1849858 |
1 |
|
|
T25 |
133 |
|
T29 |
96 |
|
T30 |
52941 |
| auto[1] |
auto[0] |
auto[1] |
266412 |
1 |
|
|
T25 |
4 |
|
T29 |
9 |
|
T30 |
8039 |
| auto[1] |
auto[1] |
auto[0] |
1833108 |
1 |
|
|
T25 |
256 |
|
T26 |
15 |
|
T29 |
68 |
| auto[1] |
auto[1] |
auto[1] |
264485 |
1 |
|
|
T25 |
11 |
|
T26 |
1 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412973 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4216498 |
1 |
|
|
T25 |
524 |
|
T26 |
16 |
|
T29 |
157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10098660 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530811 |
1 |
|
|
T25 |
25 |
|
T26 |
2 |
|
T29 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417374 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4212097 |
1 |
|
|
T25 |
507 |
|
T26 |
22 |
|
T29 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1848656 |
1 |
|
|
T25 |
245 |
|
T26 |
10 |
|
T29 |
52 |
| auto[1] |
auto[0] |
auto[1] |
267216 |
1 |
|
|
T25 |
9 |
|
T26 |
1 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1832630 |
1 |
|
|
T25 |
237 |
|
T26 |
10 |
|
T29 |
44 |
| auto[1] |
auto[1] |
auto[1] |
263595 |
1 |
|
|
T25 |
16 |
|
T26 |
1 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416465 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4213006 |
1 |
|
|
T25 |
682 |
|
T26 |
32 |
|
T29 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099091 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530380 |
1 |
|
|
T25 |
25 |
|
T26 |
1 |
|
T29 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417943 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4211528 |
1 |
|
|
T25 |
609 |
|
T26 |
15 |
|
T29 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1843483 |
1 |
|
|
T25 |
199 |
|
T26 |
4 |
|
T29 |
73 |
| auto[1] |
auto[0] |
auto[1] |
266457 |
1 |
|
|
T25 |
7 |
|
T29 |
6 |
|
T30 |
8472 |
| auto[1] |
auto[1] |
auto[0] |
1837665 |
1 |
|
|
T25 |
385 |
|
T26 |
10 |
|
T29 |
85 |
| auto[1] |
auto[1] |
auto[1] |
263923 |
1 |
|
|
T25 |
18 |
|
T26 |
1 |
|
T29 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6408767 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4220704 |
1 |
|
|
T25 |
578 |
|
T26 |
3 |
|
T29 |
154 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10096664 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
532807 |
1 |
|
|
T25 |
30 |
|
T26 |
3 |
|
T29 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6405865 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4223606 |
1 |
|
|
T25 |
609 |
|
T26 |
38 |
|
T29 |
130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1844672 |
1 |
|
|
T25 |
260 |
|
T26 |
32 |
|
T29 |
79 |
| auto[1] |
auto[0] |
auto[1] |
266089 |
1 |
|
|
T25 |
16 |
|
T26 |
3 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1846127 |
1 |
|
|
T25 |
319 |
|
T26 |
3 |
|
T29 |
42 |
| auto[1] |
auto[1] |
auto[1] |
266718 |
1 |
|
|
T25 |
14 |
|
T29 |
4 |
|
T30 |
8858 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6426117 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4203354 |
1 |
|
|
T25 |
529 |
|
T26 |
28 |
|
T29 |
162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10093821 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
535650 |
1 |
|
|
T25 |
22 |
|
T26 |
2 |
|
T29 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6387066 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4242405 |
1 |
|
|
T25 |
558 |
|
T26 |
20 |
|
T29 |
181 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1867178 |
1 |
|
|
T25 |
294 |
|
T26 |
1 |
|
T29 |
80 |
| auto[1] |
auto[0] |
auto[1] |
270466 |
1 |
|
|
T25 |
12 |
|
T29 |
7 |
|
T30 |
8455 |
| auto[1] |
auto[1] |
auto[0] |
1839577 |
1 |
|
|
T25 |
242 |
|
T26 |
17 |
|
T29 |
90 |
| auto[1] |
auto[1] |
auto[1] |
265184 |
1 |
|
|
T25 |
10 |
|
T26 |
2 |
|
T29 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6410686 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4218785 |
1 |
|
|
T25 |
528 |
|
T26 |
21 |
|
T29 |
140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099392 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
530079 |
1 |
|
|
T25 |
20 |
|
T26 |
1 |
|
T29 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6415740 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4213731 |
1 |
|
|
T25 |
396 |
|
T26 |
24 |
|
T29 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845856 |
1 |
|
|
T25 |
165 |
|
T26 |
6 |
|
T29 |
66 |
| auto[1] |
auto[0] |
auto[1] |
266285 |
1 |
|
|
T25 |
8 |
|
T29 |
3 |
|
T30 |
7862 |
| auto[1] |
auto[1] |
auto[0] |
1837796 |
1 |
|
|
T25 |
211 |
|
T26 |
17 |
|
T29 |
51 |
| auto[1] |
auto[1] |
auto[1] |
263794 |
1 |
|
|
T25 |
12 |
|
T26 |
1 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6427448 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4202023 |
1 |
|
|
T25 |
668 |
|
T26 |
43 |
|
T29 |
207 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099588 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
529883 |
1 |
|
|
T25 |
17 |
|
T26 |
1 |
|
T29 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6422980 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4206491 |
1 |
|
|
T25 |
471 |
|
T26 |
33 |
|
T29 |
172 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1851639 |
1 |
|
|
T25 |
162 |
|
T26 |
7 |
|
T29 |
68 |
| auto[1] |
auto[0] |
auto[1] |
266959 |
1 |
|
|
T25 |
5 |
|
T26 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1824969 |
1 |
|
|
T25 |
292 |
|
T26 |
25 |
|
T29 |
94 |
| auto[1] |
auto[1] |
auto[1] |
262924 |
1 |
|
|
T25 |
12 |
|
T29 |
9 |
|
T30 |
8776 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6443788 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4185683 |
1 |
|
|
T25 |
637 |
|
T26 |
25 |
|
T29 |
152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10096323 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
533148 |
1 |
|
|
T25 |
21 |
|
T26 |
1 |
|
T29 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6408582 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4220889 |
1 |
|
|
T25 |
662 |
|
T26 |
31 |
|
T29 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1862983 |
1 |
|
|
T25 |
232 |
|
T26 |
19 |
|
T29 |
55 |
| auto[1] |
auto[0] |
auto[1] |
270050 |
1 |
|
|
T25 |
10 |
|
T26 |
1 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1824758 |
1 |
|
|
T25 |
409 |
|
T26 |
11 |
|
T29 |
40 |
| auto[1] |
auto[1] |
auto[1] |
263098 |
1 |
|
|
T25 |
11 |
|
T29 |
2 |
|
T30 |
7996 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6445142 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4184329 |
1 |
|
|
T25 |
429 |
|
T26 |
46 |
|
T29 |
156 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099772 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
529699 |
1 |
|
|
T25 |
18 |
|
T29 |
13 |
|
T30 |
16092 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6419956 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4209515 |
1 |
|
|
T25 |
425 |
|
T26 |
7 |
|
T29 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1853217 |
1 |
|
|
T25 |
208 |
|
T26 |
4 |
|
T29 |
91 |
| auto[1] |
auto[0] |
auto[1] |
265805 |
1 |
|
|
T25 |
9 |
|
T29 |
9 |
|
T30 |
7621 |
| auto[1] |
auto[1] |
auto[0] |
1826599 |
1 |
|
|
T25 |
199 |
|
T26 |
3 |
|
T29 |
69 |
| auto[1] |
auto[1] |
auto[1] |
263894 |
1 |
|
|
T25 |
9 |
|
T29 |
4 |
|
T30 |
8471 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6389220 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4240251 |
1 |
|
|
T25 |
673 |
|
T26 |
33 |
|
T29 |
221 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099510 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
529961 |
1 |
|
|
T25 |
20 |
|
T26 |
1 |
|
T29 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6409642 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4219829 |
1 |
|
|
T25 |
482 |
|
T26 |
20 |
|
T29 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845892 |
1 |
|
|
T25 |
199 |
|
T29 |
61 |
|
T30 |
51930 |
| auto[1] |
auto[0] |
auto[1] |
265376 |
1 |
|
|
T25 |
7 |
|
T29 |
7 |
|
T30 |
8131 |
| auto[1] |
auto[1] |
auto[0] |
1843976 |
1 |
|
|
T25 |
263 |
|
T26 |
19 |
|
T29 |
125 |
| auto[1] |
auto[1] |
auto[1] |
264585 |
1 |
|
|
T25 |
13 |
|
T26 |
1 |
|
T29 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6414336 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4215135 |
1 |
|
|
T25 |
536 |
|
T26 |
10 |
|
T29 |
108 |