Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6406250 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4223221 |
1 |
|
|
T25 |
503 |
|
T26 |
33 |
|
T29 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8834655 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
1794816 |
1 |
|
|
T25 |
133 |
|
T26 |
31 |
|
T29 |
99 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6422268 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4207203 |
1 |
|
|
T25 |
528 |
|
T26 |
38 |
|
T29 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1200561 |
1 |
|
|
T25 |
227 |
|
T26 |
4 |
|
T29 |
25 |
| auto[1] |
auto[0] |
auto[1] |
899529 |
1 |
|
|
T25 |
50 |
|
T26 |
10 |
|
T29 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1211826 |
1 |
|
|
T25 |
168 |
|
T26 |
3 |
|
T29 |
7 |
| auto[1] |
auto[1] |
auto[1] |
895287 |
1 |
|
|
T25 |
83 |
|
T26 |
21 |
|
T29 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |