Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417496 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4211975 |
1 |
|
|
T25 |
578 |
|
T26 |
25 |
|
T29 |
203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8835231 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
1794240 |
1 |
|
|
T25 |
166 |
|
T26 |
1 |
|
T29 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417040 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4212431 |
1 |
|
|
T25 |
623 |
|
T26 |
10 |
|
T29 |
187 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1209143 |
1 |
|
|
T25 |
183 |
|
T26 |
4 |
|
T29 |
50 |
| auto[1] |
auto[0] |
auto[1] |
896491 |
1 |
|
|
T25 |
88 |
|
T29 |
20 |
|
T30 |
22938 |
| auto[1] |
auto[1] |
auto[0] |
1209048 |
1 |
|
|
T25 |
274 |
|
T26 |
5 |
|
T29 |
67 |
| auto[1] |
auto[1] |
auto[1] |
897749 |
1 |
|
|
T25 |
78 |
|
T26 |
1 |
|
T29 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |