Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412973 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4216498 |
1 |
|
|
T25 |
524 |
|
T26 |
16 |
|
T29 |
157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8837895 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
1791576 |
1 |
|
|
T25 |
135 |
|
T26 |
17 |
|
T29 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413298 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4216173 |
1 |
|
|
T25 |
640 |
|
T26 |
35 |
|
T29 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1216247 |
1 |
|
|
T25 |
255 |
|
T26 |
9 |
|
T29 |
18 |
| auto[1] |
auto[0] |
auto[1] |
899141 |
1 |
|
|
T25 |
73 |
|
T26 |
14 |
|
T29 |
37 |
| auto[1] |
auto[1] |
auto[0] |
1208350 |
1 |
|
|
T25 |
250 |
|
T26 |
9 |
|
T29 |
15 |
| auto[1] |
auto[1] |
auto[1] |
892435 |
1 |
|
|
T25 |
62 |
|
T26 |
3 |
|
T29 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |