Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6397836 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4231635 |
1 |
|
|
T25 |
483 |
|
T26 |
20 |
|
T29 |
189 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10101626 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
527845 |
1 |
|
|
T25 |
21 |
|
T26 |
3 |
|
T29 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428885 |
1 |
|
|
T20 |
80 |
|
T21 |
38534 |
|
T22 |
1 |
| auto[1] |
4200586 |
1 |
|
|
T25 |
609 |
|
T26 |
25 |
|
T29 |
146 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1835466 |
1 |
|
|
T25 |
325 |
|
T26 |
11 |
|
T29 |
68 |
| auto[1] |
auto[0] |
auto[1] |
263615 |
1 |
|
|
T25 |
13 |
|
T26 |
2 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1837275 |
1 |
|
|
T25 |
263 |
|
T26 |
11 |
|
T29 |
70 |
| auto[1] |
auto[1] |
auto[1] |
264230 |
1 |
|
|
T25 |
8 |
|
T26 |
1 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |