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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 935
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T759 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3558169570 Feb 25 12:40:23 PM PST 24 Feb 25 12:40:25 PM PST 24 52257360 ps
T760 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1156509883 Feb 25 12:40:07 PM PST 24 Feb 25 12:40:08 PM PST 24 119976097 ps
T761 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1035337501 Feb 25 12:40:02 PM PST 24 Feb 25 12:40:03 PM PST 24 30680641 ps
T94 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3352989519 Feb 25 12:39:56 PM PST 24 Feb 25 12:39:57 PM PST 24 46400225 ps
T762 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1324741610 Feb 25 12:39:44 PM PST 24 Feb 25 12:39:46 PM PST 24 92372782 ps
T763 /workspace/coverage/cover_reg_top/14.gpio_intr_test.39003059 Feb 25 12:40:04 PM PST 24 Feb 25 12:40:04 PM PST 24 22212376 ps
T764 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3279654733 Feb 25 12:40:02 PM PST 24 Feb 25 12:40:04 PM PST 24 175256164 ps
T765 /workspace/coverage/cover_reg_top/9.gpio_intr_test.823138446 Feb 25 12:39:53 PM PST 24 Feb 25 12:39:53 PM PST 24 49610573 ps
T766 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3799878964 Feb 25 12:39:50 PM PST 24 Feb 25 12:39:56 PM PST 24 11285932 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1219785765 Feb 25 12:39:49 PM PST 24 Feb 25 12:39:52 PM PST 24 452480668 ps
T768 /workspace/coverage/cover_reg_top/27.gpio_intr_test.4248268397 Feb 25 12:40:00 PM PST 24 Feb 25 12:40:02 PM PST 24 34120226 ps
T95 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2081781753 Feb 25 12:40:18 PM PST 24 Feb 25 12:40:24 PM PST 24 99901840 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2696212689 Feb 25 12:39:52 PM PST 24 Feb 25 12:39:53 PM PST 24 37468069 ps
T769 /workspace/coverage/cover_reg_top/20.gpio_intr_test.797035206 Feb 25 12:40:13 PM PST 24 Feb 25 12:40:14 PM PST 24 18019636 ps
T770 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2734475072 Feb 25 12:39:48 PM PST 24 Feb 25 12:39:51 PM PST 24 234311738 ps
T771 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.930711616 Feb 25 12:40:06 PM PST 24 Feb 25 12:40:07 PM PST 24 18330177 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3356661098 Feb 25 12:39:45 PM PST 24 Feb 25 12:39:46 PM PST 24 64858869 ps
T773 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4227270278 Feb 25 12:40:12 PM PST 24 Feb 25 12:40:13 PM PST 24 28677825 ps
T774 /workspace/coverage/cover_reg_top/23.gpio_intr_test.935990806 Feb 25 12:40:08 PM PST 24 Feb 25 12:40:09 PM PST 24 27523379 ps
T775 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1655696281 Feb 25 12:39:42 PM PST 24 Feb 25 12:39:44 PM PST 24 34624062 ps
T776 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1777849798 Feb 25 12:40:03 PM PST 24 Feb 25 12:40:04 PM PST 24 15834686 ps
T777 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3159380247 Feb 25 12:39:57 PM PST 24 Feb 25 12:39:59 PM PST 24 67890187 ps
T778 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.482419547 Feb 25 12:40:03 PM PST 24 Feb 25 12:40:05 PM PST 24 113268024 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1120589075 Feb 25 12:39:41 PM PST 24 Feb 25 12:39:42 PM PST 24 18629279 ps
T86 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.920614172 Feb 25 12:39:44 PM PST 24 Feb 25 12:39:45 PM PST 24 14243750 ps
T780 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3507525630 Feb 25 12:39:59 PM PST 24 Feb 25 12:40:01 PM PST 24 18910414 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.284316285 Feb 25 12:39:42 PM PST 24 Feb 25 12:39:43 PM PST 24 19200777 ps
T782 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3757962822 Feb 25 12:40:04 PM PST 24 Feb 25 12:40:05 PM PST 24 40932709 ps
T783 /workspace/coverage/cover_reg_top/26.gpio_intr_test.447748600 Feb 25 12:39:58 PM PST 24 Feb 25 12:39:59 PM PST 24 11997046 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3596724981 Feb 25 12:39:54 PM PST 24 Feb 25 12:39:55 PM PST 24 63283959 ps
T785 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.388867592 Feb 25 12:39:38 PM PST 24 Feb 25 12:39:40 PM PST 24 240698294 ps
T786 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2227288096 Feb 25 12:40:13 PM PST 24 Feb 25 12:40:16 PM PST 24 316030115 ps
T787 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1037315356 Feb 25 12:40:00 PM PST 24 Feb 25 12:40:02 PM PST 24 63714092 ps
T788 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2590960089 Feb 25 12:39:52 PM PST 24 Feb 25 12:39:55 PM PST 24 144897594 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2782947801 Feb 25 12:40:03 PM PST 24 Feb 25 12:40:04 PM PST 24 31193899 ps
T790 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2356272466 Feb 25 12:39:52 PM PST 24 Feb 25 12:39:53 PM PST 24 65370439 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2761224549 Feb 25 12:40:08 PM PST 24 Feb 25 12:40:09 PM PST 24 25376910 ps
T47 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4222536397 Feb 25 12:39:54 PM PST 24 Feb 25 12:39:55 PM PST 24 306085435 ps
T792 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1661671495 Feb 25 12:39:48 PM PST 24 Feb 25 12:39:49 PM PST 24 62266696 ps
T793 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.452789702 Feb 25 12:39:44 PM PST 24 Feb 25 12:39:45 PM PST 24 19512552 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1714052207 Feb 25 12:39:48 PM PST 24 Feb 25 12:39:49 PM PST 24 15239619 ps
T795 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1660738030 Feb 25 12:40:12 PM PST 24 Feb 25 12:40:13 PM PST 24 40874155 ps
T796 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1234194070 Feb 25 12:39:55 PM PST 24 Feb 25 12:39:56 PM PST 24 13068311 ps
T797 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2459479436 Feb 25 12:39:50 PM PST 24 Feb 25 12:39:51 PM PST 24 39652088 ps
T798 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2725850386 Feb 25 12:39:55 PM PST 24 Feb 25 12:39:58 PM PST 24 452630157 ps
T799 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1105144399 Feb 25 12:39:42 PM PST 24 Feb 25 12:39:43 PM PST 24 14337623 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1720327111 Feb 25 12:39:43 PM PST 24 Feb 25 12:39:44 PM PST 24 39871626 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4062206030 Feb 25 12:39:42 PM PST 24 Feb 25 12:39:43 PM PST 24 87230951 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4170538528 Feb 25 12:39:58 PM PST 24 Feb 25 12:39:59 PM PST 24 11674701 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1556089117 Feb 25 12:39:50 PM PST 24 Feb 25 12:39:50 PM PST 24 23957177 ps
T804 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3503386820 Feb 25 12:40:08 PM PST 24 Feb 25 12:40:09 PM PST 24 47248517 ps
T805 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2873792903 Feb 25 12:40:00 PM PST 24 Feb 25 12:40:02 PM PST 24 40024600 ps
T806 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3557616112 Feb 25 12:39:58 PM PST 24 Feb 25 12:39:59 PM PST 24 41754077 ps
T807 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.704042822 Feb 25 12:39:52 PM PST 24 Feb 25 12:39:54 PM PST 24 220022438 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2255781316 Feb 25 12:40:03 PM PST 24 Feb 25 12:40:04 PM PST 24 68497532 ps
T809 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2175467060 Feb 25 12:40:16 PM PST 24 Feb 25 12:40:16 PM PST 24 44470448 ps
T810 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.797898724 Feb 25 12:39:56 PM PST 24 Feb 25 12:39:57 PM PST 24 37262837 ps
T811 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.629616160 Feb 25 12:40:07 PM PST 24 Feb 25 12:40:08 PM PST 24 206194413 ps
T109 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.663983150 Feb 25 12:39:52 PM PST 24 Feb 25 12:39:53 PM PST 24 141165542 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3706645574 Feb 25 12:39:57 PM PST 24 Feb 25 12:39:59 PM PST 24 33226539 ps
T813 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.200015087 Feb 25 12:39:45 PM PST 24 Feb 25 12:39:45 PM PST 24 37700697 ps
T814 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3740545698 Feb 25 12:40:04 PM PST 24 Feb 25 12:40:05 PM PST 24 275121391 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3483814592 Feb 25 12:39:58 PM PST 24 Feb 25 12:39:59 PM PST 24 62016256 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3638756982 Feb 25 12:39:44 PM PST 24 Feb 25 12:39:45 PM PST 24 18963551 ps
T817 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1373544079 Feb 25 12:39:56 PM PST 24 Feb 25 12:39:57 PM PST 24 13487410 ps
T818 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.905763218 Feb 25 12:39:46 PM PST 24 Feb 25 12:39:47 PM PST 24 130544098 ps
T819 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2903568975 Feb 25 12:39:53 PM PST 24 Feb 25 12:39:53 PM PST 24 24221480 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1685553631 Feb 25 12:40:01 PM PST 24 Feb 25 12:40:04 PM PST 24 177628210 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2368765705 Feb 25 12:39:27 PM PST 24 Feb 25 12:39:28 PM PST 24 12631101 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3839732564 Feb 25 12:39:41 PM PST 24 Feb 25 12:39:42 PM PST 24 31653616 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2207666209 Feb 25 12:39:57 PM PST 24 Feb 25 12:39:59 PM PST 24 24356337 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1498101571 Feb 25 12:40:00 PM PST 24 Feb 25 12:40:02 PM PST 24 57514217 ps
T824 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.779080862 Feb 25 12:39:49 PM PST 24 Feb 25 12:39:56 PM PST 24 157904494 ps
T825 /workspace/coverage/cover_reg_top/32.gpio_intr_test.371199936 Feb 25 12:39:56 PM PST 24 Feb 25 12:39:56 PM PST 24 35910471 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4081508943 Feb 25 12:39:46 PM PST 24 Feb 25 12:39:47 PM PST 24 13930177 ps
T826 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2385017209 Feb 25 12:40:10 PM PST 24 Feb 25 12:40:11 PM PST 24 19873653 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4033104237 Feb 25 12:40:15 PM PST 24 Feb 25 12:40:17 PM PST 24 151233640 ps
T828 /workspace/coverage/cover_reg_top/42.gpio_intr_test.4256834245 Feb 25 12:39:56 PM PST 24 Feb 25 12:39:57 PM PST 24 12346909 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1777993190 Feb 25 12:40:13 PM PST 24 Feb 25 12:40:14 PM PST 24 14364723 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1867241663 Feb 25 12:40:10 PM PST 24 Feb 25 12:40:11 PM PST 24 80909437 ps
T831 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.412841318 Feb 25 12:40:07 PM PST 24 Feb 25 12:40:08 PM PST 24 33016592 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3085063151 Feb 25 12:39:53 PM PST 24 Feb 25 12:39:54 PM PST 24 49704572 ps
T833 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2565901484 Feb 25 12:40:08 PM PST 24 Feb 25 12:40:09 PM PST 24 50553770 ps
T834 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3390694930 Feb 25 12:39:39 PM PST 24 Feb 25 12:39:40 PM PST 24 26710979 ps
T835 /workspace/coverage/cover_reg_top/36.gpio_intr_test.265289501 Feb 25 12:39:58 PM PST 24 Feb 25 12:39:59 PM PST 24 72148321 ps
T836 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3428113732 Feb 25 01:17:09 PM PST 24 Feb 25 01:17:10 PM PST 24 90378161 ps
T837 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545279912 Feb 25 01:17:28 PM PST 24 Feb 25 01:17:29 PM PST 24 286656549 ps
T838 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4280180095 Feb 25 01:17:21 PM PST 24 Feb 25 01:17:23 PM PST 24 190421408 ps
T839 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2423546207 Feb 25 01:17:23 PM PST 24 Feb 25 01:17:25 PM PST 24 184646670 ps
T840 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2217478939 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 363630012 ps
T841 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.55536194 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 272658529 ps
T842 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2160374511 Feb 25 01:17:23 PM PST 24 Feb 25 01:17:25 PM PST 24 143859623 ps
T843 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3251080472 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 40001076 ps
T844 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1006966663 Feb 25 01:17:24 PM PST 24 Feb 25 01:17:26 PM PST 24 74019337 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.324248334 Feb 25 01:17:03 PM PST 24 Feb 25 01:17:04 PM PST 24 862631892 ps
T846 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4057000161 Feb 25 01:17:05 PM PST 24 Feb 25 01:17:06 PM PST 24 33744730 ps
T847 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237662177 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 93245431 ps
T848 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931679529 Feb 25 01:17:38 PM PST 24 Feb 25 01:17:39 PM PST 24 69514932 ps
T849 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4174570626 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 45866236 ps
T850 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1018525923 Feb 25 01:17:36 PM PST 24 Feb 25 01:17:38 PM PST 24 83615856 ps
T851 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.644515780 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 968169428 ps
T852 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1096789314 Feb 25 01:17:28 PM PST 24 Feb 25 01:17:30 PM PST 24 38046434 ps
T853 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1544702173 Feb 25 01:17:05 PM PST 24 Feb 25 01:17:06 PM PST 24 65794667 ps
T854 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1918717419 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 195411032 ps
T855 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2684454685 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 137610773 ps
T856 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2840841950 Feb 25 01:17:33 PM PST 24 Feb 25 01:17:35 PM PST 24 144130646 ps
T857 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998472329 Feb 25 01:17:11 PM PST 24 Feb 25 01:17:12 PM PST 24 43164902 ps
T858 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1790495440 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 87911940 ps
T859 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.887689235 Feb 25 01:17:16 PM PST 24 Feb 25 01:17:17 PM PST 24 116177579 ps
T860 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1117823080 Feb 25 01:17:25 PM PST 24 Feb 25 01:17:26 PM PST 24 95141181 ps
T861 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1934605103 Feb 25 01:17:33 PM PST 24 Feb 25 01:17:34 PM PST 24 1096868465 ps
T862 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3258281508 Feb 25 01:17:17 PM PST 24 Feb 25 01:17:18 PM PST 24 115980503 ps
T863 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3083028090 Feb 25 01:17:33 PM PST 24 Feb 25 01:17:34 PM PST 24 40100925 ps
T864 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348358733 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:20 PM PST 24 43856241 ps
T865 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1683009183 Feb 25 01:17:25 PM PST 24 Feb 25 01:17:27 PM PST 24 165538150 ps
T866 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1803881131 Feb 25 01:17:37 PM PST 24 Feb 25 01:17:39 PM PST 24 278457325 ps
T867 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1075381621 Feb 25 01:17:08 PM PST 24 Feb 25 01:17:09 PM PST 24 35537819 ps
T868 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4190478969 Feb 25 01:17:17 PM PST 24 Feb 25 01:17:18 PM PST 24 129967096 ps
T869 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.94856172 Feb 25 01:17:36 PM PST 24 Feb 25 01:17:37 PM PST 24 31742218 ps
T870 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2706685665 Feb 25 01:17:03 PM PST 24 Feb 25 01:17:04 PM PST 24 310698794 ps
T871 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.972398025 Feb 25 01:17:16 PM PST 24 Feb 25 01:17:18 PM PST 24 330827925 ps
T872 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1133666477 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 37903934 ps
T873 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.359361806 Feb 25 01:17:26 PM PST 24 Feb 25 01:17:28 PM PST 24 142312112 ps
T874 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4278689492 Feb 25 01:17:33 PM PST 24 Feb 25 01:17:35 PM PST 24 51913770 ps
T875 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854620633 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:20 PM PST 24 95540244 ps
T876 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.781166776 Feb 25 01:17:03 PM PST 24 Feb 25 01:17:05 PM PST 24 63747199 ps
T877 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812166937 Feb 25 01:17:23 PM PST 24 Feb 25 01:17:25 PM PST 24 49489519 ps
T878 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566285359 Feb 25 01:17:24 PM PST 24 Feb 25 01:17:26 PM PST 24 89198562 ps
T879 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3219845696 Feb 25 01:17:16 PM PST 24 Feb 25 01:17:17 PM PST 24 720643896 ps
T880 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3030499801 Feb 25 01:17:17 PM PST 24 Feb 25 01:17:18 PM PST 24 647659045 ps
T881 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3132817504 Feb 25 01:17:35 PM PST 24 Feb 25 01:17:36 PM PST 24 44301098 ps
T882 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4247434061 Feb 25 01:17:36 PM PST 24 Feb 25 01:17:38 PM PST 24 208909614 ps
T883 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3264135479 Feb 25 01:17:03 PM PST 24 Feb 25 01:17:04 PM PST 24 140093380 ps
T884 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4013873198 Feb 25 01:17:32 PM PST 24 Feb 25 01:17:34 PM PST 24 286264419 ps
T885 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.792897209 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 41482050 ps
T886 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2924437528 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 43798146 ps
T887 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1661315031 Feb 25 01:17:32 PM PST 24 Feb 25 01:17:34 PM PST 24 61551130 ps
T888 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2242972490 Feb 25 01:17:03 PM PST 24 Feb 25 01:17:04 PM PST 24 56655520 ps
T889 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.448840150 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 44035293 ps
T890 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3752845667 Feb 25 01:17:32 PM PST 24 Feb 25 01:17:33 PM PST 24 49456180 ps
T891 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2351930009 Feb 25 01:17:23 PM PST 24 Feb 25 01:17:25 PM PST 24 287515170 ps
T892 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206628442 Feb 25 01:17:13 PM PST 24 Feb 25 01:17:14 PM PST 24 702786912 ps
T893 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3579208144 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:24 PM PST 24 417451442 ps
T894 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2021027230 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 59265837 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197360352 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 84834866 ps
T896 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581483998 Feb 25 01:17:25 PM PST 24 Feb 25 01:17:26 PM PST 24 45902803 ps
T897 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1176215791 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 94058706 ps
T898 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2597955335 Feb 25 01:17:34 PM PST 24 Feb 25 01:17:35 PM PST 24 43912663 ps
T899 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3321726213 Feb 25 01:17:46 PM PST 24 Feb 25 01:17:47 PM PST 24 54369429 ps
T900 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2622719461 Feb 25 01:17:17 PM PST 24 Feb 25 01:17:19 PM PST 24 40498286 ps
T901 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2246312975 Feb 25 01:17:35 PM PST 24 Feb 25 01:17:37 PM PST 24 33759298 ps
T902 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2343664307 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 42186334 ps
T903 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2660148119 Feb 25 01:17:36 PM PST 24 Feb 25 01:17:37 PM PST 24 41471990 ps
T904 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.397443663 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 81241903 ps
T905 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705642348 Feb 25 01:17:33 PM PST 24 Feb 25 01:17:35 PM PST 24 88497905 ps
T906 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1878265137 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:20 PM PST 24 34329243 ps
T907 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.21765788 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:20 PM PST 24 56610668 ps
T908 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3076181731 Feb 25 01:17:10 PM PST 24 Feb 25 01:17:12 PM PST 24 129238343 ps
T909 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.256152434 Feb 25 01:17:35 PM PST 24 Feb 25 01:17:36 PM PST 24 125344595 ps
T910 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1868316105 Feb 25 01:17:21 PM PST 24 Feb 25 01:17:23 PM PST 24 333679552 ps
T911 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2193002070 Feb 25 01:17:36 PM PST 24 Feb 25 01:17:37 PM PST 24 55857657 ps
T912 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1002859535 Feb 25 01:17:04 PM PST 24 Feb 25 01:17:05 PM PST 24 58421032 ps
T913 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3815155227 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 237939035 ps
T914 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1018242460 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:28 PM PST 24 747569803 ps
T915 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2122616849 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:21 PM PST 24 44248185 ps
T916 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.451974661 Feb 25 01:17:44 PM PST 24 Feb 25 01:17:45 PM PST 24 107281913 ps
T917 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4074422819 Feb 25 01:17:25 PM PST 24 Feb 25 01:17:27 PM PST 24 50568154 ps
T918 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2073273655 Feb 25 01:17:10 PM PST 24 Feb 25 01:17:11 PM PST 24 71359931 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.23398959 Feb 25 01:17:11 PM PST 24 Feb 25 01:17:12 PM PST 24 67130465 ps
T920 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1684181989 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:24 PM PST 24 52975442 ps
T921 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1200821460 Feb 25 01:17:06 PM PST 24 Feb 25 01:17:07 PM PST 24 157855577 ps
T922 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2143145656 Feb 25 01:17:04 PM PST 24 Feb 25 01:17:06 PM PST 24 48050954 ps
T923 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2607181480 Feb 25 01:17:23 PM PST 24 Feb 25 01:17:25 PM PST 24 28617774 ps
T924 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4018545243 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 199818918 ps
T925 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206155969 Feb 25 01:17:21 PM PST 24 Feb 25 01:17:22 PM PST 24 312111002 ps
T926 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077862822 Feb 25 01:17:02 PM PST 24 Feb 25 01:17:03 PM PST 24 36292643 ps
T927 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3628575908 Feb 25 01:17:22 PM PST 24 Feb 25 01:17:23 PM PST 24 158025914 ps
T928 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785403028 Feb 25 01:17:27 PM PST 24 Feb 25 01:17:29 PM PST 24 960722390 ps
T929 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3158576944 Feb 25 01:17:38 PM PST 24 Feb 25 01:17:39 PM PST 24 28209783 ps
T930 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3426201872 Feb 25 01:17:25 PM PST 24 Feb 25 01:17:27 PM PST 24 324032561 ps
T931 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781420243 Feb 25 01:17:04 PM PST 24 Feb 25 01:17:05 PM PST 24 36333367 ps
T932 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880165417 Feb 25 01:17:04 PM PST 24 Feb 25 01:17:06 PM PST 24 388946667 ps
T933 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2144200615 Feb 25 01:17:18 PM PST 24 Feb 25 01:17:20 PM PST 24 296841008 ps
T934 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207039102 Feb 25 01:17:09 PM PST 24 Feb 25 01:17:10 PM PST 24 126966742 ps
T935 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2096848954 Feb 25 01:17:19 PM PST 24 Feb 25 01:17:20 PM PST 24 90932846 ps

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3435728036
Short name T25
Test name
Test status
Simulation time 71179283 ps
CPU time 3.21 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:24 PM PST 24
Peak memory 198040 kb
Host smart-e22d569e-9b75-4181-aee6-ef29b006d418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435728036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3435728036
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1859598526
Short name T51
Test name
Test status
Simulation time 34452346 ps
CPU time 1.54 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 198056 kb
Host smart-b3a5e757-74db-4d85-9a7c-e4c477c330a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859598526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1859598526
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1269916925
Short name T30
Test name
Test status
Simulation time 144389796828 ps
CPU time 674.27 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:55:45 PM PST 24
Peak memory 198332 kb
Host smart-fb41a49e-6a2c-405e-87b1-659b2ac6d4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1269916925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1269916925
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1668414044
Short name T39
Test name
Test status
Simulation time 79170014 ps
CPU time 0.89 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 213776 kb
Host smart-d0c5c645-a9ce-4163-a5d7-e884b8cee1c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668414044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1668414044
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2036260493
Short name T75
Test name
Test status
Simulation time 70648767 ps
CPU time 0.68 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 194520 kb
Host smart-d2de4f9f-4e4e-46e2-97f4-e839bc0f4baa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036260493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2036260493
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3552166509
Short name T5
Test name
Test status
Simulation time 213221494749 ps
CPU time 117.77 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:45:36 PM PST 24
Peak memory 198212 kb
Host smart-ce53cbae-bf16-4269-ae5a-89be787c612a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552166509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3552166509
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1367383107
Short name T34
Test name
Test status
Simulation time 129239453 ps
CPU time 1.42 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 198220 kb
Host smart-03cbf6a0-0b84-44ee-af56-5aa010e5ac53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367383107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1367383107
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3265843026
Short name T214
Test name
Test status
Simulation time 70183018 ps
CPU time 0.57 seconds
Started Feb 25 01:43:33 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 193916 kb
Host smart-2c3acfbe-0e41-41be-b800-8b9410db843e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265843026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3265843026
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3232326749
Short name T81
Test name
Test status
Simulation time 13305079 ps
CPU time 0.62 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 195208 kb
Host smart-76812235-f5f3-4455-ae56-fa90f63dbd5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232326749 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3232326749
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.663983150
Short name T109
Test name
Test status
Simulation time 141165542 ps
CPU time 1.12 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 198176 kb
Host smart-7653919b-0979-4a05-9330-28ee568538d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663983150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.663983150
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.905763218
Short name T818
Test name
Test status
Simulation time 130544098 ps
CPU time 1.15 seconds
Started Feb 25 12:39:46 PM PST 24
Finished Feb 25 12:39:47 PM PST 24
Peak memory 198256 kb
Host smart-b755a125-80dc-48e5-893c-4f756dabc038
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905763218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.905763218
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.388867592
Short name T785
Test name
Test status
Simulation time 240698294 ps
CPU time 2.29 seconds
Started Feb 25 12:39:38 PM PST 24
Finished Feb 25 12:39:40 PM PST 24
Peak memory 198128 kb
Host smart-2e3540b3-aeb5-4fd2-8420-af0513689a29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388867592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.388867592
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2368765705
Short name T87
Test name
Test status
Simulation time 12631101 ps
CPU time 0.61 seconds
Started Feb 25 12:39:27 PM PST 24
Finished Feb 25 12:39:28 PM PST 24
Peak memory 194752 kb
Host smart-ba86c29b-4266-41ed-8b34-6dc906fd6493
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368765705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2368765705
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2988759843
Short name T718
Test name
Test status
Simulation time 164954317 ps
CPU time 0.97 seconds
Started Feb 25 12:39:41 PM PST 24
Finished Feb 25 12:39:42 PM PST 24
Peak memory 198136 kb
Host smart-3602e19a-b677-4273-a769-1fdbacade5d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988759843 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2988759843
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3390694930
Short name T834
Test name
Test status
Simulation time 26710979 ps
CPU time 0.61 seconds
Started Feb 25 12:39:39 PM PST 24
Finished Feb 25 12:39:40 PM PST 24
Peak memory 195624 kb
Host smart-323d9fed-094d-4b47-968a-d353ccb87c82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390694930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3390694930
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2035053983
Short name T737
Test name
Test status
Simulation time 14427950 ps
CPU time 0.61 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 193864 kb
Host smart-071c5148-b4ea-4a64-9db8-1571cf7a9a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035053983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2035053983
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2590960089
Short name T788
Test name
Test status
Simulation time 144897594 ps
CPU time 2 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 198108 kb
Host smart-8816b53c-c451-47ed-9e11-832017fe2976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590960089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2590960089
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4062206030
Short name T801
Test name
Test status
Simulation time 87230951 ps
CPU time 0.86 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 197400 kb
Host smart-79377871-90e9-4717-a20a-75a9977b29e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062206030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4062206030
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1120589075
Short name T779
Test name
Test status
Simulation time 18629279 ps
CPU time 0.65 seconds
Started Feb 25 12:39:41 PM PST 24
Finished Feb 25 12:39:42 PM PST 24
Peak memory 194296 kb
Host smart-ebcbe65c-a054-429b-8d2c-9660f10392bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120589075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1120589075
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1324741610
Short name T762
Test name
Test status
Simulation time 92372782 ps
CPU time 1.55 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:46 PM PST 24
Peak memory 198216 kb
Host smart-448d1942-9bc4-4350-946e-aa0875833289
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324741610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1324741610
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4114956295
Short name T730
Test name
Test status
Simulation time 25547986 ps
CPU time 0.65 seconds
Started Feb 25 12:39:47 PM PST 24
Finished Feb 25 12:39:49 PM PST 24
Peak memory 195544 kb
Host smart-76eabc2c-3a7d-4bf5-b9ce-2c7bb32961ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114956295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4114956295
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2459479436
Short name T797
Test name
Test status
Simulation time 39652088 ps
CPU time 0.63 seconds
Started Feb 25 12:39:50 PM PST 24
Finished Feb 25 12:39:51 PM PST 24
Peak memory 196900 kb
Host smart-d34f5013-e0ef-484a-952f-98737c21689b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459479436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2459479436
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2303462382
Short name T727
Test name
Test status
Simulation time 36778205 ps
CPU time 0.63 seconds
Started Feb 25 12:39:27 PM PST 24
Finished Feb 25 12:39:28 PM PST 24
Peak memory 195080 kb
Host smart-d4f08e3b-1660-4924-a48e-408561210250
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303462382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2303462382
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3839732564
Short name T821
Test name
Test status
Simulation time 31653616 ps
CPU time 0.62 seconds
Started Feb 25 12:39:41 PM PST 24
Finished Feb 25 12:39:42 PM PST 24
Peak memory 193892 kb
Host smart-87a73f43-29c2-4462-9b52-b067da92927b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839732564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3839732564
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3356661098
Short name T772
Test name
Test status
Simulation time 64858869 ps
CPU time 0.78 seconds
Started Feb 25 12:39:45 PM PST 24
Finished Feb 25 12:39:46 PM PST 24
Peak memory 197028 kb
Host smart-04c8688a-0818-4e27-8d85-125cfab221d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356661098 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3356661098
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1219785765
Short name T767
Test name
Test status
Simulation time 452480668 ps
CPU time 2.52 seconds
Started Feb 25 12:39:49 PM PST 24
Finished Feb 25 12:39:52 PM PST 24
Peak memory 198128 kb
Host smart-c8b8041c-3b7d-4632-a44f-8df386e3b5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219785765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1219785765
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1529215760
Short name T756
Test name
Test status
Simulation time 32729138 ps
CPU time 1.65 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198224 kb
Host smart-13020e5f-4dc5-4ad7-8b1f-b4defc400b51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529215760 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1529215760
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1777993190
Short name T829
Test name
Test status
Simulation time 14364723 ps
CPU time 0.61 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:14 PM PST 24
Peak memory 194540 kb
Host smart-2c66a59d-c6c3-4b2f-b002-57bd04fcf592
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777993190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1777993190
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3483814592
Short name T815
Test name
Test status
Simulation time 62016256 ps
CPU time 0.62 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 194496 kb
Host smart-d03443d0-710d-4968-a1d2-5f88536db263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483814592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3483814592
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3557616112
Short name T806
Test name
Test status
Simulation time 41754077 ps
CPU time 0.82 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 196400 kb
Host smart-f8459891-101a-406d-997e-9118752d3101
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557616112 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3557616112
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3626045227
Short name T739
Test name
Test status
Simulation time 261063474 ps
CPU time 2.65 seconds
Started Feb 25 12:39:59 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 198220 kb
Host smart-8bc5f324-435c-458e-9fd1-f77ae0ba808d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626045227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3626045227
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3446737385
Short name T108
Test name
Test status
Simulation time 413492696 ps
CPU time 1.38 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198272 kb
Host smart-546bb8b1-00af-4689-bfc4-fd3fe755b41c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446737385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3446737385
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4125023769
Short name T747
Test name
Test status
Simulation time 100031415 ps
CPU time 1.38 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198152 kb
Host smart-c3f7ac35-689c-41cf-b7ee-3cba1b825b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125023769 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4125023769
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3326973881
Short name T82
Test name
Test status
Simulation time 11853878 ps
CPU time 0.61 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 194788 kb
Host smart-a1ace906-51f6-4720-a295-8630188a665d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326973881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3326973881
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2873792903
Short name T805
Test name
Test status
Simulation time 40024600 ps
CPU time 0.58 seconds
Started Feb 25 12:40:00 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 193760 kb
Host smart-619cb00b-3477-4b6f-a98a-0266c9b56f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873792903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2873792903
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1199072456
Short name T79
Test name
Test status
Simulation time 56737969 ps
CPU time 0.71 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 194892 kb
Host smart-2049b422-0344-4318-ba0d-996cbbd5bde5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199072456 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1199072456
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.881344586
Short name T724
Test name
Test status
Simulation time 85305223 ps
CPU time 1.65 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:46 PM PST 24
Peak memory 198152 kb
Host smart-533ad85a-d71f-49f1-9730-c94f9e2c72fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881344586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.881344586
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3706645574
Short name T812
Test name
Test status
Simulation time 33226539 ps
CPU time 1.45 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 198308 kb
Host smart-2fb11202-75fa-42ce-a80b-e8de20bc5bc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706645574 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3706645574
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1556089117
Short name T803
Test name
Test status
Simulation time 23957177 ps
CPU time 0.56 seconds
Started Feb 25 12:39:50 PM PST 24
Finished Feb 25 12:39:50 PM PST 24
Peak memory 194652 kb
Host smart-a88288a6-3c05-4ff0-8d2c-1fed96121f47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556089117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1556089117
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2827559109
Short name T746
Test name
Test status
Simulation time 75873263 ps
CPU time 0.55 seconds
Started Feb 25 12:39:55 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 193728 kb
Host smart-63829baa-7854-4b4e-a317-93d7ee965680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827559109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2827559109
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.513181808
Short name T76
Test name
Test status
Simulation time 48667003 ps
CPU time 0.86 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 196320 kb
Host smart-8d85fdde-9c10-4243-833c-bea681ea90b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513181808 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.513181808
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.779080862
Short name T824
Test name
Test status
Simulation time 157904494 ps
CPU time 1.6 seconds
Started Feb 25 12:39:49 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 198132 kb
Host smart-49920667-575a-41ab-8379-ae15852f4a07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779080862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.779080862
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4222536397
Short name T47
Test name
Test status
Simulation time 306085435 ps
CPU time 1.1 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 198132 kb
Host smart-81c4af22-23d3-4ec4-b9ce-5c18d35a398d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222536397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.4222536397
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1498101571
Short name T823
Test name
Test status
Simulation time 57514217 ps
CPU time 0.63 seconds
Started Feb 25 12:40:00 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 196436 kb
Host smart-a3d3a109-1d6a-4bb6-95f9-1f854913bf87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498101571 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1498101571
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.95923485
Short name T78
Test name
Test status
Simulation time 11762662 ps
CPU time 0.58 seconds
Started Feb 25 12:40:06 PM PST 24
Finished Feb 25 12:40:07 PM PST 24
Peak memory 194552 kb
Host smart-57ee138a-ab3e-4e4e-9cd0-6ee3d5756dc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95923485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_
csr_rw.95923485
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3799878964
Short name T766
Test name
Test status
Simulation time 11285932 ps
CPU time 0.58 seconds
Started Feb 25 12:39:50 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 194532 kb
Host smart-079c314e-b69c-4fa0-b23a-41b5c5274895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799878964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3799878964
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.412841318
Short name T831
Test name
Test status
Simulation time 33016592 ps
CPU time 0.77 seconds
Started Feb 25 12:40:07 PM PST 24
Finished Feb 25 12:40:08 PM PST 24
Peak memory 196408 kb
Host smart-cd0d16ac-4362-49b6-89bb-061546ec36b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412841318 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.412841318
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.35575216
Short name T748
Test name
Test status
Simulation time 37606305 ps
CPU time 1.43 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 198092 kb
Host smart-3157c1bc-2024-40c3-98ba-26a10ce52e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35575216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.35575216
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.704042822
Short name T807
Test name
Test status
Simulation time 220022438 ps
CPU time 1.25 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:54 PM PST 24
Peak memory 197976 kb
Host smart-cc89300d-8fa9-41d1-b82c-982f0f608542
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704042822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.704042822
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.629616160
Short name T811
Test name
Test status
Simulation time 206194413 ps
CPU time 0.69 seconds
Started Feb 25 12:40:07 PM PST 24
Finished Feb 25 12:40:08 PM PST 24
Peak memory 198012 kb
Host smart-057cc285-7411-446f-8f9e-4a71a361fd41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629616160 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.629616160
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.930711616
Short name T771
Test name
Test status
Simulation time 18330177 ps
CPU time 0.55 seconds
Started Feb 25 12:40:06 PM PST 24
Finished Feb 25 12:40:07 PM PST 24
Peak memory 195192 kb
Host smart-43a1ffdb-44ca-4ec7-afb4-1e03fce4624e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930711616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.930711616
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.39003059
Short name T763
Test name
Test status
Simulation time 22212376 ps
CPU time 0.6 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 194516 kb
Host smart-2bba8643-38a9-42b7-8713-40f9caad704f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.39003059
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1973589464
Short name T92
Test name
Test status
Simulation time 116089896 ps
CPU time 0.78 seconds
Started Feb 25 12:40:11 PM PST 24
Finished Feb 25 12:40:12 PM PST 24
Peak memory 197172 kb
Host smart-344b84fe-abf6-45b9-9736-dd6095969e99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973589464 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1973589464
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2930282951
Short name T740
Test name
Test status
Simulation time 324033580 ps
CPU time 2.67 seconds
Started Feb 25 12:40:01 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198132 kb
Host smart-895bcce5-9b78-4bbf-a090-30ea45b3fbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930282951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2930282951
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1906965984
Short name T110
Test name
Test status
Simulation time 167921121 ps
CPU time 1.2 seconds
Started Feb 25 12:40:19 PM PST 24
Finished Feb 25 12:40:22 PM PST 24
Peak memory 198148 kb
Host smart-157f1e18-a0b6-4254-ab3e-14ff5227135f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906965984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1906965984
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.482419547
Short name T778
Test name
Test status
Simulation time 113268024 ps
CPU time 0.93 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 198136 kb
Host smart-264ec84d-882b-43c3-b7f0-0daad9319221
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482419547 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.482419547
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1861627277
Short name T738
Test name
Test status
Simulation time 36685668 ps
CPU time 0.58 seconds
Started Feb 25 12:40:05 PM PST 24
Finished Feb 25 12:40:06 PM PST 24
Peak memory 194588 kb
Host smart-ed6b50e1-1423-447e-a861-49fe6fb64a54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861627277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1861627277
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1390424107
Short name T729
Test name
Test status
Simulation time 22211179 ps
CPU time 0.57 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 193816 kb
Host smart-03785b7a-4e0e-45e9-8a45-34a5aa78f32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390424107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1390424107
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2069410623
Short name T93
Test name
Test status
Simulation time 432573354 ps
CPU time 0.87 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 196376 kb
Host smart-d3255c7a-11c0-44d1-9665-f26008cd2c62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069410623 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2069410623
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2987780762
Short name T707
Test name
Test status
Simulation time 43400733 ps
CPU time 2.38 seconds
Started Feb 25 12:40:18 PM PST 24
Finished Feb 25 12:40:21 PM PST 24
Peak memory 198200 kb
Host smart-5a70bca2-c672-4b90-b321-7badc4368147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987780762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2987780762
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3130764965
Short name T46
Test name
Test status
Simulation time 125445696 ps
CPU time 1.2 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:20 PM PST 24
Peak memory 198280 kb
Host smart-c1e17031-880d-44bb-b006-f62fa9638f38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130764965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3130764965
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3507525630
Short name T780
Test name
Test status
Simulation time 18910414 ps
CPU time 0.95 seconds
Started Feb 25 12:39:59 PM PST 24
Finished Feb 25 12:40:01 PM PST 24
Peak memory 198044 kb
Host smart-d5da0d4b-1db5-4d66-a931-542eeaf03bc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507525630 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3507525630
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.938779190
Short name T750
Test name
Test status
Simulation time 68349986 ps
CPU time 0.59 seconds
Started Feb 25 12:40:30 PM PST 24
Finished Feb 25 12:40:31 PM PST 24
Peak memory 195420 kb
Host smart-61f3b699-224d-4739-a11f-27085cbfdc2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938779190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.938779190
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.4150151441
Short name T754
Test name
Test status
Simulation time 48891331 ps
CPU time 0.59 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 193872 kb
Host smart-61db1f12-6b62-49a1-91a3-08270724ca04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150151441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.4150151441
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1660738030
Short name T795
Test name
Test status
Simulation time 40874155 ps
CPU time 0.64 seconds
Started Feb 25 12:40:12 PM PST 24
Finished Feb 25 12:40:13 PM PST 24
Peak memory 194980 kb
Host smart-5c419c5f-5005-4eee-a756-9391fa5fca59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660738030 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1660738030
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1536275484
Short name T728
Test name
Test status
Simulation time 427229993 ps
CPU time 2.02 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:46 PM PST 24
Peak memory 198080 kb
Host smart-82e16a3d-f680-4733-be11-e33ba30e57ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536275484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1536275484
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1493227946
Short name T45
Test name
Test status
Simulation time 272050614 ps
CPU time 1.09 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 197808 kb
Host smart-0ca04676-a042-4ebf-a09c-efe9fc71a188
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493227946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1493227946
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3904193364
Short name T745
Test name
Test status
Simulation time 54166715 ps
CPU time 0.79 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 198044 kb
Host smart-562cf4e1-0f4a-4eac-a3c6-61a869364fe7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904193364 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3904193364
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2195319505
Short name T107
Test name
Test status
Simulation time 12327528 ps
CPU time 0.62 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 195360 kb
Host smart-69e06bcc-7286-4700-a5f8-db10a4ffe5cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195319505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2195319505
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1892109382
Short name T708
Test name
Test status
Simulation time 27428792 ps
CPU time 0.61 seconds
Started Feb 25 12:39:41 PM PST 24
Finished Feb 25 12:39:42 PM PST 24
Peak memory 193780 kb
Host smart-edf11057-8049-4fb0-ab01-23550dceaf58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892109382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1892109382
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2207666209
Short name T822
Test name
Test status
Simulation time 24356337 ps
CPU time 0.72 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 194840 kb
Host smart-184f5657-a33a-495e-bf86-cfbdaca70299
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207666209 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2207666209
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4033104237
Short name T827
Test name
Test status
Simulation time 151233640 ps
CPU time 2.35 seconds
Started Feb 25 12:40:15 PM PST 24
Finished Feb 25 12:40:17 PM PST 24
Peak memory 198100 kb
Host smart-7fe910d5-81e0-46e8-8978-52e7d1b1fb76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033104237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4033104237
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2071254827
Short name T753
Test name
Test status
Simulation time 76559149 ps
CPU time 1.07 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:14 PM PST 24
Peak memory 198056 kb
Host smart-90f5167d-3e3c-414d-ace5-4f9469626822
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071254827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2071254827
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1004399691
Short name T744
Test name
Test status
Simulation time 107574307 ps
CPU time 1.31 seconds
Started Feb 25 12:39:45 PM PST 24
Finished Feb 25 12:39:47 PM PST 24
Peak memory 198244 kb
Host smart-31c6a7d6-f0a1-4099-80d2-289ac8415bd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004399691 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1004399691
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3831505553
Short name T77
Test name
Test status
Simulation time 14265780 ps
CPU time 0.56 seconds
Started Feb 25 12:39:51 PM PST 24
Finished Feb 25 12:39:51 PM PST 24
Peak memory 194724 kb
Host smart-9c9eff0b-3e0c-4367-a35d-77ea1b75533d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831505553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3831505553
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1105144399
Short name T799
Test name
Test status
Simulation time 14337623 ps
CPU time 0.6 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 194456 kb
Host smart-baea8753-571b-40d4-9dd2-fc0b6a820590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105144399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1105144399
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2782947801
Short name T789
Test name
Test status
Simulation time 31193899 ps
CPU time 0.73 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 195136 kb
Host smart-f1725b41-5d7d-4054-b00b-17b8d9174770
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782947801 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2782947801
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.759019910
Short name T717
Test name
Test status
Simulation time 125590441 ps
CPU time 2.48 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:07 PM PST 24
Peak memory 198124 kb
Host smart-ec174087-0d24-448a-a122-6d6a3550c6f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759019910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.759019910
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1156509883
Short name T760
Test name
Test status
Simulation time 119976097 ps
CPU time 0.84 seconds
Started Feb 25 12:40:07 PM PST 24
Finished Feb 25 12:40:08 PM PST 24
Peak memory 197452 kb
Host smart-81411a30-fb0f-44de-9b5f-5620e4881766
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156509883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1156509883
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2976831237
Short name T723
Test name
Test status
Simulation time 38501497 ps
CPU time 0.97 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 198020 kb
Host smart-0e2be6fb-f7e4-4ee5-8fba-2449d4a3a23b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976831237 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2976831237
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3750824853
Short name T80
Test name
Test status
Simulation time 37943834 ps
CPU time 0.6 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 193704 kb
Host smart-57acffc8-1b85-4d2b-8643-8dfa6aa92855
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750824853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3750824853
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1035337501
Short name T761
Test name
Test status
Simulation time 30680641 ps
CPU time 0.58 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:03 PM PST 24
Peak memory 193924 kb
Host smart-cd9c1619-104c-4e04-a1cb-b27b424c7215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035337501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1035337501
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3632828883
Short name T89
Test name
Test status
Simulation time 33920585 ps
CPU time 0.61 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:58 PM PST 24
Peak memory 194344 kb
Host smart-67bd7217-d338-42d0-a384-0d4662230a1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632828883 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3632828883
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2398591294
Short name T741
Test name
Test status
Simulation time 33780653 ps
CPU time 1.74 seconds
Started Feb 25 12:39:49 PM PST 24
Finished Feb 25 12:39:51 PM PST 24
Peak memory 198220 kb
Host smart-b9640842-0e72-481b-a615-b1d37097900f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398591294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2398591294
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1867241663
Short name T830
Test name
Test status
Simulation time 80909437 ps
CPU time 1.11 seconds
Started Feb 25 12:40:10 PM PST 24
Finished Feb 25 12:40:11 PM PST 24
Peak memory 198284 kb
Host smart-680d12e0-ade8-4dcf-92e7-6837624096b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867241663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1867241663
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.200015087
Short name T813
Test name
Test status
Simulation time 37700697 ps
CPU time 0.64 seconds
Started Feb 25 12:39:45 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 195188 kb
Host smart-d63444d0-3b22-4e30-9c45-28bacba445a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200015087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.200015087
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4106277095
Short name T74
Test name
Test status
Simulation time 313725195 ps
CPU time 2.35 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:47 PM PST 24
Peak memory 198320 kb
Host smart-a013479d-1c71-4f5c-9f54-e590641e805f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106277095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4106277095
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.284316285
Short name T781
Test name
Test status
Simulation time 19200777 ps
CPU time 0.65 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 195064 kb
Host smart-314af519-3c9c-44d6-915d-ce0e8228a967
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284316285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.284316285
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.85958479
Short name T721
Test name
Test status
Simulation time 43943626 ps
CPU time 1 seconds
Started Feb 25 12:39:40 PM PST 24
Finished Feb 25 12:39:42 PM PST 24
Peak memory 198052 kb
Host smart-79490dc4-c083-4376-b1b7-a24347a84303
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85958479 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.85958479
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.920614172
Short name T86
Test name
Test status
Simulation time 14243750 ps
CPU time 0.58 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 193672 kb
Host smart-ae8e4586-284a-4b4b-8ea7-7e6df8f47472
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920614172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.920614172
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2970248509
Short name T733
Test name
Test status
Simulation time 19012873 ps
CPU time 0.59 seconds
Started Feb 25 12:39:37 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 193900 kb
Host smart-59cc01c4-57c2-43b6-8c35-64a5cca8ab7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970248509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2970248509
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.452789702
Short name T793
Test name
Test status
Simulation time 19512552 ps
CPU time 0.9 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 197248 kb
Host smart-4c7ed4a9-1e33-46eb-8573-1f1bcdf595a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452789702 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.452789702
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.295551963
Short name T755
Test name
Test status
Simulation time 53829347 ps
CPU time 1.3 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 198208 kb
Host smart-72759573-ce98-48ec-bf6c-2551f303ca96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295551963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.295551963
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2337630483
Short name T36
Test name
Test status
Simulation time 43007409 ps
CPU time 0.87 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 197004 kb
Host smart-e42c2ef2-96f7-4808-9891-7718014b0440
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337630483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2337630483
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.797035206
Short name T769
Test name
Test status
Simulation time 18019636 ps
CPU time 0.63 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:14 PM PST 24
Peak memory 193928 kb
Host smart-1daa6874-9aaf-4344-877a-2803fb016841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797035206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.797035206
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.591885504
Short name T736
Test name
Test status
Simulation time 14098770 ps
CPU time 0.59 seconds
Started Feb 25 12:40:06 PM PST 24
Finished Feb 25 12:40:07 PM PST 24
Peak memory 193916 kb
Host smart-a5303a20-88eb-4868-8ac0-f42b7d882947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591885504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.591885504
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2385017209
Short name T826
Test name
Test status
Simulation time 19873653 ps
CPU time 0.59 seconds
Started Feb 25 12:40:10 PM PST 24
Finished Feb 25 12:40:11 PM PST 24
Peak memory 194528 kb
Host smart-1928808d-bf78-400e-b224-7a57ad30ee40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385017209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2385017209
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.935990806
Short name T774
Test name
Test status
Simulation time 27523379 ps
CPU time 0.58 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 193752 kb
Host smart-12909099-e3c4-4ef0-ba8f-5b85869085b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935990806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.935990806
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.228873958
Short name T710
Test name
Test status
Simulation time 14597056 ps
CPU time 0.63 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 194556 kb
Host smart-c00ab1c6-9ca0-453b-a36c-efbfb015578c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228873958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.228873958
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4076879903
Short name T712
Test name
Test status
Simulation time 20592555 ps
CPU time 0.57 seconds
Started Feb 25 12:39:49 PM PST 24
Finished Feb 25 12:39:50 PM PST 24
Peak memory 194480 kb
Host smart-7456be15-cc39-49d3-bc8d-f3757e75fd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076879903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4076879903
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.447748600
Short name T783
Test name
Test status
Simulation time 11997046 ps
CPU time 0.56 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 194492 kb
Host smart-746f9f44-489f-41b9-8d83-0b357407bfe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447748600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.447748600
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4248268397
Short name T768
Test name
Test status
Simulation time 34120226 ps
CPU time 0.6 seconds
Started Feb 25 12:40:00 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 193832 kb
Host smart-5b26572b-6262-4a76-a2be-5cf3b722e7f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248268397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4248268397
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3027697583
Short name T734
Test name
Test status
Simulation time 40369175 ps
CPU time 0.58 seconds
Started Feb 25 12:40:06 PM PST 24
Finished Feb 25 12:40:07 PM PST 24
Peak memory 193808 kb
Host smart-9b362c6d-38e0-4faa-9961-30bddbc10cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027697583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3027697583
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3558169570
Short name T759
Test name
Test status
Simulation time 52257360 ps
CPU time 0.58 seconds
Started Feb 25 12:40:23 PM PST 24
Finished Feb 25 12:40:25 PM PST 24
Peak memory 193804 kb
Host smart-518f4057-c892-4bd9-9aec-c38e75a59fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558169570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3558169570
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3225682587
Short name T84
Test name
Test status
Simulation time 30254246 ps
CPU time 0.79 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 196068 kb
Host smart-50f3b8bf-a32e-4f68-9903-d8b6b317be71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225682587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3225682587
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1655696281
Short name T775
Test name
Test status
Simulation time 34624062 ps
CPU time 1.42 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 197328 kb
Host smart-3ab0ed79-6b88-4f1d-9e08-c7895dd61572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655696281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1655696281
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1189751914
Short name T83
Test name
Test status
Simulation time 203775472 ps
CPU time 0.6 seconds
Started Feb 25 12:39:53 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 195388 kb
Host smart-cd5a7768-90bd-4beb-859c-9c026aee48be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189751914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1189751914
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1720327111
Short name T800
Test name
Test status
Simulation time 39871626 ps
CPU time 0.78 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 198048 kb
Host smart-98d10755-53c4-43dc-8b1b-260738edab8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720327111 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1720327111
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4081508943
Short name T88
Test name
Test status
Simulation time 13930177 ps
CPU time 0.61 seconds
Started Feb 25 12:39:46 PM PST 24
Finished Feb 25 12:39:47 PM PST 24
Peak memory 193400 kb
Host smart-c0945031-6717-47bd-939b-11667fbbcbc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081508943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4081508943
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3638756982
Short name T816
Test name
Test status
Simulation time 18963551 ps
CPU time 0.64 seconds
Started Feb 25 12:39:44 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 194116 kb
Host smart-a2aaa260-d248-4262-b3f4-8d5fdbc3f88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638756982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3638756982
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1661671495
Short name T792
Test name
Test status
Simulation time 62266696 ps
CPU time 0.81 seconds
Started Feb 25 12:39:48 PM PST 24
Finished Feb 25 12:39:49 PM PST 24
Peak memory 196356 kb
Host smart-d13032a3-0a64-46a7-a0e1-4fed6d374686
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661671495 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1661671495
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3279654733
Short name T764
Test name
Test status
Simulation time 175256164 ps
CPU time 1.43 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198228 kb
Host smart-bb74b730-27a9-4d94-845d-4c4206e0d618
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279654733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3279654733
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.939467123
Short name T38
Test name
Test status
Simulation time 92313282 ps
CPU time 0.87 seconds
Started Feb 25 12:39:59 PM PST 24
Finished Feb 25 12:40:00 PM PST 24
Peak memory 197456 kb
Host smart-a8e14f90-d6e2-4fb9-809f-1b27c62e438e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939467123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.939467123
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2356272466
Short name T790
Test name
Test status
Simulation time 65370439 ps
CPU time 0.56 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 194552 kb
Host smart-3b9d14ef-c787-4674-b0ae-b96fc33a71a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356272466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2356272466
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1777849798
Short name T776
Test name
Test status
Simulation time 15834686 ps
CPU time 0.6 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 193860 kb
Host smart-2187f241-cdb2-435c-8620-dd9a1515e791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777849798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1777849798
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.371199936
Short name T825
Test name
Test status
Simulation time 35910471 ps
CPU time 0.58 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 193956 kb
Host smart-ea67b610-5041-4c73-be34-e255eeab4035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371199936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.371199936
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3462084459
Short name T719
Test name
Test status
Simulation time 18409252 ps
CPU time 0.64 seconds
Started Feb 25 12:40:09 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 193988 kb
Host smart-0f1b6d02-a75a-416e-823b-67b808015b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462084459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3462084459
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2903568975
Short name T819
Test name
Test status
Simulation time 24221480 ps
CPU time 0.57 seconds
Started Feb 25 12:39:53 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 193784 kb
Host smart-c046566a-9ed3-47e2-83f1-845222dff60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903568975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2903568975
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2416886542
Short name T726
Test name
Test status
Simulation time 12226096 ps
CPU time 0.61 seconds
Started Feb 25 12:40:00 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 193888 kb
Host smart-cfd1420d-a5fd-422a-aa58-3fbb8deb9785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416886542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2416886542
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.265289501
Short name T835
Test name
Test status
Simulation time 72148321 ps
CPU time 0.57 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 193736 kb
Host smart-aa7a9f1c-6c18-4b1a-b9f7-6be471491f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265289501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.265289501
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2175467060
Short name T809
Test name
Test status
Simulation time 44470448 ps
CPU time 0.57 seconds
Started Feb 25 12:40:16 PM PST 24
Finished Feb 25 12:40:16 PM PST 24
Peak memory 193788 kb
Host smart-92777043-afbb-4fce-9e70-65573ae28e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175467060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2175467060
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3503386820
Short name T804
Test name
Test status
Simulation time 47248517 ps
CPU time 0.56 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 194508 kb
Host smart-0cc13320-120a-47e8-a2a2-4ad42340b4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503386820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3503386820
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1631466546
Short name T722
Test name
Test status
Simulation time 22823431 ps
CPU time 0.61 seconds
Started Feb 25 12:39:50 PM PST 24
Finished Feb 25 12:39:51 PM PST 24
Peak memory 194552 kb
Host smart-eae2caea-43ef-49c4-8450-92aa9d3dc6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631466546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1631466546
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2696212689
Short name T85
Test name
Test status
Simulation time 37468069 ps
CPU time 0.72 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 196008 kb
Host smart-a64ad2c5-e1fc-4f52-961f-092b56944a96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696212689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2696212689
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1685553631
Short name T820
Test name
Test status
Simulation time 177628210 ps
CPU time 2.46 seconds
Started Feb 25 12:40:01 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198108 kb
Host smart-2244ef58-a35a-4744-aebf-99a39b46dc2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685553631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1685553631
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3747750249
Short name T73
Test name
Test status
Simulation time 16607396 ps
CPU time 0.7 seconds
Started Feb 25 12:39:59 PM PST 24
Finished Feb 25 12:40:00 PM PST 24
Peak memory 195504 kb
Host smart-623476ba-d693-4c3e-b7a9-c6e9c2984366
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747750249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3747750249
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.402749655
Short name T758
Test name
Test status
Simulation time 25255584 ps
CPU time 0.82 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 198136 kb
Host smart-1ce5c444-e78d-4945-93c6-2d98394ce44f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402749655 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.402749655
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4079836733
Short name T714
Test name
Test status
Simulation time 11510809 ps
CPU time 0.59 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 195220 kb
Host smart-246be88f-31a8-4244-92be-de793b590d0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079836733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4079836733
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3085063151
Short name T832
Test name
Test status
Simulation time 49704572 ps
CPU time 0.64 seconds
Started Feb 25 12:39:53 PM PST 24
Finished Feb 25 12:39:54 PM PST 24
Peak memory 193800 kb
Host smart-cc9b532d-4e21-4522-965e-4d31adcc6883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085063151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3085063151
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3596724981
Short name T784
Test name
Test status
Simulation time 63283959 ps
CPU time 0.84 seconds
Started Feb 25 12:39:54 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 196620 kb
Host smart-c60e1394-78fb-4c22-a7eb-888b678e0c59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596724981 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3596724981
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2487335918
Short name T713
Test name
Test status
Simulation time 93509483 ps
CPU time 1.75 seconds
Started Feb 25 12:40:01 PM PST 24
Finished Feb 25 12:40:03 PM PST 24
Peak memory 198208 kb
Host smart-da905a3c-065e-4158-b7b6-ea9e491f767b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487335918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2487335918
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4061259596
Short name T35
Test name
Test status
Simulation time 56178489 ps
CPU time 0.9 seconds
Started Feb 25 12:40:30 PM PST 24
Finished Feb 25 12:40:31 PM PST 24
Peak memory 197964 kb
Host smart-2d954aef-a62a-4b9a-a26a-639b2dfd1656
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061259596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.4061259596
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.676485553
Short name T711
Test name
Test status
Simulation time 55504012 ps
CPU time 0.55 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 193884 kb
Host smart-80d0db91-6104-4c64-961b-8efadeaf045d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676485553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.676485553
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2565901484
Short name T833
Test name
Test status
Simulation time 50553770 ps
CPU time 0.58 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 193904 kb
Host smart-52d50e7e-b16b-4da9-81b0-aaf5a03c3cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565901484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2565901484
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4256834245
Short name T828
Test name
Test status
Simulation time 12346909 ps
CPU time 0.57 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 193768 kb
Host smart-fb29cf03-35e1-4681-bf0c-95f517b41163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256834245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4256834245
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1238968129
Short name T757
Test name
Test status
Simulation time 12898726 ps
CPU time 0.61 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 193832 kb
Host smart-7f7019e8-48a7-43e0-8989-44770552a97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238968129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1238968129
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4227270278
Short name T773
Test name
Test status
Simulation time 28677825 ps
CPU time 0.59 seconds
Started Feb 25 12:40:12 PM PST 24
Finished Feb 25 12:40:13 PM PST 24
Peak memory 193940 kb
Host smart-39bd7248-9670-49e2-9531-13ab717d3dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227270278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4227270278
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1373544079
Short name T817
Test name
Test status
Simulation time 13487410 ps
CPU time 0.56 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 193784 kb
Host smart-90bdc708-0527-4624-a1e9-8abaf87fb9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373544079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1373544079
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1330785053
Short name T751
Test name
Test status
Simulation time 110575165 ps
CPU time 0.56 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 194428 kb
Host smart-4085c283-1916-435e-afb2-d5dc3cd0c0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330785053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1330785053
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1818957049
Short name T709
Test name
Test status
Simulation time 20641547 ps
CPU time 0.59 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:13 PM PST 24
Peak memory 193868 kb
Host smart-e557ee6f-633d-4fe2-9aee-5160376ded9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818957049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1818957049
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1234194070
Short name T796
Test name
Test status
Simulation time 13068311 ps
CPU time 0.57 seconds
Started Feb 25 12:39:55 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 194540 kb
Host smart-188fba53-8575-46b4-baf0-657661aecb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234194070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1234194070
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3809621710
Short name T731
Test name
Test status
Simulation time 19448761 ps
CPU time 0.57 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 193908 kb
Host smart-70244877-0f98-4ee0-b7f0-870fb6a3e6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809621710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3809621710
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2459507003
Short name T743
Test name
Test status
Simulation time 20345220 ps
CPU time 0.7 seconds
Started Feb 25 12:39:47 PM PST 24
Finished Feb 25 12:39:49 PM PST 24
Peak memory 197660 kb
Host smart-1b7f3474-0613-497d-aa90-02b2ae54b6b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459507003 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2459507003
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4170538528
Short name T802
Test name
Test status
Simulation time 11674701 ps
CPU time 0.6 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 194708 kb
Host smart-d98e2756-e06a-4aee-878f-600c0e5f3345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170538528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4170538528
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3129762576
Short name T725
Test name
Test status
Simulation time 51525359 ps
CPU time 0.59 seconds
Started Feb 25 12:39:52 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 193888 kb
Host smart-7fe3a0d5-367a-40f4-81d7-bfa82b69769e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129762576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3129762576
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2888357583
Short name T90
Test name
Test status
Simulation time 106827010 ps
CPU time 0.84 seconds
Started Feb 25 12:39:43 PM PST 24
Finished Feb 25 12:39:44 PM PST 24
Peak memory 197144 kb
Host smart-af199dcb-d527-4c53-bbc1-cc3f0e001c25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888357583 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2888357583
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2227288096
Short name T786
Test name
Test status
Simulation time 316030115 ps
CPU time 2.69 seconds
Started Feb 25 12:40:13 PM PST 24
Finished Feb 25 12:40:16 PM PST 24
Peak memory 198148 kb
Host smart-0221ae53-e10b-4781-8dcb-69b78c32f2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227288096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2227288096
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.798179763
Short name T44
Test name
Test status
Simulation time 613795460 ps
CPU time 1.14 seconds
Started Feb 25 12:39:42 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 198200 kb
Host smart-43913281-4f2c-4add-ab73-90ce2adb9f4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798179763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.798179763
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3663820265
Short name T752
Test name
Test status
Simulation time 267916880 ps
CPU time 1.16 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:40:00 PM PST 24
Peak memory 198184 kb
Host smart-f53ac1cc-5ed8-41c8-a463-c40d6b678644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663820265 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3663820265
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1037315356
Short name T787
Test name
Test status
Simulation time 63714092 ps
CPU time 0.64 seconds
Started Feb 25 12:40:00 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 195596 kb
Host smart-9c85ee74-fb26-4874-9851-77df1fb6b7b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037315356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1037315356
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2999664962
Short name T715
Test name
Test status
Simulation time 28019251 ps
CPU time 0.59 seconds
Started Feb 25 12:40:07 PM PST 24
Finished Feb 25 12:40:08 PM PST 24
Peak memory 193924 kb
Host smart-927d70e1-deff-472a-aea1-bf4733723370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999664962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2999664962
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2081781753
Short name T95
Test name
Test status
Simulation time 99901840 ps
CPU time 0.61 seconds
Started Feb 25 12:40:18 PM PST 24
Finished Feb 25 12:40:24 PM PST 24
Peak memory 194380 kb
Host smart-b96b56a1-aea0-4979-a37a-2ab6ee797b68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081781753 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2081781753
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.36410416
Short name T732
Test name
Test status
Simulation time 59586816 ps
CPU time 1.6 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:40:00 PM PST 24
Peak memory 198180 kb
Host smart-eea84297-aba6-4f6a-8d14-339c91c58801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36410416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.36410416
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2255781316
Short name T808
Test name
Test status
Simulation time 68497532 ps
CPU time 0.86 seconds
Started Feb 25 12:40:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 197932 kb
Host smart-33d06c5a-77fa-47e4-9972-f7ef40541964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255781316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2255781316
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3159380247
Short name T777
Test name
Test status
Simulation time 67890187 ps
CPU time 0.94 seconds
Started Feb 25 12:39:57 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 198136 kb
Host smart-02fd7f21-2a4c-47ed-9365-4ebf1e6447e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159380247 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3159380247
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1414336316
Short name T720
Test name
Test status
Simulation time 13710839 ps
CPU time 0.63 seconds
Started Feb 25 12:40:01 PM PST 24
Finished Feb 25 12:40:02 PM PST 24
Peak memory 194640 kb
Host smart-ae4dd057-c4b9-4ae2-bba7-9494afd72da2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414336316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1414336316
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1714052207
Short name T794
Test name
Test status
Simulation time 15239619 ps
CPU time 0.54 seconds
Started Feb 25 12:39:48 PM PST 24
Finished Feb 25 12:39:49 PM PST 24
Peak memory 194456 kb
Host smart-f1c19e54-a36f-4642-816a-657a18ed5bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714052207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1714052207
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3352989519
Short name T94
Test name
Test status
Simulation time 46400225 ps
CPU time 0.64 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 194724 kb
Host smart-91cf9afa-6353-4b03-b886-c7bf7b2ef5f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352989519 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3352989519
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.262485393
Short name T742
Test name
Test status
Simulation time 976634264 ps
CPU time 2.41 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 198204 kb
Host smart-4f780f33-5b58-4f9b-8702-2bb9fdd44c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262485393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.262485393
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3740545698
Short name T814
Test name
Test status
Simulation time 275121391 ps
CPU time 1.17 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 198092 kb
Host smart-f7ccdb24-fc23-4fda-9432-8ed641227086
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740545698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3740545698
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2394363564
Short name T716
Test name
Test status
Simulation time 169379360 ps
CPU time 1.02 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 197988 kb
Host smart-5fba3ba2-3854-43e0-804b-42c1c45d28ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394363564 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2394363564
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.797898724
Short name T810
Test name
Test status
Simulation time 37262837 ps
CPU time 0.56 seconds
Started Feb 25 12:39:56 PM PST 24
Finished Feb 25 12:39:57 PM PST 24
Peak memory 193976 kb
Host smart-526678d8-d65a-4421-ad68-ea620a089111
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797898724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.797898724
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2761224549
Short name T791
Test name
Test status
Simulation time 25376910 ps
CPU time 0.57 seconds
Started Feb 25 12:40:08 PM PST 24
Finished Feb 25 12:40:09 PM PST 24
Peak memory 193776 kb
Host smart-3634b79f-3ace-4dfb-b3b5-e0dd8627f11a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761224549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2761224549
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.933901747
Short name T91
Test name
Test status
Simulation time 36853967 ps
CPU time 0.86 seconds
Started Feb 25 12:39:53 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 196648 kb
Host smart-8ea06615-a209-43d4-9a92-003181e8555b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933901747 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.933901747
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2725850386
Short name T798
Test name
Test status
Simulation time 452630157 ps
CPU time 2.51 seconds
Started Feb 25 12:39:55 PM PST 24
Finished Feb 25 12:39:58 PM PST 24
Peak memory 198208 kb
Host smart-14a4cf83-a096-4757-9817-d1b01d303e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725850386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2725850386
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.419993618
Short name T749
Test name
Test status
Simulation time 212027407 ps
CPU time 0.87 seconds
Started Feb 25 12:39:58 PM PST 24
Finished Feb 25 12:39:59 PM PST 24
Peak memory 197288 kb
Host smart-a05e2420-2368-4394-b511-40a91e99da98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419993618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.419993618
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3591773363
Short name T735
Test name
Test status
Simulation time 31077773 ps
CPU time 0.85 seconds
Started Feb 25 12:40:02 PM PST 24
Finished Feb 25 12:40:03 PM PST 24
Peak memory 197988 kb
Host smart-9acc1c57-fcba-40c7-99e5-eaeb413dde0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591773363 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3591773363
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1283371873
Short name T106
Test name
Test status
Simulation time 57136425 ps
CPU time 0.61 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 194868 kb
Host smart-a77a2eca-0248-4dde-8484-9898dab38283
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283371873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1283371873
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.823138446
Short name T765
Test name
Test status
Simulation time 49610573 ps
CPU time 0.59 seconds
Started Feb 25 12:39:53 PM PST 24
Finished Feb 25 12:39:53 PM PST 24
Peak memory 194640 kb
Host smart-0dc5d18d-b97b-4512-923e-bbac0031073f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823138446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.823138446
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3757962822
Short name T782
Test name
Test status
Simulation time 40932709 ps
CPU time 0.83 seconds
Started Feb 25 12:40:04 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 196316 kb
Host smart-1d920c2f-aefe-45b5-854d-c81e92897c65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757962822 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3757962822
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2734475072
Short name T770
Test name
Test status
Simulation time 234311738 ps
CPU time 3.15 seconds
Started Feb 25 12:39:48 PM PST 24
Finished Feb 25 12:39:51 PM PST 24
Peak memory 198156 kb
Host smart-c2326689-b875-4ead-9adb-55b4b7b4d262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734475072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2734475072
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3519437748
Short name T467
Test name
Test status
Simulation time 45873040 ps
CPU time 0.58 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:17 PM PST 24
Peak memory 194872 kb
Host smart-cb50f47f-4a2d-4ba7-8b0d-f9e274af8bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519437748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3519437748
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.484165338
Short name T197
Test name
Test status
Simulation time 19774612 ps
CPU time 0.68 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 194036 kb
Host smart-a5bff3b9-bc4c-40e2-b7ab-28d8c607a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484165338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.484165338
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.124655150
Short name T120
Test name
Test status
Simulation time 188960751 ps
CPU time 3.58 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 196048 kb
Host smart-91f1f56c-5124-4d10-b233-1bcb0be3340d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124655150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.124655150
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2696561046
Short name T330
Test name
Test status
Simulation time 70000186 ps
CPU time 0.69 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 194568 kb
Host smart-f7f23aa1-aa33-4ba4-a754-2658bd5452b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696561046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2696561046
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.299133259
Short name T541
Test name
Test status
Simulation time 20074799 ps
CPU time 0.74 seconds
Started Feb 25 01:43:04 PM PST 24
Finished Feb 25 01:43:05 PM PST 24
Peak memory 194440 kb
Host smart-b12c11ec-1123-4347-bfe6-8f86b8dee2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299133259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.299133259
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2004325711
Short name T280
Test name
Test status
Simulation time 320935035 ps
CPU time 1.58 seconds
Started Feb 25 01:43:03 PM PST 24
Finished Feb 25 01:43:05 PM PST 24
Peak memory 198028 kb
Host smart-46b2dda5-9b26-41ec-8041-99a94a7e0994
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004325711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2004325711
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4198475540
Short name T335
Test name
Test status
Simulation time 93352960 ps
CPU time 1.7 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:04 PM PST 24
Peak memory 195848 kb
Host smart-6d4ff72c-e4ce-4365-987f-6664b184384f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198475540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4198475540
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.937896312
Short name T425
Test name
Test status
Simulation time 79436992 ps
CPU time 0.87 seconds
Started Feb 25 01:43:04 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 195864 kb
Host smart-e61537d5-709e-45c8-8071-6fc70b32f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937896312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.937896312
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.952609474
Short name T675
Test name
Test status
Simulation time 202650548 ps
CPU time 0.7 seconds
Started Feb 25 01:43:05 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 194348 kb
Host smart-3a5d94fe-3d09-4484-a3ab-e534d109fede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952609474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.952609474
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1970117811
Short name T500
Test name
Test status
Simulation time 431870743 ps
CPU time 2.85 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 198080 kb
Host smart-3f9b460e-466f-4a94-bb6d-76d70d41ceac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970117811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1970117811
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3049484496
Short name T40
Test name
Test status
Simulation time 97971988 ps
CPU time 0.96 seconds
Started Feb 25 01:43:11 PM PST 24
Finished Feb 25 01:43:13 PM PST 24
Peak memory 214984 kb
Host smart-49b3a7fe-6472-4812-a1b7-d2cab314520f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049484496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3049484496
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1442010240
Short name T539
Test name
Test status
Simulation time 371824596 ps
CPU time 1.3 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:04 PM PST 24
Peak memory 198048 kb
Host smart-8df92216-02d0-4a70-8682-44cbfc16c4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442010240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1442010240
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3356341838
Short name T102
Test name
Test status
Simulation time 186284641 ps
CPU time 1.04 seconds
Started Feb 25 01:43:07 PM PST 24
Finished Feb 25 01:43:08 PM PST 24
Peak memory 196464 kb
Host smart-06f6769e-25ea-43e0-a83b-2bcf0da9071e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356341838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3356341838
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.292086982
Short name T680
Test name
Test status
Simulation time 15672292666 ps
CPU time 106.82 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:44:44 PM PST 24
Peak memory 198260 kb
Host smart-6b3c0c52-e5e4-4287-b179-aa9734473923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292086982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.292086982
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2703919198
Short name T447
Test name
Test status
Simulation time 23197167 ps
CPU time 0.62 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 193908 kb
Host smart-409723de-d6bf-4817-920f-100dbf691dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703919198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2703919198
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4057516323
Short name T115
Test name
Test status
Simulation time 48680817 ps
CPU time 1.02 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:43:23 PM PST 24
Peak memory 196496 kb
Host smart-0e6f874d-22bb-4fcc-a835-8985a07a8188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057516323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4057516323
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1242116833
Short name T357
Test name
Test status
Simulation time 725099939 ps
CPU time 9.9 seconds
Started Feb 25 01:43:23 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 196852 kb
Host smart-68cbb349-5f3c-42a0-b229-2a5e1fecaa78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242116833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1242116833
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3845421241
Short name T479
Test name
Test status
Simulation time 85165651 ps
CPU time 1.04 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:43:22 PM PST 24
Peak memory 198020 kb
Host smart-b6019aec-b75e-4d73-a44f-11e00d9b248b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845421241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3845421241
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3305180206
Short name T544
Test name
Test status
Simulation time 329623874 ps
CPU time 1.43 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:18 PM PST 24
Peak memory 195920 kb
Host smart-386718af-1b94-4e3c-8777-9974e31e4a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305180206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3305180206
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4200531931
Short name T268
Test name
Test status
Simulation time 32405919 ps
CPU time 1.17 seconds
Started Feb 25 01:43:22 PM PST 24
Finished Feb 25 01:43:23 PM PST 24
Peak memory 195548 kb
Host smart-159f75ed-272a-4472-bb47-bc88c2f18837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200531931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4200531931
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.584480869
Short name T653
Test name
Test status
Simulation time 286834101 ps
CPU time 1.42 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 197052 kb
Host smart-520d1c1b-823f-432a-a38a-e9fa652350f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584480869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.584480869
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1843043071
Short name T634
Test name
Test status
Simulation time 45379896 ps
CPU time 1.17 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:43:20 PM PST 24
Peak memory 196612 kb
Host smart-0d7355c0-0358-4434-9b3f-45e9c204195a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843043071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1843043071
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.977283040
Short name T12
Test name
Test status
Simulation time 847670211 ps
CPU time 3.74 seconds
Started Feb 25 01:43:22 PM PST 24
Finished Feb 25 01:43:26 PM PST 24
Peak memory 197980 kb
Host smart-dc7cdd18-a945-4c03-836b-70a1a16d85aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977283040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.977283040
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3342680930
Short name T48
Test name
Test status
Simulation time 242538979 ps
CPU time 0.9 seconds
Started Feb 25 01:43:22 PM PST 24
Finished Feb 25 01:43:23 PM PST 24
Peak memory 213888 kb
Host smart-a18212c3-0b87-4f19-940b-819f0ca602d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342680930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3342680930
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2954955821
Short name T58
Test name
Test status
Simulation time 34920959 ps
CPU time 0.9 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 195356 kb
Host smart-fe7f5c86-e592-4498-aef0-c68880f1e1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954955821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2954955821
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2204848777
Short name T348
Test name
Test status
Simulation time 67917384 ps
CPU time 1.01 seconds
Started Feb 25 01:43:20 PM PST 24
Finished Feb 25 01:43:21 PM PST 24
Peak memory 196304 kb
Host smart-e8bfab24-d66f-4b7f-bcb3-377fd8518169
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204848777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2204848777
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3093085567
Short name T189
Test name
Test status
Simulation time 35610680717 ps
CPU time 135.32 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:45:34 PM PST 24
Peak memory 198224 kb
Host smart-908aa344-9e03-4853-b9ff-edfb1923b1dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093085567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3093085567
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3585443261
Short name T96
Test name
Test status
Simulation time 280999708394 ps
CPU time 1637.13 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 02:10:35 PM PST 24
Peak memory 198372 kb
Host smart-b3388646-0be0-411a-a328-e74b56c4d017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3585443261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3585443261
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2284585794
Short name T238
Test name
Test status
Simulation time 70282319 ps
CPU time 0.82 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 196128 kb
Host smart-9b30a746-f66a-4f83-ba0c-5d6b49697078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284585794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2284585794
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.722643572
Short name T220
Test name
Test status
Simulation time 1377757952 ps
CPU time 23.57 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 197012 kb
Host smart-d9b9ecbf-b691-4eb3-a924-5e2d240f20fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722643572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.722643572
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1704850180
Short name T32
Test name
Test status
Simulation time 59229518 ps
CPU time 0.89 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 196716 kb
Host smart-e6a198e4-dc3f-4811-bc06-c0f3052ed485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704850180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1704850180
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1888987147
Short name T114
Test name
Test status
Simulation time 148574508 ps
CPU time 1.23 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 195476 kb
Host smart-411f9ab4-5981-4191-986b-2a25759277fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888987147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1888987147
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1183966721
Short name T515
Test name
Test status
Simulation time 268228558 ps
CPU time 2.77 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 198124 kb
Host smart-6c8e18a5-dfec-4aac-a0b4-1a7960364251
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183966721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1183966721
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.190066462
Short name T472
Test name
Test status
Simulation time 40469490 ps
CPU time 1.22 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:43:51 PM PST 24
Peak memory 197484 kb
Host smart-ad672f0a-b625-4d15-a057-d55b4b504a4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190066462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
190066462
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2594477686
Short name T253
Test name
Test status
Simulation time 33140082 ps
CPU time 0.68 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 195328 kb
Host smart-baf18d3f-e0ec-4432-a125-ceaee2765b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594477686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2594477686
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.682572365
Short name T380
Test name
Test status
Simulation time 100407992 ps
CPU time 0.78 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 196232 kb
Host smart-b0373ec2-756e-42bd-8133-ce6ae433161c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682572365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.682572365
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.695255032
Short name T404
Test name
Test status
Simulation time 2226282843 ps
CPU time 6.62 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 198144 kb
Host smart-a2af7250-fdf9-4b56-966b-bc7cbf4449e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695255032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.695255032
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.34975224
Short name T153
Test name
Test status
Simulation time 209504834 ps
CPU time 1.12 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 195764 kb
Host smart-bd178679-d042-456a-a4ee-c4103a399fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34975224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.34975224
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2803902261
Short name T27
Test name
Test status
Simulation time 139168432 ps
CPU time 1.18 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 195756 kb
Host smart-c5554212-6c3c-466b-ac0e-6d0e2b3a5a5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803902261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2803902261
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.161171800
Short name T275
Test name
Test status
Simulation time 31883928082 ps
CPU time 225.6 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:47:22 PM PST 24
Peak memory 198220 kb
Host smart-2e038369-660f-47ec-833e-bfacd136505c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161171800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.161171800
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4181737851
Short name T678
Test name
Test status
Simulation time 17437928 ps
CPU time 0.55 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 194632 kb
Host smart-355e8cb5-14d4-4195-bf08-5b38df647d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181737851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4181737851
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2508256853
Short name T594
Test name
Test status
Simulation time 81746316 ps
CPU time 0.62 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 194132 kb
Host smart-7bf0c646-5483-42b4-8d15-28ffa64f7b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508256853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2508256853
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1298910837
Short name T278
Test name
Test status
Simulation time 2977154748 ps
CPU time 21.83 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 197080 kb
Host smart-ef5bcaf5-331b-4fc8-9e5a-b01fb02a5044
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298910837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1298910837
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3792163807
Short name T283
Test name
Test status
Simulation time 37938899 ps
CPU time 0.63 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 194324 kb
Host smart-c3136499-a7d4-4c2b-840e-b40a4871ce4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792163807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3792163807
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3304461129
Short name T66
Test name
Test status
Simulation time 42128499 ps
CPU time 0.67 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 194304 kb
Host smart-e147153b-3f79-43d6-83e1-50ddf7385f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304461129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3304461129
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3242287461
Short name T414
Test name
Test status
Simulation time 188695925 ps
CPU time 3.65 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 198136 kb
Host smart-ceb5e43e-5c58-40df-8239-c54585c8b6bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242287461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3242287461
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.287613865
Short name T388
Test name
Test status
Simulation time 153388388 ps
CPU time 1.67 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 196112 kb
Host smart-fcebd74e-4f28-4056-a431-1a2640d46f47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287613865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
287613865
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2674624391
Short name T647
Test name
Test status
Simulation time 130841602 ps
CPU time 0.87 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 196672 kb
Host smart-21b1bfbe-3027-47ad-930a-46c55f6b5a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674624391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2674624391
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4264222046
Short name T341
Test name
Test status
Simulation time 22061377 ps
CPU time 0.82 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 197460 kb
Host smart-1ec985b2-4e81-4770-932f-96e5d0d73e08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264222046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4264222046
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.173499582
Short name T222
Test name
Test status
Simulation time 375341947 ps
CPU time 5.01 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 198032 kb
Host smart-f5b61286-102c-4bf9-9026-c5b540213d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173499582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.173499582
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3480318530
Short name T483
Test name
Test status
Simulation time 187672439 ps
CPU time 1.33 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 196652 kb
Host smart-1377153b-5c94-4032-a81f-9c3eefe6ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480318530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3480318530
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3369754282
Short name T148
Test name
Test status
Simulation time 136892688 ps
CPU time 1.27 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 195796 kb
Host smart-ed4f5dc2-277b-48be-90e9-d3f15e4e5e0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369754282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3369754282
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3516191524
Short name T534
Test name
Test status
Simulation time 17250350 ps
CPU time 0.56 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 193924 kb
Host smart-de37c106-749b-45a3-9b9b-12f23c3a037d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516191524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3516191524
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2156267483
Short name T136
Test name
Test status
Simulation time 39903224 ps
CPU time 0.96 seconds
Started Feb 25 01:43:42 PM PST 24
Finished Feb 25 01:43:43 PM PST 24
Peak memory 195924 kb
Host smart-710be854-ed7d-4815-aae2-80c1e6102f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156267483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2156267483
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2675929188
Short name T382
Test name
Test status
Simulation time 2106273212 ps
CPU time 11.83 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 195556 kb
Host smart-dd8c3d63-339e-4a5a-9002-8ab062db5d1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675929188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2675929188
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1023401525
Short name T644
Test name
Test status
Simulation time 36108560 ps
CPU time 0.78 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 195780 kb
Host smart-1f37224d-3c5d-43fb-a446-8ddd8d7d0a3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023401525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1023401525
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.687218385
Short name T223
Test name
Test status
Simulation time 29692987 ps
CPU time 0.96 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 196796 kb
Host smart-7654e6b7-20b8-47ad-bdf7-8974cb926634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687218385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.687218385
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2608678588
Short name T326
Test name
Test status
Simulation time 121171442 ps
CPU time 1.8 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 198292 kb
Host smart-f3c39a49-847c-4a8c-9dd6-fce8e570c752
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608678588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2608678588
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2339172501
Short name T496
Test name
Test status
Simulation time 331515342 ps
CPU time 2.03 seconds
Started Feb 25 01:43:41 PM PST 24
Finished Feb 25 01:43:44 PM PST 24
Peak memory 196264 kb
Host smart-aa6a72c0-4fe6-4b5b-abb8-ac76a67732b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339172501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2339172501
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3069460369
Short name T171
Test name
Test status
Simulation time 113266482 ps
CPU time 0.87 seconds
Started Feb 25 01:43:42 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 196568 kb
Host smart-c2bfcf9a-3ddc-4ae9-a04f-9dd6f5a26e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069460369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3069460369
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.379200908
Short name T141
Test name
Test status
Simulation time 25731297 ps
CPU time 1.02 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 195888 kb
Host smart-de52ce1b-5179-4563-8ea3-115258f66915
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379200908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.379200908
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2868723625
Short name T351
Test name
Test status
Simulation time 254750855 ps
CPU time 4.57 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:43 PM PST 24
Peak memory 197928 kb
Host smart-d63bd8f2-767a-4dea-8d6b-8e134f928ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868723625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2868723625
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.233554857
Short name T172
Test name
Test status
Simulation time 133334587 ps
CPU time 1.13 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 197128 kb
Host smart-b0da02f2-2c82-4c57-a764-c0c6411982c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233554857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.233554857
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1483373399
Short name T654
Test name
Test status
Simulation time 35836958 ps
CPU time 0.82 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 196116 kb
Host smart-97feba95-49e9-4332-9be4-55f7197e26e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483373399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1483373399
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2411179035
Short name T412
Test name
Test status
Simulation time 117330124773 ps
CPU time 152.79 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 198116 kb
Host smart-7e565382-dbec-49d7-9652-65f5b53c882b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411179035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2411179035
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1116094543
Short name T62
Test name
Test status
Simulation time 22330523832 ps
CPU time 245.24 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:47:53 PM PST 24
Peak memory 198264 kb
Host smart-11c90652-8d54-4e76-9f5f-840ffd6a1a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1116094543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1116094543
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.861478549
Short name T582
Test name
Test status
Simulation time 13732987 ps
CPU time 0.59 seconds
Started Feb 25 01:43:45 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 194808 kb
Host smart-880bf3b5-c3e5-43b8-83e6-483de719252a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861478549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.861478549
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4007881995
Short name T643
Test name
Test status
Simulation time 188641751 ps
CPU time 0.92 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 195672 kb
Host smart-0c8d597b-7338-48c7-9074-55971c6434e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007881995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4007881995
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.744617553
Short name T705
Test name
Test status
Simulation time 820392538 ps
CPU time 5.37 seconds
Started Feb 25 01:43:43 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 195656 kb
Host smart-0f0cc0f9-b1f5-4b94-aef2-c56c6672e3fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744617553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.744617553
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1681445563
Short name T453
Test name
Test status
Simulation time 39049741 ps
CPU time 0.78 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 195820 kb
Host smart-7259f94f-93cf-4afc-a754-643bc3486567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681445563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1681445563
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3052799193
Short name T313
Test name
Test status
Simulation time 56747329 ps
CPU time 1.11 seconds
Started Feb 25 01:43:45 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 196196 kb
Host smart-ec35e598-b396-45c5-aa50-3fbc66ba6a48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052799193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3052799193
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3685919669
Short name T439
Test name
Test status
Simulation time 127806524 ps
CPU time 1.49 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 196744 kb
Host smart-fe7a1a0a-770e-4dd0-92a7-fc60eb19e255
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685919669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3685919669
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.357962594
Short name T54
Test name
Test status
Simulation time 156899471 ps
CPU time 3.22 seconds
Started Feb 25 01:43:43 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 198116 kb
Host smart-8555617c-2829-46df-8f4b-fa6d7bc99301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357962594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
357962594
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3209939283
Short name T428
Test name
Test status
Simulation time 30854899 ps
CPU time 1.06 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 196616 kb
Host smart-01464a39-7c10-455a-a9eb-3459294e35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209939283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3209939283
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.612063344
Short name T462
Test name
Test status
Simulation time 71985897 ps
CPU time 1.5 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 196868 kb
Host smart-f402aa31-6c64-464a-ba99-0ec0f787b0cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612063344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.612063344
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1546571245
Short name T415
Test name
Test status
Simulation time 64839893 ps
CPU time 2.95 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 198120 kb
Host smart-f0acd577-02fb-4638-ba4f-f7cd8e1cfef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546571245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1546571245
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3332875588
Short name T580
Test name
Test status
Simulation time 107795206 ps
CPU time 1.43 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 196964 kb
Host smart-03574166-5d28-4727-aa93-7b520d772f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332875588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3332875588
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.218863496
Short name T508
Test name
Test status
Simulation time 148268207 ps
CPU time 1.24 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 198088 kb
Host smart-51d21392-c297-42db-b8b8-9654765b7f70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218863496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.218863496
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1145736729
Short name T518
Test name
Test status
Simulation time 14824196346 ps
CPU time 54.43 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:44:41 PM PST 24
Peak memory 198236 kb
Host smart-22419231-1df4-4c09-8f25-559e9577680b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145736729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1145736729
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.512436446
Short name T349
Test name
Test status
Simulation time 14312694 ps
CPU time 0.58 seconds
Started Feb 25 01:43:42 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 194620 kb
Host smart-13104a89-50c5-45a6-8dba-0d98b7837c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512436446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.512436446
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3903860015
Short name T525
Test name
Test status
Simulation time 21403840 ps
CPU time 0.72 seconds
Started Feb 25 01:43:46 PM PST 24
Finished Feb 25 01:43:47 PM PST 24
Peak memory 194956 kb
Host smart-e539a559-40ef-4cf3-b019-7e19b976a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903860015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3903860015
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2994681511
Short name T563
Test name
Test status
Simulation time 272691121 ps
CPU time 7.29 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:54 PM PST 24
Peak memory 195580 kb
Host smart-e579cc81-52b0-4775-b1b9-8af252f67533
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994681511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2994681511
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1186993228
Short name T578
Test name
Test status
Simulation time 52161812 ps
CPU time 0.7 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 194296 kb
Host smart-20f8a467-689f-4f4c-b74f-125a9e6d1632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186993228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1186993228
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.80695061
Short name T609
Test name
Test status
Simulation time 247959643 ps
CPU time 0.77 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 195568 kb
Host smart-a4c2fa58-39cd-44bd-8973-1b469dd5ab9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80695061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.80695061
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2797004184
Short name T516
Test name
Test status
Simulation time 349611355 ps
CPU time 3.53 seconds
Started Feb 25 01:43:43 PM PST 24
Finished Feb 25 01:43:47 PM PST 24
Peak memory 196412 kb
Host smart-da5a4165-3e3e-46d6-9ef3-a2ce1f27c258
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797004184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2797004184
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2301977685
Short name T375
Test name
Test status
Simulation time 30674571 ps
CPU time 0.89 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 194016 kb
Host smart-8a9f395e-c028-4255-881a-2a5ea244b9bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301977685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2301977685
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3226120460
Short name T432
Test name
Test status
Simulation time 39992016 ps
CPU time 0.76 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:43:51 PM PST 24
Peak memory 195428 kb
Host smart-a7546f7f-5f21-4800-a98d-6831389a254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226120460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3226120460
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2634779379
Short name T511
Test name
Test status
Simulation time 54929443 ps
CPU time 1.1 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 196600 kb
Host smart-b002abae-b039-41e5-98b2-8aa5c06545d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634779379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2634779379
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3479325667
Short name T6
Test name
Test status
Simulation time 1667489507 ps
CPU time 4.68 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 198052 kb
Host smart-4fe00063-63a3-4b2b-9da4-68d15f72e525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479325667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3479325667
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.292784369
Short name T363
Test name
Test status
Simulation time 40575635 ps
CPU time 1.3 seconds
Started Feb 25 01:43:43 PM PST 24
Finished Feb 25 01:43:44 PM PST 24
Peak memory 196492 kb
Host smart-958d7ffb-06d7-465a-8b31-a7298d795c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292784369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.292784369
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.933866198
Short name T422
Test name
Test status
Simulation time 69505674 ps
CPU time 1.17 seconds
Started Feb 25 01:43:45 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 195752 kb
Host smart-bf1cd878-e60f-41ce-9e72-8343d022092c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933866198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.933866198
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3758858584
Short name T366
Test name
Test status
Simulation time 9417064214 ps
CPU time 25.4 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:44:13 PM PST 24
Peak memory 198192 kb
Host smart-c19a7a33-ade0-4c95-9c92-a7ddf1e4dfb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758858584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3758858584
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1983988097
Short name T697
Test name
Test status
Simulation time 185238455392 ps
CPU time 746.66 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:56:10 PM PST 24
Peak memory 198360 kb
Host smart-4fa14471-85ef-4637-b2cd-dc1d24f42a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1983988097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1983988097
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1539682950
Short name T631
Test name
Test status
Simulation time 26977159 ps
CPU time 0.56 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 193896 kb
Host smart-0ba576e7-a7b7-4a82-959c-89f2c1e35e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539682950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1539682950
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2262851782
Short name T387
Test name
Test status
Simulation time 127676399 ps
CPU time 0.88 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 195432 kb
Host smart-e19530e0-6685-4e3c-9ba9-492017bcef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262851782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2262851782
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.117004211
Short name T482
Test name
Test status
Simulation time 836953034 ps
CPU time 12.32 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 198040 kb
Host smart-1b6f10c2-6a81-410b-b212-39ea57fe4cbc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117004211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.117004211
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1110870011
Short name T221
Test name
Test status
Simulation time 290198944 ps
CPU time 0.99 seconds
Started Feb 25 01:43:52 PM PST 24
Finished Feb 25 01:43:53 PM PST 24
Peak memory 196612 kb
Host smart-f81bf11e-3569-4478-b41a-6cc4877e9bef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110870011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1110870011
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1608704303
Short name T247
Test name
Test status
Simulation time 334639011 ps
CPU time 1.05 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 196024 kb
Host smart-492e11a0-a0d3-410e-9dea-a3ecd7f81529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608704303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1608704303
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2501245486
Short name T620
Test name
Test status
Simulation time 21544995 ps
CPU time 0.93 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 195748 kb
Host smart-45549b88-33ca-45d6-963b-cbf908dd9da9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501245486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2501245486
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2409207567
Short name T434
Test name
Test status
Simulation time 336071770 ps
CPU time 1.87 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 196528 kb
Host smart-f274e5c7-e2a2-4cfd-986c-e6fc62f58ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409207567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2409207567
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.404900603
Short name T267
Test name
Test status
Simulation time 38142738 ps
CPU time 0.61 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:43:51 PM PST 24
Peak memory 194172 kb
Host smart-21fcdfff-4ad0-4e0a-9c83-1c56e48569d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404900603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.404900603
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1816334869
Short name T535
Test name
Test status
Simulation time 55144702 ps
CPU time 1.11 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 195688 kb
Host smart-2c982be2-3d6b-4812-9fb7-03e5e4bc85c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816334869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1816334869
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3115428519
Short name T200
Test name
Test status
Simulation time 492270012 ps
CPU time 6.02 seconds
Started Feb 25 01:43:52 PM PST 24
Finished Feb 25 01:43:58 PM PST 24
Peak memory 198036 kb
Host smart-d0067c5b-0d64-4146-8852-7be4cf74ff14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115428519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3115428519
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3399901047
Short name T373
Test name
Test status
Simulation time 34578405 ps
CPU time 0.79 seconds
Started Feb 25 01:43:57 PM PST 24
Finished Feb 25 01:43:58 PM PST 24
Peak memory 195276 kb
Host smart-b72a945f-6755-4e33-86ed-c7a969c03904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399901047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3399901047
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3684510529
Short name T557
Test name
Test status
Simulation time 58452431 ps
CPU time 1.17 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 196300 kb
Host smart-2f9525ed-e04c-42cf-8b62-251478b05031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684510529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3684510529
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3979515230
Short name T137
Test name
Test status
Simulation time 4031401930 ps
CPU time 111.16 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:45:38 PM PST 24
Peak memory 198192 kb
Host smart-610bb695-7a6e-46c9-a4ad-1b26f5ad258f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979515230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3979515230
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1992033387
Short name T509
Test name
Test status
Simulation time 35781458 ps
CPU time 0.6 seconds
Started Feb 25 01:43:53 PM PST 24
Finished Feb 25 01:43:54 PM PST 24
Peak memory 194912 kb
Host smart-3589b6c8-5d86-47e6-b94a-17e3d850d396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992033387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1992033387
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4000550491
Short name T622
Test name
Test status
Simulation time 48255485 ps
CPU time 0.74 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 194192 kb
Host smart-9f7e54ad-ae84-4bb6-95b6-cff5ec00b112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000550491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4000550491
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.111364295
Short name T217
Test name
Test status
Simulation time 466319573 ps
CPU time 24.65 seconds
Started Feb 25 01:43:46 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 196828 kb
Host smart-ac0aac9f-0561-4f87-a1d3-dcd5b5f09952
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111364295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.111364295
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1159633189
Short name T143
Test name
Test status
Simulation time 155970588 ps
CPU time 1.1 seconds
Started Feb 25 01:43:52 PM PST 24
Finished Feb 25 01:43:53 PM PST 24
Peak memory 198036 kb
Host smart-ee5467cd-b5e9-40fe-b45e-6ec2fb781b83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159633189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1159633189
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2280163683
Short name T389
Test name
Test status
Simulation time 166951074 ps
CPU time 1.33 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:53 PM PST 24
Peak memory 197460 kb
Host smart-514fa92c-512b-4c3c-8ec2-13dfea2ce7e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280163683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2280163683
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2193180854
Short name T421
Test name
Test status
Simulation time 77444676 ps
CPU time 2.96 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 198156 kb
Host smart-d131f826-d4c1-44ed-82eb-0e6d8ec5d5d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193180854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2193180854
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1126209288
Short name T261
Test name
Test status
Simulation time 125336034 ps
CPU time 1 seconds
Started Feb 25 01:44:01 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 196116 kb
Host smart-992791f7-10d1-449f-bcff-32ca583431a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126209288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1126209288
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1525315513
Short name T607
Test name
Test status
Simulation time 62963830 ps
CPU time 1.3 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 198140 kb
Host smart-6298035c-b41a-45c3-95cf-48126c3f6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525315513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1525315513
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3815111003
Short name T354
Test name
Test status
Simulation time 18676268 ps
CPU time 0.81 seconds
Started Feb 25 01:43:45 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 195552 kb
Host smart-1940afac-9a94-4888-b681-95297ecd66a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815111003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3815111003
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2498907431
Short name T4
Test name
Test status
Simulation time 190304380 ps
CPU time 2.51 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:43:53 PM PST 24
Peak memory 198076 kb
Host smart-055526cd-d32f-44e0-bd75-45f26a37d510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498907431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2498907431
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.120551792
Short name T560
Test name
Test status
Simulation time 246751590 ps
CPU time 1.19 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 196208 kb
Host smart-ad7be649-097c-4e79-9273-018c7dbb7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120551792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.120551792
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3179501586
Short name T569
Test name
Test status
Simulation time 121436146 ps
CPU time 0.82 seconds
Started Feb 25 01:43:45 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 195208 kb
Host smart-f662ea9c-dd53-44da-8798-998bc1d0eb40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179501586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3179501586
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1173113822
Short name T663
Test name
Test status
Simulation time 17898396378 ps
CPU time 59.88 seconds
Started Feb 25 01:43:52 PM PST 24
Finished Feb 25 01:44:52 PM PST 24
Peak memory 198156 kb
Host smart-18f2b4f9-a152-4a51-917c-277e64ce32e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173113822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1173113822
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3027074988
Short name T59
Test name
Test status
Simulation time 141778514025 ps
CPU time 751.68 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 198368 kb
Host smart-d786a9d5-7ca2-4042-b6ef-2b46177ab0fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3027074988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3027074988
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.248088463
Short name T677
Test name
Test status
Simulation time 14682735 ps
CPU time 0.57 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:44:06 PM PST 24
Peak memory 194128 kb
Host smart-407ba9ce-7032-4711-88a0-fdb8d04f62cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248088463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.248088463
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.896358201
Short name T169
Test name
Test status
Simulation time 25238313 ps
CPU time 0.79 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 195272 kb
Host smart-6465d187-5a89-4fe5-9150-a17db26b49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896358201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.896358201
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2820728878
Short name T558
Test name
Test status
Simulation time 1886978457 ps
CPU time 13.64 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:44:05 PM PST 24
Peak memory 196828 kb
Host smart-beece8cf-4c52-46ed-a31f-0862178cc7c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820728878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2820728878
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.356510091
Short name T9
Test name
Test status
Simulation time 61476177 ps
CPU time 0.88 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 197664 kb
Host smart-636096a4-6832-4b29-a5dc-c04296e89c28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356510091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.356510091
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3249637019
Short name T327
Test name
Test status
Simulation time 17319805 ps
CPU time 0.69 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 195168 kb
Host smart-89e1017a-1874-4be1-8251-05e82be5fc43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249637019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3249637019
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2661519337
Short name T390
Test name
Test status
Simulation time 23427249 ps
CPU time 1 seconds
Started Feb 25 01:43:50 PM PST 24
Finished Feb 25 01:43:51 PM PST 24
Peak memory 196116 kb
Host smart-be582f20-9f9a-4c1a-a8e4-1a374b0ea28a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661519337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2661519337
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2119022719
Short name T124
Test name
Test status
Simulation time 118408485 ps
CPU time 2.41 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:50 PM PST 24
Peak memory 196832 kb
Host smart-8a716992-90f6-413d-9e8d-2ed3b4d77675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119022719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2119022719
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2136133591
Short name T413
Test name
Test status
Simulation time 29576118 ps
CPU time 0.75 seconds
Started Feb 25 01:44:00 PM PST 24
Finished Feb 25 01:44:01 PM PST 24
Peak memory 195340 kb
Host smart-684d0a0f-e7ca-4810-9366-98bf159c50fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136133591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2136133591
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3825986345
Short name T111
Test name
Test status
Simulation time 69098770 ps
CPU time 0.89 seconds
Started Feb 25 01:43:47 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 196104 kb
Host smart-0dc608fb-f948-43d9-a8e5-5d020c0159e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825986345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3825986345
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2160014863
Short name T471
Test name
Test status
Simulation time 135385066 ps
CPU time 2.55 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:53 PM PST 24
Peak memory 198008 kb
Host smart-c61a719c-898f-4f96-afb7-3234ba0dc36f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160014863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2160014863
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1245439188
Short name T588
Test name
Test status
Simulation time 122883972 ps
CPU time 0.95 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 195604 kb
Host smart-1d38bc8f-f17d-4d7a-9011-efeb3c0216f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245439188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1245439188
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2705134479
Short name T353
Test name
Test status
Simulation time 320450569 ps
CPU time 1.3 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 196768 kb
Host smart-d2618f94-28dc-4459-8821-aa6236b1c042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705134479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2705134479
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.20785304
Short name T265
Test name
Test status
Simulation time 3250627930 ps
CPU time 55.09 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:45:00 PM PST 24
Peak memory 198192 kb
Host smart-434d3469-36d7-48a1-a985-b2c5bbc99286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20785304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gp
io_stress_all.20785304
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3481493190
Short name T61
Test name
Test status
Simulation time 145820373255 ps
CPU time 2252.08 seconds
Started Feb 25 01:44:01 PM PST 24
Finished Feb 25 02:21:34 PM PST 24
Peak memory 198288 kb
Host smart-ba392677-1130-404e-b01c-794a661d7554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3481493190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3481493190
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.720314185
Short name T617
Test name
Test status
Simulation time 50371316 ps
CPU time 0.61 seconds
Started Feb 25 01:43:53 PM PST 24
Finished Feb 25 01:43:54 PM PST 24
Peak memory 194828 kb
Host smart-f4ea9cac-7b46-4e13-b3ea-c9501413a2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720314185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.720314185
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2643872675
Short name T564
Test name
Test status
Simulation time 81864786 ps
CPU time 0.85 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:44:06 PM PST 24
Peak memory 195244 kb
Host smart-755062e6-c558-4c7a-bcab-6a1f25c7637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643872675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2643872675
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.702161017
Short name T97
Test name
Test status
Simulation time 4227353824 ps
CPU time 18.66 seconds
Started Feb 25 01:43:51 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 196688 kb
Host smart-9bcae73b-d561-4342-90ed-4783e583bc4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702161017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.702161017
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3273838607
Short name T581
Test name
Test status
Simulation time 28936475 ps
CPU time 0.67 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 194500 kb
Host smart-87b00f67-b2b1-4026-9f27-33f7089f8b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273838607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3273838607
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3570641803
Short name T513
Test name
Test status
Simulation time 345522359 ps
CPU time 1.01 seconds
Started Feb 25 01:43:56 PM PST 24
Finished Feb 25 01:43:57 PM PST 24
Peak memory 196892 kb
Host smart-35809dc6-d32e-4448-bfdc-f3b6ccac6b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570641803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3570641803
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1531880345
Short name T524
Test name
Test status
Simulation time 284632439 ps
CPU time 1.67 seconds
Started Feb 25 01:43:54 PM PST 24
Finished Feb 25 01:43:56 PM PST 24
Peak memory 196620 kb
Host smart-767e592c-f5cd-44c6-805d-a36631657ac5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531880345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1531880345
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.183511766
Short name T227
Test name
Test status
Simulation time 582684846 ps
CPU time 3.2 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:11 PM PST 24
Peak memory 195696 kb
Host smart-204d69f5-c62f-421e-85f7-4e33626a6afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183511766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
183511766
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4260585915
Short name T254
Test name
Test status
Simulation time 22441882 ps
CPU time 0.93 seconds
Started Feb 25 01:43:55 PM PST 24
Finished Feb 25 01:43:56 PM PST 24
Peak memory 196060 kb
Host smart-a2bb8cfc-b99b-4aee-9d23-0756fb1a9b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260585915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4260585915
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1494362370
Short name T134
Test name
Test status
Simulation time 857800843 ps
CPU time 1.05 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 195688 kb
Host smart-a1d56f0f-47ce-414f-b0a7-f6147e99f99e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494362370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1494362370
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1328618551
Short name T550
Test name
Test status
Simulation time 1853909084 ps
CPU time 5.75 seconds
Started Feb 25 01:43:59 PM PST 24
Finished Feb 25 01:44:05 PM PST 24
Peak memory 198080 kb
Host smart-61359aee-53e1-4ad9-83ec-a950d6863819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328618551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1328618551
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.900134241
Short name T686
Test name
Test status
Simulation time 130000508 ps
CPU time 0.98 seconds
Started Feb 25 01:43:59 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 195632 kb
Host smart-5e51d434-baea-4968-a3c7-b7c2026c23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900134241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.900134241
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1558470223
Short name T618
Test name
Test status
Simulation time 47378683 ps
CPU time 1.2 seconds
Started Feb 25 01:44:03 PM PST 24
Finished Feb 25 01:44:05 PM PST 24
Peak memory 195680 kb
Host smart-a3927e2a-7498-47c2-b600-e4a3f694f26a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558470223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1558470223
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2200046340
Short name T603
Test name
Test status
Simulation time 14709796710 ps
CPU time 105.51 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 197972 kb
Host smart-8ad33a9a-f708-46cf-8848-12ba899596b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200046340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2200046340
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.479074125
Short name T616
Test name
Test status
Simulation time 40746515 ps
CPU time 0.54 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:44:06 PM PST 24
Peak memory 194564 kb
Host smart-a35730f0-8bf4-4980-8a38-61fc426af112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479074125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.479074125
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2311600334
Short name T250
Test name
Test status
Simulation time 146528449 ps
CPU time 0.81 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 195068 kb
Host smart-8ee3f27e-6c83-41e5-899b-31ebbc750c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311600334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2311600334
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3814835185
Short name T216
Test name
Test status
Simulation time 1436821499 ps
CPU time 18.88 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:26 PM PST 24
Peak memory 196788 kb
Host smart-7f5acbd3-387d-4b94-943d-cfe9ed557407
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814835185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3814835185
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3416899452
Short name T579
Test name
Test status
Simulation time 49394692 ps
CPU time 0.92 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 196820 kb
Host smart-ae93bea9-2b23-4466-ad07-d071e5780d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416899452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3416899452
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.338516276
Short name T619
Test name
Test status
Simulation time 78509316 ps
CPU time 0.78 seconds
Started Feb 25 01:44:11 PM PST 24
Finished Feb 25 01:44:12 PM PST 24
Peak memory 195336 kb
Host smart-87593f57-504e-49f5-9c45-bfb778188720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338516276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.338516276
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.24248123
Short name T477
Test name
Test status
Simulation time 220662126 ps
CPU time 1.18 seconds
Started Feb 25 01:44:11 PM PST 24
Finished Feb 25 01:44:13 PM PST 24
Peak memory 198040 kb
Host smart-e00798e0-45d4-45e4-be00-2ecc795562a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24248123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.gpio_intr_with_filter_rand_intr_event.24248123
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2168935950
Short name T347
Test name
Test status
Simulation time 367973643 ps
CPU time 3.36 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:13 PM PST 24
Peak memory 197200 kb
Host smart-7d8b3804-9c1e-4338-a326-62a0bb0d6ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168935950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2168935950
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3162588212
Short name T152
Test name
Test status
Simulation time 74343469 ps
CPU time 0.7 seconds
Started Feb 25 01:44:01 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 195992 kb
Host smart-a19cc0ca-73fe-42e2-b290-ae7e30dc4b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162588212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3162588212
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2176210177
Short name T601
Test name
Test status
Simulation time 133624571 ps
CPU time 0.92 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:44:06 PM PST 24
Peak memory 196704 kb
Host smart-51651941-20da-437d-84e4-1fb23d886134
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176210177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2176210177
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4185713148
Short name T248
Test name
Test status
Simulation time 127086434 ps
CPU time 1.71 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 198088 kb
Host smart-a74063e8-7adf-43da-bf62-f680e26c4493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185713148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4185713148
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3867268858
Short name T206
Test name
Test status
Simulation time 110871332 ps
CPU time 0.95 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 196144 kb
Host smart-635ca6bf-e3bb-43bb-a777-5a73ae2b1c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867268858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3867268858
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4273213128
Short name T202
Test name
Test status
Simulation time 97709783 ps
CPU time 0.8 seconds
Started Feb 25 01:43:53 PM PST 24
Finished Feb 25 01:43:54 PM PST 24
Peak memory 195356 kb
Host smart-6c53e2af-f6fd-4ad4-ae37-6daa38d19a8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273213128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4273213128
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2584193311
Short name T345
Test name
Test status
Simulation time 26462760898 ps
CPU time 83.18 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 198204 kb
Host smart-7586e0a0-d8e0-4627-8da7-e770520fd39d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584193311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2584193311
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.70343611
Short name T332
Test name
Test status
Simulation time 23752978 ps
CPU time 0.6 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:17 PM PST 24
Peak memory 194092 kb
Host smart-0e3002ae-0ffb-4086-8088-81821943f74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70343611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.70343611
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3436262248
Short name T628
Test name
Test status
Simulation time 56955266 ps
CPU time 0.73 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:43:22 PM PST 24
Peak memory 194680 kb
Host smart-8a4712fc-fb6d-4eb5-976e-1aa1d218da05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436262248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3436262248
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1049122347
Short name T669
Test name
Test status
Simulation time 894951389 ps
CPU time 7.58 seconds
Started Feb 25 01:43:20 PM PST 24
Finished Feb 25 01:43:28 PM PST 24
Peak memory 197220 kb
Host smart-9a194fab-1f75-4397-aeb8-7660b58bbcf4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049122347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1049122347
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2501548296
Short name T667
Test name
Test status
Simulation time 487838065 ps
CPU time 0.94 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:17 PM PST 24
Peak memory 196472 kb
Host smart-95148110-c35e-47af-b54a-3d82c2e48b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501548296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2501548296
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3706212205
Short name T274
Test name
Test status
Simulation time 214826097 ps
CPU time 1.05 seconds
Started Feb 25 01:43:17 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 196868 kb
Host smart-03500a1c-eca7-499e-b2ee-ec78ebe5b472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706212205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3706212205
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1984109888
Short name T703
Test name
Test status
Simulation time 361814427 ps
CPU time 3.33 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:43:22 PM PST 24
Peak memory 198080 kb
Host smart-a9f4d434-36fe-4051-b309-2982a60f32c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984109888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1984109888
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1535482559
Short name T266
Test name
Test status
Simulation time 251394943 ps
CPU time 1.15 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:18 PM PST 24
Peak memory 195536 kb
Host smart-9dff67a0-ee9e-48bd-a28e-6bd86ceb59cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535482559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1535482559
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1688441976
Short name T219
Test name
Test status
Simulation time 63857208 ps
CPU time 1.18 seconds
Started Feb 25 01:43:17 PM PST 24
Finished Feb 25 01:43:18 PM PST 24
Peak memory 196124 kb
Host smart-578d2144-3815-43b5-a9de-29db60a68140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688441976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1688441976
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3832562247
Short name T561
Test name
Test status
Simulation time 31739306 ps
CPU time 0.86 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:43:22 PM PST 24
Peak memory 196408 kb
Host smart-0ee0d3c5-c524-4d08-b54c-e72728ffe118
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832562247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3832562247
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.401613821
Short name T226
Test name
Test status
Simulation time 199706755 ps
CPU time 3.6 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:43:23 PM PST 24
Peak memory 198044 kb
Host smart-65b7cd24-ed47-4de4-99f1-84a2a153c806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401613821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.401613821
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.145305855
Short name T41
Test name
Test status
Simulation time 229078500 ps
CPU time 0.89 seconds
Started Feb 25 01:43:17 PM PST 24
Finished Feb 25 01:43:18 PM PST 24
Peak memory 213760 kb
Host smart-7ae89fb6-8079-4dfe-ac48-69c1f2c45732
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145305855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.145305855
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3704635282
Short name T381
Test name
Test status
Simulation time 538162393 ps
CPU time 1.32 seconds
Started Feb 25 01:43:16 PM PST 24
Finished Feb 25 01:43:18 PM PST 24
Peak memory 198056 kb
Host smart-98346422-3f19-4a17-8aab-012ce70fad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704635282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3704635282
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4129521576
Short name T37
Test name
Test status
Simulation time 49701282 ps
CPU time 1.28 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:43:21 PM PST 24
Peak memory 196632 kb
Host smart-15c1f474-609c-4525-b4eb-697e885a7f99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129521576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4129521576
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3754269821
Short name T1
Test name
Test status
Simulation time 75557553478 ps
CPU time 204.14 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 198216 kb
Host smart-9e47bf41-36d3-4990-9d1a-2efd092353a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754269821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3754269821
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3655942650
Short name T33
Test name
Test status
Simulation time 53167804472 ps
CPU time 745.26 seconds
Started Feb 25 01:43:17 PM PST 24
Finished Feb 25 01:55:43 PM PST 24
Peak memory 198284 kb
Host smart-6e462d1c-67b0-4f60-b386-4b79b33f1c18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3655942650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3655942650
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.455279013
Short name T445
Test name
Test status
Simulation time 48186910 ps
CPU time 0.61 seconds
Started Feb 25 01:44:10 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 194132 kb
Host smart-271806fb-14ad-4532-84c2-195effe2f77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455279013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.455279013
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.651094460
Short name T490
Test name
Test status
Simulation time 54806948 ps
CPU time 0.69 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 193980 kb
Host smart-28d71d81-eb9b-492c-92e8-73937647513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651094460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.651094460
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3492373093
Short name T155
Test name
Test status
Simulation time 1868598368 ps
CPU time 15.12 seconds
Started Feb 25 01:44:11 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 196772 kb
Host smart-1ce9031a-3191-4680-90b3-ace1bbab2745
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492373093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3492373093
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2562565516
Short name T302
Test name
Test status
Simulation time 43259197 ps
CPU time 0.74 seconds
Started Feb 25 01:44:11 PM PST 24
Finished Feb 25 01:44:12 PM PST 24
Peak memory 195472 kb
Host smart-6c917e91-19a0-452c-acf6-c6f5e58f76f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562565516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2562565516
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.586298387
Short name T308
Test name
Test status
Simulation time 99893743 ps
CPU time 0.86 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 196912 kb
Host smart-b3c1d8f5-9981-4e13-a72a-2ce157605a34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586298387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.586298387
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2220645203
Short name T570
Test name
Test status
Simulation time 49324582 ps
CPU time 1.03 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 197008 kb
Host smart-c2db9d73-a9d5-4a11-a693-4159b3e841f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220645203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2220645203
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2801348459
Short name T571
Test name
Test status
Simulation time 156884060 ps
CPU time 1.45 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 195860 kb
Host smart-45b23be7-e936-40f7-b11c-ead7d4bcd3f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801348459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2801348459
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2782150242
Short name T402
Test name
Test status
Simulation time 56094152 ps
CPU time 1.02 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 195852 kb
Host smart-94d6f6d4-ad96-4c98-a608-d3d93660a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782150242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2782150242
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1280805547
Short name T228
Test name
Test status
Simulation time 245501409 ps
CPU time 1.01 seconds
Started Feb 25 01:44:20 PM PST 24
Finished Feb 25 01:44:21 PM PST 24
Peak memory 195824 kb
Host smart-2254164d-fe6c-43c8-8a42-d2a7f2cd25c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280805547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1280805547
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1282748486
Short name T151
Test name
Test status
Simulation time 51606108 ps
CPU time 1.2 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:44:07 PM PST 24
Peak memory 198080 kb
Host smart-46e7c9e0-f50f-421c-9e9f-1a7914692baf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282748486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1282748486
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3919177466
Short name T328
Test name
Test status
Simulation time 72566396 ps
CPU time 1.24 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 196900 kb
Host smart-ab3dfaaf-8307-4977-9ada-e20d8cf4a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919177466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3919177466
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1826902646
Short name T116
Test name
Test status
Simulation time 377636247 ps
CPU time 1.44 seconds
Started Feb 25 01:44:11 PM PST 24
Finished Feb 25 01:44:13 PM PST 24
Peak memory 196896 kb
Host smart-3b1c19ac-5990-4e85-87fd-323837e13683
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826902646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1826902646
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.4171090409
Short name T585
Test name
Test status
Simulation time 5922570054 ps
CPU time 39.61 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 198184 kb
Host smart-0e8411a1-425a-4cab-aa52-23b010e2084c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171090409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.4171090409
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2384966632
Short name T394
Test name
Test status
Simulation time 21872557 ps
CPU time 0.55 seconds
Started Feb 25 01:44:16 PM PST 24
Finished Feb 25 01:44:17 PM PST 24
Peak memory 194128 kb
Host smart-d286e588-a017-4f1b-bcdd-3e902113778d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384966632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2384966632
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1890870144
Short name T218
Test name
Test status
Simulation time 90960236 ps
CPU time 0.73 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 195248 kb
Host smart-d0aed463-6089-4d58-baed-746e06c009dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890870144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1890870144
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1757242555
Short name T242
Test name
Test status
Simulation time 1425098652 ps
CPU time 21.35 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 197300 kb
Host smart-d69b9cc2-74bb-441c-a9a0-8fff12af6db6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757242555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1757242555
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2104074463
Short name T590
Test name
Test status
Simulation time 56681531 ps
CPU time 0.88 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 197848 kb
Host smart-69d7f274-3a38-46f8-9530-046a3ac34ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104074463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2104074463
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2803852577
Short name T526
Test name
Test status
Simulation time 57870163 ps
CPU time 0.69 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 194300 kb
Host smart-d8227b79-d922-4fcd-abca-3f2172f1805a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803852577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2803852577
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3504278368
Short name T641
Test name
Test status
Simulation time 694755084 ps
CPU time 1.83 seconds
Started Feb 25 01:44:05 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 198152 kb
Host smart-290a21a6-a7d2-4f1b-877d-788b5c36bea2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504278368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3504278368
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.385550485
Short name T337
Test name
Test status
Simulation time 50853629 ps
CPU time 1.63 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 196848 kb
Host smart-0205a507-a6f6-4be2-8ceb-122403389b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385550485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
385550485
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.972475548
Short name T258
Test name
Test status
Simulation time 45981202 ps
CPU time 0.7 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 195424 kb
Host smart-46207aac-8480-4391-9ce2-0388771d80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972475548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.972475548
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.405635714
Short name T196
Test name
Test status
Simulation time 33760867 ps
CPU time 1.27 seconds
Started Feb 25 01:44:08 PM PST 24
Finished Feb 25 01:44:10 PM PST 24
Peak memory 197136 kb
Host smart-d1a2d278-ceae-473e-8c05-8615984f9e72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405635714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.405635714
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3256073057
Short name T378
Test name
Test status
Simulation time 380104715 ps
CPU time 4.96 seconds
Started Feb 25 01:44:06 PM PST 24
Finished Feb 25 01:44:11 PM PST 24
Peak memory 198016 kb
Host smart-26fe0d24-8f15-425c-95a3-6118786cb919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256073057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3256073057
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.517976490
Short name T554
Test name
Test status
Simulation time 90206481 ps
CPU time 1.56 seconds
Started Feb 25 01:44:09 PM PST 24
Finished Feb 25 01:44:11 PM PST 24
Peak memory 198044 kb
Host smart-310fc887-d43c-4f9d-84f2-ed8617babfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517976490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.517976490
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2047046831
Short name T386
Test name
Test status
Simulation time 275846496 ps
CPU time 1.3 seconds
Started Feb 25 01:44:07 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 197964 kb
Host smart-6220b3fc-c035-49a4-8da7-b238e46f64c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047046831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2047046831
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3626161979
Short name T271
Test name
Test status
Simulation time 11216504830 ps
CPU time 158.24 seconds
Started Feb 25 01:44:10 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 198204 kb
Host smart-1ded4c46-e19c-4c27-835e-37b8cf7cb84e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626161979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3626161979
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1467395852
Short name T289
Test name
Test status
Simulation time 22201070 ps
CPU time 0.56 seconds
Started Feb 25 01:44:16 PM PST 24
Finished Feb 25 01:44:18 PM PST 24
Peak memory 193888 kb
Host smart-e0bdcd5b-7971-4344-8dbf-82b2572db8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467395852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1467395852
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1917327852
Short name T546
Test name
Test status
Simulation time 74004914 ps
CPU time 0.81 seconds
Started Feb 25 01:44:16 PM PST 24
Finished Feb 25 01:44:18 PM PST 24
Peak memory 196176 kb
Host smart-a5246bff-f25f-461f-a18d-7c9f01a81fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917327852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1917327852
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.280813537
Short name T596
Test name
Test status
Simulation time 972398213 ps
CPU time 26.55 seconds
Started Feb 25 01:44:18 PM PST 24
Finished Feb 25 01:44:45 PM PST 24
Peak memory 194916 kb
Host smart-a4651fc6-eb13-4818-bd4b-bc13455cbae6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280813537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.280813537
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2230844273
Short name T17
Test name
Test status
Simulation time 50502724 ps
CPU time 0.79 seconds
Started Feb 25 01:44:13 PM PST 24
Finished Feb 25 01:44:14 PM PST 24
Peak memory 196004 kb
Host smart-60fbbf41-f641-4c56-80c2-4488cd6de0a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230844273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2230844273
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2084083603
Short name T132
Test name
Test status
Simulation time 60356077 ps
CPU time 1.17 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:15 PM PST 24
Peak memory 196120 kb
Host smart-3465b5eb-89ea-416b-b9bb-07093cc6fd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084083603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2084083603
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3919033613
Short name T139
Test name
Test status
Simulation time 247184474 ps
CPU time 2.71 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 196504 kb
Host smart-fb7ad251-905d-4e35-a7a8-675de5d640f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919033613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3919033613
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1089323328
Short name T664
Test name
Test status
Simulation time 352842996 ps
CPU time 2.82 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:18 PM PST 24
Peak memory 196832 kb
Host smart-816889b9-0b80-4781-9e36-c0eb0aa411ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089323328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1089323328
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2292343846
Short name T257
Test name
Test status
Simulation time 19589152 ps
CPU time 0.8 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:15 PM PST 24
Peak memory 195000 kb
Host smart-89ab9be6-9b48-4096-b775-cbc08cd7a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292343846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2292343846
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2626279622
Short name T273
Test name
Test status
Simulation time 81024656 ps
CPU time 0.96 seconds
Started Feb 25 01:44:13 PM PST 24
Finished Feb 25 01:44:14 PM PST 24
Peak memory 195924 kb
Host smart-d9ede2e8-6e1a-456e-aec8-69b9e3511e41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626279622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2626279622
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3107921739
Short name T698
Test name
Test status
Simulation time 410707908 ps
CPU time 4.97 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:44:23 PM PST 24
Peak memory 197876 kb
Host smart-448b1f1a-b164-4e73-b259-13c5a0d0074d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107921739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3107921739
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.4093894002
Short name T67
Test name
Test status
Simulation time 84667720 ps
CPU time 1.29 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 195624 kb
Host smart-b89700b5-4b49-403e-8d07-e19a15cb273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093894002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.4093894002
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3555917222
Short name T455
Test name
Test status
Simulation time 168832899 ps
CPU time 1.04 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 195820 kb
Host smart-22bf1e3f-8cad-422e-a9ff-8225bd512f64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555917222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3555917222
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1415778094
Short name T417
Test name
Test status
Simulation time 51775873127 ps
CPU time 120.39 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 198192 kb
Host smart-7968e9b7-c92e-462c-9119-34e716fd4820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415778094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1415778094
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1862998415
Short name T568
Test name
Test status
Simulation time 43658514 ps
CPU time 0.55 seconds
Started Feb 25 01:44:22 PM PST 24
Finished Feb 25 01:44:23 PM PST 24
Peak memory 193932 kb
Host smart-077f5c28-541b-4a59-982d-67c3e68e388b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862998415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1862998415
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2991701290
Short name T300
Test name
Test status
Simulation time 34248549 ps
CPU time 0.7 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:17 PM PST 24
Peak memory 194096 kb
Host smart-560a8365-cfaf-4254-a8d7-c1b18209cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991701290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2991701290
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2419129386
Short name T668
Test name
Test status
Simulation time 332570653 ps
CPU time 5.99 seconds
Started Feb 25 01:44:18 PM PST 24
Finished Feb 25 01:44:25 PM PST 24
Peak memory 195656 kb
Host smart-05fc09ab-dc1b-470b-8eed-b672f41eac9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419129386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2419129386
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1175872392
Short name T181
Test name
Test status
Simulation time 22297841 ps
CPU time 0.65 seconds
Started Feb 25 01:44:18 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 195452 kb
Host smart-ee2f6bdb-d420-4881-bd67-d961b4b0a6a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175872392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1175872392
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3294161250
Short name T213
Test name
Test status
Simulation time 83632264 ps
CPU time 1.38 seconds
Started Feb 25 01:44:13 PM PST 24
Finished Feb 25 01:44:14 PM PST 24
Peak memory 195864 kb
Host smart-774e8c54-0762-4963-8dba-a0f9b1535a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294161250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3294161250
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3681505945
Short name T215
Test name
Test status
Simulation time 177468965 ps
CPU time 1.74 seconds
Started Feb 25 01:44:16 PM PST 24
Finished Feb 25 01:44:20 PM PST 24
Peak memory 197376 kb
Host smart-e2b0e6de-786e-4182-8a38-cdd200c4657a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681505945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3681505945
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2526974354
Short name T53
Test name
Test status
Simulation time 1696563494 ps
CPU time 2.75 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:18 PM PST 24
Peak memory 198096 kb
Host smart-7793f59b-61b4-426d-bc79-2431ed2e6be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526974354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2526974354
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2141855217
Short name T158
Test name
Test status
Simulation time 118137519 ps
CPU time 0.86 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:15 PM PST 24
Peak memory 196148 kb
Host smart-10924f7b-9dbe-471f-b795-994cfdeccab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141855217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2141855217
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2142199221
Short name T57
Test name
Test status
Simulation time 105572337 ps
CPU time 0.79 seconds
Started Feb 25 01:44:18 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 195512 kb
Host smart-7263892e-14b4-49e6-88ff-e0a2c711f084
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142199221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2142199221
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4097528003
Short name T392
Test name
Test status
Simulation time 111430366 ps
CPU time 2.19 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:16 PM PST 24
Peak memory 198020 kb
Host smart-c74530f5-5bf3-4a1f-a3ef-c23ad5d460d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097528003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4097528003
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.222730233
Short name T501
Test name
Test status
Simulation time 128506495 ps
CPU time 1.11 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:16 PM PST 24
Peak memory 195840 kb
Host smart-37668fdb-13b4-4a15-84ff-ac15e8f24aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222730233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.222730233
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1393448006
Short name T70
Test name
Test status
Simulation time 149811850 ps
CPU time 0.94 seconds
Started Feb 25 01:44:20 PM PST 24
Finished Feb 25 01:44:21 PM PST 24
Peak memory 195236 kb
Host smart-6828ea90-c19e-4668-9deb-d27c9c23fa70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393448006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1393448006
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2650206200
Short name T458
Test name
Test status
Simulation time 5881497469 ps
CPU time 37.74 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:54 PM PST 24
Peak memory 198212 kb
Host smart-5e1681c1-5025-4c2a-8a22-cea78cc34810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650206200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2650206200
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.641451520
Short name T504
Test name
Test status
Simulation time 46906930 ps
CPU time 0.59 seconds
Started Feb 25 01:44:20 PM PST 24
Finished Feb 25 01:44:21 PM PST 24
Peak memory 193920 kb
Host smart-064ad46f-53ba-4e4a-a064-180c2e6517f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641451520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.641451520
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2301207892
Short name T149
Test name
Test status
Simulation time 58787555 ps
CPU time 0.81 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:16 PM PST 24
Peak memory 196176 kb
Host smart-3f2a73dd-d92d-4603-a84b-43b6c2166dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301207892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2301207892
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3558011126
Short name T629
Test name
Test status
Simulation time 1713668526 ps
CPU time 8.56 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 196840 kb
Host smart-a2083d91-ddfa-4564-8433-ddd21538a3f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558011126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3558011126
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4139559973
Short name T491
Test name
Test status
Simulation time 203011835 ps
CPU time 0.66 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:44:17 PM PST 24
Peak memory 194536 kb
Host smart-29d282b2-617d-43b9-85cf-44ce1fd36e28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139559973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4139559973
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1514637533
Short name T358
Test name
Test status
Simulation time 110812357 ps
CPU time 1.5 seconds
Started Feb 25 01:44:18 PM PST 24
Finished Feb 25 01:44:20 PM PST 24
Peak memory 196488 kb
Host smart-ac835141-a3c7-4203-9182-da4d063fa712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514637533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1514637533
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3307115709
Short name T692
Test name
Test status
Simulation time 257960723 ps
CPU time 2.68 seconds
Started Feb 25 01:44:23 PM PST 24
Finished Feb 25 01:44:26 PM PST 24
Peak memory 198168 kb
Host smart-7c4b3758-c8e8-4986-8609-1ab714f429a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307115709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3307115709
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2881376462
Short name T142
Test name
Test status
Simulation time 357010121 ps
CPU time 2.03 seconds
Started Feb 25 01:44:16 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 196188 kb
Host smart-0d28f805-b52d-4291-a401-5a5939c68d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881376462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2881376462
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.770192706
Short name T164
Test name
Test status
Simulation time 40483011 ps
CPU time 0.99 seconds
Started Feb 25 01:44:17 PM PST 24
Finished Feb 25 01:44:19 PM PST 24
Peak memory 196584 kb
Host smart-964fa3fa-4635-4805-b5c3-125ad4df0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770192706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.770192706
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2060679318
Short name T365
Test name
Test status
Simulation time 69230312 ps
CPU time 0.79 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:15 PM PST 24
Peak memory 196468 kb
Host smart-3996ecdf-ccf4-4ead-8957-6dd0ea8020a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060679318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2060679318
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3975566611
Short name T562
Test name
Test status
Simulation time 83721757 ps
CPU time 3.92 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:18 PM PST 24
Peak memory 197772 kb
Host smart-060a0a2d-1775-4381-a11d-dada5172d7b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975566611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3975566611
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1626094651
Short name T310
Test name
Test status
Simulation time 615282541 ps
CPU time 1.4 seconds
Started Feb 25 01:44:14 PM PST 24
Finished Feb 25 01:44:15 PM PST 24
Peak memory 195584 kb
Host smart-6a8d5d82-0174-408c-b23c-b5197e750bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626094651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1626094651
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2168635617
Short name T69
Test name
Test status
Simulation time 74640393 ps
CPU time 1.25 seconds
Started Feb 25 01:44:20 PM PST 24
Finished Feb 25 01:44:21 PM PST 24
Peak memory 195724 kb
Host smart-e392e472-5f0e-4bd8-b28b-687f1522e6d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168635617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2168635617
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2024710373
Short name T598
Test name
Test status
Simulation time 5463516004 ps
CPU time 129.57 seconds
Started Feb 25 01:44:15 PM PST 24
Finished Feb 25 01:46:25 PM PST 24
Peak memory 198220 kb
Host smart-a690ec9e-6858-4de1-b8e2-79bbef8beb04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024710373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2024710373
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4052914694
Short name T176
Test name
Test status
Simulation time 14005151 ps
CPU time 0.58 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 194100 kb
Host smart-5c6fedad-97a5-40df-ac8f-19fbca2bda6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052914694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4052914694
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4255893495
Short name T230
Test name
Test status
Simulation time 21859356 ps
CPU time 0.78 seconds
Started Feb 25 01:44:33 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 195352 kb
Host smart-fa3bc8d6-68ed-4be0-a2f8-07efdd5aa674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255893495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4255893495
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3909056512
Short name T173
Test name
Test status
Simulation time 820120622 ps
CPU time 10.61 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:38 PM PST 24
Peak memory 196812 kb
Host smart-badb1ccb-75a0-4140-9076-24cec10432ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909056512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3909056512
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.330190897
Short name T636
Test name
Test status
Simulation time 23730280 ps
CPU time 0.67 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 194588 kb
Host smart-da4ddc43-b883-4597-affd-f78501a01645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330190897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.330190897
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1938571036
Short name T232
Test name
Test status
Simulation time 305879973 ps
CPU time 1.28 seconds
Started Feb 25 01:44:25 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 196896 kb
Host smart-6af0e27e-729d-4bfe-ad17-369aa8bf278f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938571036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1938571036
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3481638543
Short name T296
Test name
Test status
Simulation time 91244440 ps
CPU time 1.03 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 196144 kb
Host smart-c77552f6-ef43-45dd-bc1c-5eca9aed0bfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481638543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3481638543
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.458751456
Short name T233
Test name
Test status
Simulation time 123416922 ps
CPU time 3.36 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 197276 kb
Host smart-3bfc710d-56cc-4385-bd75-17c609ce662c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458751456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
458751456
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3520333377
Short name T255
Test name
Test status
Simulation time 83658780 ps
CPU time 1.01 seconds
Started Feb 25 01:44:23 PM PST 24
Finished Feb 25 01:44:25 PM PST 24
Peak memory 196060 kb
Host smart-60fb47cf-81ee-44cb-9d45-07ea2fbb98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520333377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3520333377
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3682297038
Short name T658
Test name
Test status
Simulation time 86056058 ps
CPU time 1.04 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 196784 kb
Host smart-733a9f9c-c5ed-4eb4-be9b-f04b07239fdd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682297038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3682297038
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3028986436
Short name T140
Test name
Test status
Simulation time 1503915060 ps
CPU time 5.09 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:37 PM PST 24
Peak memory 198048 kb
Host smart-4dafba23-8a0d-4d6d-bfc2-fbb24cb80c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028986436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3028986436
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.556749607
Short name T497
Test name
Test status
Simulation time 314546877 ps
CPU time 1.35 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 198064 kb
Host smart-c3717fe0-6fa8-462f-b3be-b783e4a598b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556749607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.556749607
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2040059289
Short name T209
Test name
Test status
Simulation time 352916321 ps
CPU time 1.58 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 195672 kb
Host smart-4859801c-707a-42d7-9a68-68426550c12c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040059289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2040059289
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3187319245
Short name T576
Test name
Test status
Simulation time 70532780293 ps
CPU time 104.14 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:46:13 PM PST 24
Peak memory 198192 kb
Host smart-026bc4a5-67d6-4c19-b472-0bc1575d6880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187319245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3187319245
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4027307267
Short name T565
Test name
Test status
Simulation time 45315336 ps
CPU time 0.59 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 194000 kb
Host smart-5a3fd4f5-a4db-49ef-85bb-f4cec921ade5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027307267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4027307267
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2440156204
Short name T156
Test name
Test status
Simulation time 24973882 ps
CPU time 0.68 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 194232 kb
Host smart-d05ec90f-7220-43ce-8695-ce7fbbb47deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440156204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2440156204
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.629654348
Short name T252
Test name
Test status
Simulation time 858032000 ps
CPU time 10.29 seconds
Started Feb 25 01:44:36 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 196812 kb
Host smart-5b08a126-0afd-4286-bd6e-14993369e341
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629654348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.629654348
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2527817142
Short name T264
Test name
Test status
Simulation time 33183040 ps
CPU time 0.62 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 194600 kb
Host smart-70bcbb2b-60a1-4aaa-b813-e0d8309b4a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527817142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2527817142
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1401962610
Short name T256
Test name
Test status
Simulation time 44981742 ps
CPU time 0.92 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 197264 kb
Host smart-b441a8e9-786f-423c-b464-bc45d1c6497f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401962610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1401962610
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4149007180
Short name T203
Test name
Test status
Simulation time 53938198 ps
CPU time 2.04 seconds
Started Feb 25 01:44:25 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 198204 kb
Host smart-83ceaa13-52d1-4817-8e31-d20444303f81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149007180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4149007180
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.103242760
Short name T117
Test name
Test status
Simulation time 946146219 ps
CPU time 3.5 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:36 PM PST 24
Peak memory 196580 kb
Host smart-287b4403-c4fc-46c2-8289-a84081fab7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103242760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
103242760
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1288503447
Short name T174
Test name
Test status
Simulation time 102272617 ps
CPU time 1.05 seconds
Started Feb 25 01:44:25 PM PST 24
Finished Feb 25 01:44:26 PM PST 24
Peak memory 196020 kb
Host smart-0e438023-bae7-4496-8069-14db03953348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288503447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1288503447
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3818502230
Short name T444
Test name
Test status
Simulation time 46827788 ps
CPU time 1.01 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 196788 kb
Host smart-6c7bab93-6d7b-4089-a790-82bcbae6ae04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818502230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3818502230
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3624607466
Short name T130
Test name
Test status
Simulation time 268134867 ps
CPU time 4.42 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:35 PM PST 24
Peak memory 198080 kb
Host smart-7126e74d-7153-4145-88fb-7b2d905aede8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624607466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3624607466
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3419254887
Short name T442
Test name
Test status
Simulation time 220341737 ps
CPU time 1.09 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 195816 kb
Host smart-c5b4ebf0-e783-4d41-9205-ed8260983411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419254887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3419254887
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3538927855
Short name T384
Test name
Test status
Simulation time 69808056 ps
CPU time 1.05 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 195852 kb
Host smart-f6413e9a-d97c-41dd-bd52-d8067872efdb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538927855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3538927855
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2600480754
Short name T290
Test name
Test status
Simulation time 15345911088 ps
CPU time 217.61 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:48:08 PM PST 24
Peak memory 198192 kb
Host smart-9778d0da-54fe-4be0-93b4-ba8de88976d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600480754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2600480754
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3294852465
Short name T65
Test name
Test status
Simulation time 79923066225 ps
CPU time 1599.26 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 02:11:08 PM PST 24
Peak memory 198448 kb
Host smart-f8fee5a4-3bea-40c8-a8ae-f7f7334a7e90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3294852465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3294852465
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.546274747
Short name T43
Test name
Test status
Simulation time 42135580 ps
CPU time 0.59 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 194560 kb
Host smart-54276089-9120-4a40-a7db-8430fcb8ca03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546274747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.546274747
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1096757068
Short name T650
Test name
Test status
Simulation time 24741584 ps
CPU time 0.72 seconds
Started Feb 25 01:44:33 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 195244 kb
Host smart-e328291e-8fa2-44f9-b33d-e42c005c7d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096757068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1096757068
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2703749873
Short name T163
Test name
Test status
Simulation time 544598822 ps
CPU time 7.23 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:37 PM PST 24
Peak memory 196920 kb
Host smart-61687fcc-d888-41dc-a97c-21a5d76682bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703749873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2703749873
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.956784420
Short name T521
Test name
Test status
Simulation time 827150024 ps
CPU time 0.88 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 197744 kb
Host smart-bd10a6ab-5ede-4e72-8ca6-90d3a9a1cc9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956784420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.956784420
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.292285889
Short name T322
Test name
Test status
Simulation time 33057052 ps
CPU time 0.76 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 195468 kb
Host smart-5ceab546-662a-4da1-b7ec-b404fea8f526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292285889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.292285889
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3154872233
Short name T269
Test name
Test status
Simulation time 80364280 ps
CPU time 3.08 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 198092 kb
Host smart-a3c4fb3d-82a2-4286-8de7-cd6d8bf83e21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154872233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3154872233
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3279480631
Short name T323
Test name
Test status
Simulation time 788197635 ps
CPU time 1.28 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 195520 kb
Host smart-1a254ff6-8ab4-4de8-b807-9cc509623d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279480631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3279480631
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2940593395
Short name T157
Test name
Test status
Simulation time 253621355 ps
CPU time 1.11 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 195784 kb
Host smart-37b92e10-0e34-42bc-86dc-63a3a6febc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940593395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2940593395
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.706766868
Short name T502
Test name
Test status
Simulation time 72620410 ps
CPU time 0.67 seconds
Started Feb 25 01:44:25 PM PST 24
Finished Feb 25 01:44:26 PM PST 24
Peak memory 195048 kb
Host smart-1040423d-be06-44d6-8fb2-2a2915881be0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706766868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.706766868
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3820532094
Short name T584
Test name
Test status
Simulation time 82317811 ps
CPU time 3.75 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 198004 kb
Host smart-6bbb76a2-fa73-4bd3-a6f8-1a23d277f058
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820532094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3820532094
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1530966784
Short name T276
Test name
Test status
Simulation time 36346107 ps
CPU time 1.01 seconds
Started Feb 25 01:44:25 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 195928 kb
Host smart-d19a606b-59e8-41e5-b17b-f6f514f7ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530966784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1530966784
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.942239721
Short name T637
Test name
Test status
Simulation time 137179247 ps
CPU time 1.31 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 198048 kb
Host smart-a99f28a0-bd0f-4662-8401-40e1d307aae0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942239721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.942239721
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2130728118
Short name T301
Test name
Test status
Simulation time 4979842880 ps
CPU time 133.94 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 198168 kb
Host smart-8c6d3580-8d91-4bf7-8212-f1c84517a5dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130728118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2130728118
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2651952514
Short name T22
Test name
Test status
Simulation time 34186021 ps
CPU time 0.58 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 194664 kb
Host smart-de92f67b-3606-4ccb-b26c-5106913d634b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651952514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2651952514
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.193588034
Short name T159
Test name
Test status
Simulation time 288886265 ps
CPU time 0.72 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 195224 kb
Host smart-45365650-6168-44db-a8e7-25ca7e77f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193588034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.193588034
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.844372352
Short name T528
Test name
Test status
Simulation time 953133166 ps
CPU time 7.85 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:36 PM PST 24
Peak memory 197340 kb
Host smart-440e8f72-847f-47c9-8e05-7c0d612f6816
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844372352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.844372352
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2760525446
Short name T2
Test name
Test status
Simulation time 102046394 ps
CPU time 0.79 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 195908 kb
Host smart-cdf9266b-8522-412f-ae70-20f5159112f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760525446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2760525446
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1600767994
Short name T635
Test name
Test status
Simulation time 86415980 ps
CPU time 1.43 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 197220 kb
Host smart-75a4eade-9984-47d7-a78b-8df4e3936274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600767994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1600767994
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.594766010
Short name T182
Test name
Test status
Simulation time 77069210 ps
CPU time 3.44 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 198044 kb
Host smart-8f786533-f7de-411c-82e9-2d51be148b7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594766010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.594766010
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3808178632
Short name T397
Test name
Test status
Simulation time 29549751 ps
CPU time 0.94 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:27 PM PST 24
Peak memory 195564 kb
Host smart-c6250fce-754e-4aa4-93cb-0ce0932e4183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808178632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3808178632
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2205369630
Short name T239
Test name
Test status
Simulation time 207841510 ps
CPU time 1.24 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 196896 kb
Host smart-b21ca7ce-9213-4fdb-b57c-cff7933b9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205369630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2205369630
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1048504216
Short name T112
Test name
Test status
Simulation time 23738628 ps
CPU time 0.85 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 196492 kb
Host smart-32456972-4fb8-4bc9-8449-ec1f80d701a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048504216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1048504216
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1453680971
Short name T320
Test name
Test status
Simulation time 1339635601 ps
CPU time 5.85 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 197920 kb
Host smart-c06cc2d8-e7b7-4f86-9d16-e706bf9aa307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453680971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1453680971
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2648864812
Short name T688
Test name
Test status
Simulation time 52693038 ps
CPU time 1.14 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 196460 kb
Host smart-ac61a360-95cd-452f-ae11-083c1c402914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648864812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2648864812
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3154463475
Short name T602
Test name
Test status
Simulation time 74646210 ps
CPU time 1.06 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 196304 kb
Host smart-50ec8cc9-8eac-41d3-ba43-90513f384a3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154463475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3154463475
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3747168011
Short name T436
Test name
Test status
Simulation time 3259486197 ps
CPU time 36.47 seconds
Started Feb 25 01:44:26 PM PST 24
Finished Feb 25 01:45:03 PM PST 24
Peak memory 198180 kb
Host smart-ce974730-a114-4e21-b0ec-cfdd206a4f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747168011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3747168011
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1897588341
Short name T64
Test name
Test status
Simulation time 110020312352 ps
CPU time 902.96 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:59:32 PM PST 24
Peak memory 198464 kb
Host smart-01a73b12-93b4-441d-a16a-84d88ed43134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1897588341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1897588341
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2576068182
Short name T42
Test name
Test status
Simulation time 32196180 ps
CPU time 0.56 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 194620 kb
Host smart-e2b6ba6f-5ee1-4a47-b26e-9fe0976d6a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576068182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2576068182
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1079299271
Short name T633
Test name
Test status
Simulation time 47907088 ps
CPU time 0.83 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 197284 kb
Host smart-b9c6b5da-f02d-4e80-a3a3-78392ce05abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079299271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1079299271
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1331182814
Short name T452
Test name
Test status
Simulation time 602062281 ps
CPU time 8.96 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 01:44:37 PM PST 24
Peak memory 195636 kb
Host smart-517ddb95-27a7-4d58-a3a6-b753b38a8dc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331182814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1331182814
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4260712997
Short name T281
Test name
Test status
Simulation time 205205680 ps
CPU time 0.85 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 196052 kb
Host smart-97c1634b-ae47-4952-88cd-640053a7e7da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260712997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4260712997
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1829092006
Short name T431
Test name
Test status
Simulation time 91645489 ps
CPU time 1.35 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 197116 kb
Host smart-c156a57b-22be-4f73-8cf3-8e6fd1804752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829092006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1829092006
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.921973861
Short name T656
Test name
Test status
Simulation time 242092840 ps
CPU time 2.66 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 198092 kb
Host smart-709ed1f3-c66e-4554-9edf-2fc0f6e23099
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921973861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.921973861
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1375058609
Short name T339
Test name
Test status
Simulation time 403495674 ps
CPU time 2.3 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:35 PM PST 24
Peak memory 196976 kb
Host smart-6554a4d7-5f9a-4fd9-b616-ad7e96f9c822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375058609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1375058609
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.377447302
Short name T208
Test name
Test status
Simulation time 74668047 ps
CPU time 0.98 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 196512 kb
Host smart-6499221c-9af6-4d14-bfcf-293cad8169e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377447302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.377447302
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.733376686
Short name T574
Test name
Test status
Simulation time 49890384 ps
CPU time 1.05 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 196572 kb
Host smart-bafddab6-50bc-46f3-add9-d0fa9cbda5af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733376686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.733376686
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3115816543
Short name T361
Test name
Test status
Simulation time 240870382 ps
CPU time 4.25 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:36 PM PST 24
Peak memory 198044 kb
Host smart-7469d46f-0edc-4136-8161-3ae91b0c4f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115816543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3115816543
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2907621468
Short name T393
Test name
Test status
Simulation time 184127728 ps
CPU time 1.28 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 196672 kb
Host smart-e3cb6d2e-501a-49db-ba7d-aae565df4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907621468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2907621468
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1749598702
Short name T183
Test name
Test status
Simulation time 24455189 ps
CPU time 0.76 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 195192 kb
Host smart-913ecc49-c447-499d-9102-694d6d560aaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749598702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1749598702
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1314831110
Short name T127
Test name
Test status
Simulation time 16436786500 ps
CPU time 225.11 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:48:13 PM PST 24
Peak memory 198164 kb
Host smart-bb3d3e80-95a8-4775-9cfb-49d89414ed6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314831110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1314831110
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2134931835
Short name T613
Test name
Test status
Simulation time 107046749843 ps
CPU time 1610.11 seconds
Started Feb 25 01:44:27 PM PST 24
Finished Feb 25 02:11:18 PM PST 24
Peak memory 198376 kb
Host smart-c1e94494-cc77-4221-a0a9-8f6aecb50c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2134931835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2134931835
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3106995021
Short name T188
Test name
Test status
Simulation time 13096959 ps
CPU time 0.59 seconds
Started Feb 25 01:43:31 PM PST 24
Finished Feb 25 01:43:31 PM PST 24
Peak memory 194560 kb
Host smart-418513cc-5226-425e-a654-84b1b790b79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106995021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3106995021
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1930835624
Short name T20
Test name
Test status
Simulation time 37357219 ps
CPU time 0.8 seconds
Started Feb 25 01:43:23 PM PST 24
Finished Feb 25 01:43:24 PM PST 24
Peak memory 195920 kb
Host smart-38ab8418-5911-40d5-8dfc-e85156dd13e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930835624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1930835624
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.799910951
Short name T399
Test name
Test status
Simulation time 4449905578 ps
CPU time 19.64 seconds
Started Feb 25 01:43:19 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 198088 kb
Host smart-150541d7-07bd-4e04-b1b6-e1d7e2a8120f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799910951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.799910951
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2823971346
Short name T336
Test name
Test status
Simulation time 173384852 ps
CPU time 0.77 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 195836 kb
Host smart-320af1a4-a9bd-4380-8114-4e6279e00804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823971346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2823971346
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3953976254
Short name T486
Test name
Test status
Simulation time 62504566 ps
CPU time 0.7 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 194928 kb
Host smart-6083166c-f28c-46f8-9121-cddcfb9b9579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953976254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3953976254
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1807154327
Short name T552
Test name
Test status
Simulation time 166193230 ps
CPU time 3.53 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:22 PM PST 24
Peak memory 196552 kb
Host smart-94bbe810-0620-461f-a463-69593c6ec457
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807154327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1807154327
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.473668961
Short name T184
Test name
Test status
Simulation time 198284838 ps
CPU time 2.48 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:20 PM PST 24
Peak memory 197148 kb
Host smart-a689c6b8-099d-45db-8bb0-6416cb204328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473668961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.473668961
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3741854399
Short name T167
Test name
Test status
Simulation time 25275867 ps
CPU time 0.88 seconds
Started Feb 25 01:43:20 PM PST 24
Finished Feb 25 01:43:21 PM PST 24
Peak memory 195484 kb
Host smart-c496e335-43b7-4b38-be50-b4102a9cbc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741854399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3741854399
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4257673198
Short name T305
Test name
Test status
Simulation time 32163561 ps
CPU time 1.11 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 196116 kb
Host smart-0caf023a-1914-4a3c-ab35-2e73a1dd62bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257673198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4257673198
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3942031371
Short name T693
Test name
Test status
Simulation time 84711694 ps
CPU time 2.09 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 198040 kb
Host smart-2ff4e8ed-2c50-41ff-b314-a8bc438a40c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942031371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3942031371
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3770448335
Short name T527
Test name
Test status
Simulation time 153507977 ps
CPU time 1.26 seconds
Started Feb 25 01:43:21 PM PST 24
Finished Feb 25 01:43:23 PM PST 24
Peak memory 195900 kb
Host smart-9e291b19-37d2-4cec-8ac6-f1785167a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770448335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3770448335
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2158248055
Short name T244
Test name
Test status
Simulation time 107850221 ps
CPU time 1 seconds
Started Feb 25 01:43:18 PM PST 24
Finished Feb 25 01:43:19 PM PST 24
Peak memory 195732 kb
Host smart-f14dc9c0-09d3-43ee-8eb0-7802346dea72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158248055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2158248055
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4269729950
Short name T538
Test name
Test status
Simulation time 17894840047 ps
CPU time 188.36 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 198192 kb
Host smart-a269cdc1-df78-45b5-bd76-c9bfa209b814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269729950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4269729950
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2773857806
Short name T287
Test name
Test status
Simulation time 14988087 ps
CPU time 0.58 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 193972 kb
Host smart-4f50c67a-83b2-4417-baf6-02617693d818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773857806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2773857806
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1599479155
Short name T150
Test name
Test status
Simulation time 371442122 ps
CPU time 0.7 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 194124 kb
Host smart-ce31d57e-d2e6-4eed-b19b-e16efd5dfb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599479155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1599479155
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3517972703
Short name T282
Test name
Test status
Simulation time 1925828872 ps
CPU time 16.31 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:49 PM PST 24
Peak memory 197040 kb
Host smart-f4f8fae8-0061-44b2-9fda-b363e952aef8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517972703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3517972703
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1372520413
Short name T129
Test name
Test status
Simulation time 73100151 ps
CPU time 0.64 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:29 PM PST 24
Peak memory 194564 kb
Host smart-1a488eae-5c47-4836-b5cb-35c9b88438ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372520413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1372520413
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4280038740
Short name T699
Test name
Test status
Simulation time 304013047 ps
CPU time 1.48 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:33 PM PST 24
Peak memory 196768 kb
Host smart-42763840-9e5f-4dbd-a2f9-02c689de65ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280038740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4280038740
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1289320518
Short name T374
Test name
Test status
Simulation time 31273404 ps
CPU time 1.41 seconds
Started Feb 25 01:44:28 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 196708 kb
Host smart-16e591a5-944c-4e12-b3b0-2cd718c19335
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289320518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1289320518
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1769746449
Short name T324
Test name
Test status
Simulation time 125053620 ps
CPU time 2.84 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:35 PM PST 24
Peak memory 198104 kb
Host smart-713dd12c-9f3a-4fa5-bc1d-84909855976c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769746449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1769746449
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.126741561
Short name T14
Test name
Test status
Simulation time 69715717 ps
CPU time 0.85 seconds
Started Feb 25 01:44:29 PM PST 24
Finished Feb 25 01:44:30 PM PST 24
Peak memory 197156 kb
Host smart-a7a6189f-e3e1-438f-adb7-279c131257d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126741561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.126741561
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3409816291
Short name T696
Test name
Test status
Simulation time 229783281 ps
CPU time 1.4 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:33 PM PST 24
Peak memory 198072 kb
Host smart-19f055bc-6935-4c69-99a4-a437826acc30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409816291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3409816291
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2519885916
Short name T649
Test name
Test status
Simulation time 125005718 ps
CPU time 2.38 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 198008 kb
Host smart-dffbe54c-c00d-483a-8a6d-00d348493efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519885916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2519885916
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2878392654
Short name T56
Test name
Test status
Simulation time 68199815 ps
CPU time 1.3 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:33 PM PST 24
Peak memory 196936 kb
Host smart-64e855dc-8b05-4251-8417-f2f38d84dd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878392654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2878392654
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2845755573
Short name T195
Test name
Test status
Simulation time 113794404 ps
CPU time 0.92 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:44:32 PM PST 24
Peak memory 196184 kb
Host smart-c085209d-9a99-4cee-ba38-f9800ae0c43b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845755573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2845755573
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1804091698
Short name T7
Test name
Test status
Simulation time 19373779343 ps
CPU time 37.62 seconds
Started Feb 25 01:44:31 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 198176 kb
Host smart-c24d4daa-1c37-40be-94c2-d455339e929e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804091698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1804091698
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3470778065
Short name T377
Test name
Test status
Simulation time 37274605 ps
CPU time 0.57 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 194584 kb
Host smart-63d29138-fe02-4ef2-9100-e0c746cb6417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470778065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3470778065
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3155575796
Short name T383
Test name
Test status
Simulation time 81022577 ps
CPU time 0.83 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 195552 kb
Host smart-46f0b9fd-84f8-4fe1-a3fe-e591966b23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155575796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3155575796
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.479624412
Short name T21
Test name
Test status
Simulation time 2011180748 ps
CPU time 18.81 seconds
Started Feb 25 01:44:41 PM PST 24
Finished Feb 25 01:45:00 PM PST 24
Peak memory 197040 kb
Host smart-87846451-c8b3-42b3-9c05-b183a9dc679a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479624412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.479624412
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2379568640
Short name T103
Test name
Test status
Simulation time 75526337 ps
CPU time 0.96 seconds
Started Feb 25 01:44:44 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 196376 kb
Host smart-ee3b9d64-e0d9-4587-a7af-50845f69205a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379568640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2379568640
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3862681015
Short name T68
Test name
Test status
Simulation time 229809645 ps
CPU time 1.28 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 196932 kb
Host smart-0fdddccd-cebf-4531-804b-b1a6e7c7b7fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862681015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3862681015
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.179892361
Short name T611
Test name
Test status
Simulation time 228953051 ps
CPU time 2.66 seconds
Started Feb 25 01:44:44 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 198160 kb
Host smart-a73d02ac-2841-407f-8ae5-5b4c4bdd77b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179892361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.179892361
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3372595363
Short name T355
Test name
Test status
Simulation time 81333800 ps
CPU time 2.54 seconds
Started Feb 25 01:44:39 PM PST 24
Finished Feb 25 01:44:42 PM PST 24
Peak memory 197336 kb
Host smart-638cbc1d-a9d6-449d-a152-5e6d23acc7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372595363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3372595363
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1567797244
Short name T118
Test name
Test status
Simulation time 30833027 ps
CPU time 1.11 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 195904 kb
Host smart-10e3d74b-6bf9-4f80-83e2-55774df176c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567797244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1567797244
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1453996651
Short name T510
Test name
Test status
Simulation time 113724837 ps
CPU time 1.25 seconds
Started Feb 25 01:44:44 PM PST 24
Finished Feb 25 01:44:45 PM PST 24
Peak memory 197212 kb
Host smart-31543be3-3258-4c03-8132-4c4700c25c54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453996651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1453996651
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2579358711
Short name T545
Test name
Test status
Simulation time 32567940 ps
CPU time 1.67 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:44 PM PST 24
Peak memory 197988 kb
Host smart-da21e8cf-192b-422b-b08c-28a252bed6be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579358711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2579358711
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2026871246
Short name T673
Test name
Test status
Simulation time 85323923 ps
CPU time 1.27 seconds
Started Feb 25 01:44:32 PM PST 24
Finished Feb 25 01:44:33 PM PST 24
Peak memory 197036 kb
Host smart-65311fc1-fdf8-4476-8990-7a52c621f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026871246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2026871246
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2217031342
Short name T666
Test name
Test status
Simulation time 208663891 ps
CPU time 1.13 seconds
Started Feb 25 01:44:30 PM PST 24
Finished Feb 25 01:44:31 PM PST 24
Peak memory 196552 kb
Host smart-ec1185d7-655a-4328-8165-a85292e946d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217031342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2217031342
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3958895226
Short name T460
Test name
Test status
Simulation time 20179558221 ps
CPU time 215.25 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:48:22 PM PST 24
Peak memory 198192 kb
Host smart-6c9ef6a1-662d-4cd7-9545-ccd7563fe206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958895226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3958895226
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.997362823
Short name T400
Test name
Test status
Simulation time 14691128 ps
CPU time 0.55 seconds
Started Feb 25 01:44:41 PM PST 24
Finished Feb 25 01:44:41 PM PST 24
Peak memory 193860 kb
Host smart-118aa499-0f84-4afe-b767-e18746ab67b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997362823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.997362823
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3564598081
Short name T179
Test name
Test status
Simulation time 82174004 ps
CPU time 0.82 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:44:48 PM PST 24
Peak memory 195144 kb
Host smart-48f02f7f-5f66-49d5-a606-84ef7473c3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564598081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3564598081
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2425298528
Short name T319
Test name
Test status
Simulation time 487182150 ps
CPU time 25.55 seconds
Started Feb 25 01:44:41 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 196988 kb
Host smart-baaebfab-76c8-4d35-a325-625ff214dd7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425298528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2425298528
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.84890782
Short name T433
Test name
Test status
Simulation time 756174394 ps
CPU time 1.07 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:44 PM PST 24
Peak memory 197824 kb
Host smart-1c543321-529b-4b1d-935c-067692e84c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84890782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.84890782
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3099576705
Short name T29
Test name
Test status
Simulation time 101553541 ps
CPU time 1.51 seconds
Started Feb 25 01:44:37 PM PST 24
Finished Feb 25 01:44:39 PM PST 24
Peak memory 197188 kb
Host smart-281af132-d5dc-460f-bdfe-751818de37d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099576705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3099576705
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2877163989
Short name T72
Test name
Test status
Simulation time 28630421 ps
CPU time 1.37 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:44 PM PST 24
Peak memory 196756 kb
Host smart-797c3007-06b9-4cd3-80b8-2c9dd3bf543f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877163989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2877163989
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.728032342
Short name T119
Test name
Test status
Simulation time 57925943 ps
CPU time 1.37 seconds
Started Feb 25 01:44:39 PM PST 24
Finished Feb 25 01:44:40 PM PST 24
Peak memory 196852 kb
Host smart-5cd0ef51-6233-45f3-8307-7c6000c82dc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728032342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
728032342
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1166324488
Short name T359
Test name
Test status
Simulation time 240377356 ps
CPU time 1.12 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 195952 kb
Host smart-f10bb7f2-be05-4fa2-972d-4e59e76691ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166324488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1166324488
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2449623349
Short name T627
Test name
Test status
Simulation time 20301010 ps
CPU time 0.69 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 195064 kb
Host smart-cf1ffdcb-4fce-40bb-8d8f-dc4d6065e6b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449623349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2449623349
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.95624815
Short name T170
Test name
Test status
Simulation time 181327760 ps
CPU time 4.1 seconds
Started Feb 25 01:44:39 PM PST 24
Finished Feb 25 01:44:44 PM PST 24
Peak memory 198040 kb
Host smart-079ceda7-199c-497e-9ef2-3afbffa85f3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95624815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.95624815
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2370101176
Short name T391
Test name
Test status
Simulation time 147608287 ps
CPU time 1.34 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 196964 kb
Host smart-c43461b5-a5f0-4390-b20d-2831db69f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370101176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2370101176
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2451251540
Short name T210
Test name
Test status
Simulation time 33314915 ps
CPU time 1.07 seconds
Started Feb 25 01:44:41 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 195516 kb
Host smart-038e098a-2f1c-407b-8b28-bf0cd1622acc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451251540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2451251540
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.365788770
Short name T461
Test name
Test status
Simulation time 12369702474 ps
CPU time 170.25 seconds
Started Feb 25 01:44:43 PM PST 24
Finished Feb 25 01:47:33 PM PST 24
Peak memory 198196 kb
Host smart-54833d88-84ef-4d52-bcf2-e175ccda14bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365788770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.365788770
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2770720225
Short name T60
Test name
Test status
Simulation time 257526879384 ps
CPU time 1418.35 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 02:08:24 PM PST 24
Peak memory 198448 kb
Host smart-6efceda6-b619-4f11-97d9-9412a4e0227a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2770720225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2770720225
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1738283827
Short name T682
Test name
Test status
Simulation time 14454339 ps
CPU time 0.6 seconds
Started Feb 25 01:44:38 PM PST 24
Finished Feb 25 01:44:39 PM PST 24
Peak memory 194080 kb
Host smart-9cccab7c-5aec-47a1-b37a-7a3f74e1270f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738283827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1738283827
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1576607070
Short name T463
Test name
Test status
Simulation time 270861024 ps
CPU time 1.04 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:44:49 PM PST 24
Peak memory 196032 kb
Host smart-a621eaff-ee74-4ebc-a3d3-ce52539c1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576607070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1576607070
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.59766644
Short name T531
Test name
Test status
Simulation time 1320654043 ps
CPU time 23.26 seconds
Started Feb 25 01:44:44 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 198036 kb
Host smart-4e0e74f4-844a-4d09-ab19-f7065be3315e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59766644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stress
.59766644
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3420837703
Short name T292
Test name
Test status
Simulation time 263206374 ps
CPU time 0.9 seconds
Started Feb 25 01:44:38 PM PST 24
Finished Feb 25 01:44:39 PM PST 24
Peak memory 196132 kb
Host smart-845a608c-3bec-44a1-a0a1-9d2aa675f321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420837703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3420837703
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3009254096
Short name T632
Test name
Test status
Simulation time 21485822 ps
CPU time 0.77 seconds
Started Feb 25 01:44:44 PM PST 24
Finished Feb 25 01:44:45 PM PST 24
Peak memory 195560 kb
Host smart-abd7f33f-5e27-4ec0-960e-eac17587e692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009254096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3009254096
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3352828562
Short name T448
Test name
Test status
Simulation time 55543733 ps
CPU time 2.27 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 198032 kb
Host smart-cc19dca1-7ddc-4ecb-a9a0-dcea6836b4e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352828562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3352828562
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1826845375
Short name T639
Test name
Test status
Simulation time 55358115 ps
CPU time 1.53 seconds
Started Feb 25 01:44:41 PM PST 24
Finished Feb 25 01:44:42 PM PST 24
Peak memory 196584 kb
Host smart-18a96945-3e2c-4818-905e-1ed54f76e978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826845375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1826845375
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.581344392
Short name T165
Test name
Test status
Simulation time 31093555 ps
CPU time 0.89 seconds
Started Feb 25 01:44:42 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 195704 kb
Host smart-3c035f57-2419-440c-b48b-e9b653396069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581344392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.581344392
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3510307138
Short name T672
Test name
Test status
Simulation time 252201257 ps
CPU time 0.7 seconds
Started Feb 25 01:44:40 PM PST 24
Finished Feb 25 01:44:41 PM PST 24
Peak memory 195340 kb
Host smart-7d2d42e3-22d2-40af-9a31-7ac7e71d761e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510307138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3510307138
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1488007239
Short name T532
Test name
Test status
Simulation time 48174568 ps
CPU time 2.07 seconds
Started Feb 25 01:44:46 PM PST 24
Finished Feb 25 01:44:49 PM PST 24
Peak memory 197996 kb
Host smart-7d524a4a-8981-4bf0-8412-11bb49833189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488007239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1488007239
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1510178914
Short name T231
Test name
Test status
Simulation time 89041101 ps
CPU time 1.31 seconds
Started Feb 25 01:44:46 PM PST 24
Finished Feb 25 01:44:48 PM PST 24
Peak memory 195936 kb
Host smart-5ffba0ca-22a7-493b-8cba-6878fe12c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510178914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1510178914
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1969287680
Short name T695
Test name
Test status
Simulation time 119261768 ps
CPU time 1.35 seconds
Started Feb 25 01:44:37 PM PST 24
Finished Feb 25 01:44:38 PM PST 24
Peak memory 195596 kb
Host smart-04c260d2-6d5c-41ca-b6ae-8a6a4f385f4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969287680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1969287680
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.61484321
Short name T205
Test name
Test status
Simulation time 2782452378 ps
CPU time 69.61 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:45:57 PM PST 24
Peak memory 198156 kb
Host smart-d1b49570-d4a3-4d29-b8f9-485042537dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61484321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gp
io_stress_all.61484321
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2593441143
Short name T474
Test name
Test status
Simulation time 18074470 ps
CPU time 0.6 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 194140 kb
Host smart-a4045939-43e3-40fe-8429-e877da062c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593441143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2593441143
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1563014190
Short name T126
Test name
Test status
Simulation time 135396838 ps
CPU time 0.87 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:44:48 PM PST 24
Peak memory 195904 kb
Host smart-dbd1a4c9-8251-463a-ab79-4dc44ffbfd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563014190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1563014190
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1110467819
Short name T396
Test name
Test status
Simulation time 190633752 ps
CPU time 3.8 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 196288 kb
Host smart-52c595fe-777c-4987-9760-ddc87ce2014f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110467819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1110467819
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3536562217
Short name T577
Test name
Test status
Simulation time 164282483 ps
CPU time 0.83 seconds
Started Feb 25 01:44:46 PM PST 24
Finished Feb 25 01:44:48 PM PST 24
Peak memory 196612 kb
Host smart-2caedd17-8d35-415f-a5b2-8fa512c5648e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536562217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3536562217
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.4010738238
Short name T443
Test name
Test status
Simulation time 21929444 ps
CPU time 0.74 seconds
Started Feb 25 01:44:45 PM PST 24
Finished Feb 25 01:44:45 PM PST 24
Peak memory 196220 kb
Host smart-7f8879ae-ef62-4055-8231-a73fd98b22ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010738238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.4010738238
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2601237399
Short name T533
Test name
Test status
Simulation time 78146658 ps
CPU time 2.97 seconds
Started Feb 25 01:44:43 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 198168 kb
Host smart-e80096d0-1720-4329-823c-9281889dc685
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601237399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2601237399
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.613805813
Short name T166
Test name
Test status
Simulation time 105126492 ps
CPU time 2.56 seconds
Started Feb 25 01:44:37 PM PST 24
Finished Feb 25 01:44:39 PM PST 24
Peak memory 196844 kb
Host smart-dc333a08-f1cf-4fb8-b054-1a4ee6a8c643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613805813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
613805813
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1410775187
Short name T279
Test name
Test status
Simulation time 94560118 ps
CPU time 0.94 seconds
Started Feb 25 01:44:37 PM PST 24
Finished Feb 25 01:44:38 PM PST 24
Peak memory 196008 kb
Host smart-f89a63db-31ac-446e-a92e-85c6327286c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410775187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1410775187
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.952202913
Short name T438
Test name
Test status
Simulation time 76252000 ps
CPU time 1.32 seconds
Started Feb 25 01:44:39 PM PST 24
Finished Feb 25 01:44:40 PM PST 24
Peak memory 196648 kb
Host smart-84631ebc-6687-46b1-ab4a-d22e3ffe0dc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952202913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.952202913
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1904264348
Short name T369
Test name
Test status
Simulation time 93047768 ps
CPU time 2.97 seconds
Started Feb 25 01:44:47 PM PST 24
Finished Feb 25 01:44:50 PM PST 24
Peak memory 198000 kb
Host smart-c74667cf-9359-4d04-9b38-02121ee8b51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904264348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1904264348
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3370283218
Short name T489
Test name
Test status
Simulation time 35029188 ps
CPU time 0.98 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 195452 kb
Host smart-8943286d-0dec-42d2-bee7-3685c699942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370283218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3370283218
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3943068151
Short name T464
Test name
Test status
Simulation time 89583556 ps
CPU time 0.75 seconds
Started Feb 25 01:44:40 PM PST 24
Finished Feb 25 01:44:40 PM PST 24
Peak memory 195940 kb
Host smart-8b876483-1b19-4d06-9106-75ee4ac4df3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943068151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3943068151
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.509845393
Short name T503
Test name
Test status
Simulation time 5354488063 ps
CPU time 138.19 seconds
Started Feb 25 01:44:43 PM PST 24
Finished Feb 25 01:47:01 PM PST 24
Peak memory 198204 kb
Host smart-c4a3aa95-f205-4091-a9c0-2688dfcdd84e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509845393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.509845393
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1007021680
Short name T670
Test name
Test status
Simulation time 28492855 ps
CPU time 0.56 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 193868 kb
Host smart-71e6a525-5216-49ae-bb69-1acc8d5a0cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007021680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1007021680
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2769231257
Short name T241
Test name
Test status
Simulation time 31211668 ps
CPU time 0.88 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 197104 kb
Host smart-9ec891ac-0d56-4ea4-a668-f6d3df972b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769231257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2769231257
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1188579504
Short name T556
Test name
Test status
Simulation time 1475045766 ps
CPU time 26.87 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 197060 kb
Host smart-e8cc8ba7-ea48-4157-8b70-0f70acd4da37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188579504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1188579504
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2369863281
Short name T494
Test name
Test status
Simulation time 262760891 ps
CPU time 1.09 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196524 kb
Host smart-809bd337-626a-4ce5-8f5b-06b369e7eb66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369863281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2369863281
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.4120710478
Short name T146
Test name
Test status
Simulation time 100806318 ps
CPU time 0.94 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196184 kb
Host smart-751e1d87-5434-4269-af6c-c8c352492be4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120710478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.4120710478
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3765516262
Short name T291
Test name
Test status
Simulation time 51627611 ps
CPU time 2.08 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 198096 kb
Host smart-9318ca23-bf2f-49b8-9969-4cf4ab654237
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765516262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3765516262
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2063430723
Short name T591
Test name
Test status
Simulation time 495294939 ps
CPU time 3.67 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 197224 kb
Host smart-b4c6d707-f5d4-4af6-8c48-7e7d41496259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063430723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2063430723
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.938009750
Short name T295
Test name
Test status
Simulation time 36365528 ps
CPU time 1.18 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196136 kb
Host smart-7f7c36f7-fbe0-424d-b35a-7946efcc5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938009750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.938009750
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.825017842
Short name T207
Test name
Test status
Simulation time 29918149 ps
CPU time 0.78 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 195500 kb
Host smart-d967cdf0-9575-4f80-892f-2f19cad494bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825017842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.825017842
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2664764692
Short name T251
Test name
Test status
Simulation time 107112452 ps
CPU time 2.11 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 198084 kb
Host smart-9cb220ac-fa09-4200-a716-40c6a186acac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664764692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2664764692
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2105298688
Short name T277
Test name
Test status
Simulation time 44247719 ps
CPU time 1.27 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 196312 kb
Host smart-0ee1b673-8657-463f-9c26-a90651decaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105298688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2105298688
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3623127766
Short name T630
Test name
Test status
Simulation time 34472488 ps
CPU time 0.92 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196344 kb
Host smart-65812b62-57ff-416b-984e-ce6959662f87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623127766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3623127766
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3373136024
Short name T559
Test name
Test status
Simulation time 27179988915 ps
CPU time 167.66 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:47:41 PM PST 24
Peak memory 198244 kb
Host smart-6ee6911f-b4e7-4f2f-a958-591db86123bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373136024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3373136024
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.383960357
Short name T409
Test name
Test status
Simulation time 13685002 ps
CPU time 0.66 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 195656 kb
Host smart-5f3a1d96-6414-4f76-afb6-692e100fcd8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383960357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.383960357
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2535250471
Short name T476
Test name
Test status
Simulation time 16340776 ps
CPU time 0.67 seconds
Started Feb 25 01:44:59 PM PST 24
Finished Feb 25 01:45:00 PM PST 24
Peak memory 194288 kb
Host smart-a09b09cc-9a61-4426-899e-8ea1bc4ee919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535250471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2535250471
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1418011974
Short name T606
Test name
Test status
Simulation time 876148082 ps
CPU time 8.78 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 195636 kb
Host smart-bf502321-9285-4509-aaa4-399d532022bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418011974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1418011974
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.718677402
Short name T481
Test name
Test status
Simulation time 67953384 ps
CPU time 0.95 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 197724 kb
Host smart-4bc73a9c-5009-4daf-9d0a-77f897a8368c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718677402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.718677402
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.141857920
Short name T551
Test name
Test status
Simulation time 69328105 ps
CPU time 0.76 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 195436 kb
Host smart-0726f815-abba-40aa-b623-a18797b3b814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141857920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.141857920
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4003591987
Short name T549
Test name
Test status
Simulation time 360323682 ps
CPU time 3.46 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 198132 kb
Host smart-bd59d1c9-3d33-4b13-9939-2d69f409458e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003591987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4003591987
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3769218029
Short name T372
Test name
Test status
Simulation time 48855059 ps
CPU time 1.61 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 195744 kb
Host smart-a4fd4209-08e8-45f5-8be0-fea8fb29eba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769218029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3769218029
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1180895088
Short name T249
Test name
Test status
Simulation time 30938572 ps
CPU time 0.79 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:54 PM PST 24
Peak memory 195504 kb
Host smart-b67d30fd-7ffb-4301-91ad-21939b90d9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180895088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1180895088
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1640653267
Short name T144
Test name
Test status
Simulation time 738277269 ps
CPU time 1.31 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 197132 kb
Host smart-6e7e1978-4584-4fe5-9aac-dbf5382e48ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640653267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1640653267
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1335924182
Short name T262
Test name
Test status
Simulation time 115409764 ps
CPU time 2.02 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:44:58 PM PST 24
Peak memory 198088 kb
Host smart-8d63943b-9abe-4969-8ec3-73f4eb81f62a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335924182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1335924182
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3101186020
Short name T11
Test name
Test status
Simulation time 45204558 ps
CPU time 1.28 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196792 kb
Host smart-db26f591-7bdf-4a6a-97c1-499075be143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101186020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3101186020
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3312231967
Short name T360
Test name
Test status
Simulation time 46531855 ps
CPU time 0.94 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 196200 kb
Host smart-31642093-7edd-42fb-9cd8-694f72908db9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312231967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3312231967
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3494683971
Short name T8
Test name
Test status
Simulation time 15999509086 ps
CPU time 191.37 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:48:04 PM PST 24
Peak memory 198156 kb
Host smart-ac1ac957-77d4-4434-93d4-7fa1d2c3f899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494683971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3494683971
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.242436109
Short name T284
Test name
Test status
Simulation time 19881413 ps
CPU time 0.61 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 194820 kb
Host smart-e9f43aaa-1939-432b-8230-1b9d5c641ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242436109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.242436109
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3116077819
Short name T145
Test name
Test status
Simulation time 14809415 ps
CPU time 0.65 seconds
Started Feb 25 01:44:53 PM PST 24
Finished Feb 25 01:44:54 PM PST 24
Peak memory 194712 kb
Host smart-3353ae29-4aa7-4197-abf8-6d73d26dae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116077819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3116077819
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.917365628
Short name T334
Test name
Test status
Simulation time 685877357 ps
CPU time 6.4 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:45:01 PM PST 24
Peak memory 196844 kb
Host smart-d8a5e0d6-d23b-4273-9dd8-54f61f054e51
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917365628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.917365628
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1107357497
Short name T395
Test name
Test status
Simulation time 496206372 ps
CPU time 1 seconds
Started Feb 25 01:44:57 PM PST 24
Finished Feb 25 01:44:58 PM PST 24
Peak memory 197904 kb
Host smart-6f2cc79a-d291-4778-8391-0bd225f8bb10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107357497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1107357497
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.491548018
Short name T285
Test name
Test status
Simulation time 523341239 ps
CPU time 1.1 seconds
Started Feb 25 01:44:58 PM PST 24
Finished Feb 25 01:44:59 PM PST 24
Peak memory 196156 kb
Host smart-b977d0bb-533b-4ec1-8619-c68efdc8616f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491548018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.491548018
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4155785339
Short name T314
Test name
Test status
Simulation time 46768458 ps
CPU time 1.03 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 196236 kb
Host smart-b9babd9a-0349-4634-95d4-ba7fa91524b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155785339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4155785339
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1879510174
Short name T624
Test name
Test status
Simulation time 126020538 ps
CPU time 0.89 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 194552 kb
Host smart-ac28d784-02bd-4636-97c3-f631996c040b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879510174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1879510174
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3514402213
Short name T659
Test name
Test status
Simulation time 112446188 ps
CPU time 1.2 seconds
Started Feb 25 01:44:57 PM PST 24
Finished Feb 25 01:44:58 PM PST 24
Peak memory 198132 kb
Host smart-b56188fb-b011-479c-884d-e0c0a1d4755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514402213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3514402213
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1070667195
Short name T457
Test name
Test status
Simulation time 32645261 ps
CPU time 0.67 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 194228 kb
Host smart-0cbe2543-3ca7-433a-bcf2-8b63e629241a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070667195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1070667195
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2749024516
Short name T3
Test name
Test status
Simulation time 84180299 ps
CPU time 1.06 seconds
Started Feb 25 01:44:55 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 196600 kb
Host smart-7dd3a2be-1425-4db4-9846-1aa199f3ba44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749024516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2749024516
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2494236508
Short name T259
Test name
Test status
Simulation time 138702485 ps
CPU time 1.23 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 195580 kb
Host smart-0223c27a-1fcf-40d6-93c2-52b4ec3dfce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494236508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2494236508
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1063227407
Short name T270
Test name
Test status
Simulation time 160603301 ps
CPU time 1.38 seconds
Started Feb 25 01:44:57 PM PST 24
Finished Feb 25 01:44:58 PM PST 24
Peak memory 196752 kb
Host smart-a5164689-9b53-4f9a-81ed-955beda81c16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063227407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1063227407
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.525253990
Short name T548
Test name
Test status
Simulation time 10125082836 ps
CPU time 133.31 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:47:09 PM PST 24
Peak memory 198196 kb
Host smart-fc435511-8bef-42aa-8a20-7894db19a6e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525253990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.525253990
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4278787509
Short name T13
Test name
Test status
Simulation time 95258310861 ps
CPU time 1955.12 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 02:17:29 PM PST 24
Peak memory 198268 kb
Host smart-118e75f8-6636-412c-88c3-16fb89ab8c25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4278787509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4278787509
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.402978724
Short name T484
Test name
Test status
Simulation time 44488744 ps
CPU time 0.6 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 194832 kb
Host smart-b2473f6e-7d36-45c4-86e6-b947512ea4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402978724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.402978724
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2939015137
Short name T23
Test name
Test status
Simulation time 21762720 ps
CPU time 0.77 seconds
Started Feb 25 01:45:05 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 195404 kb
Host smart-320979f5-5dfc-4d8b-82f6-bfdcc253f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939015137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2939015137
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.833638206
Short name T493
Test name
Test status
Simulation time 875729333 ps
CPU time 22.05 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:45:16 PM PST 24
Peak memory 196844 kb
Host smart-4105ae74-c128-4212-9f2e-4a4b1d2ca418
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833638206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.833638206
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3370130308
Short name T429
Test name
Test status
Simulation time 20117054 ps
CPU time 0.62 seconds
Started Feb 25 01:45:00 PM PST 24
Finished Feb 25 01:45:01 PM PST 24
Peak memory 194284 kb
Host smart-0d1ebfc4-d333-48e1-82ac-9f3e9d278dd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370130308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3370130308
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1087625766
Short name T589
Test name
Test status
Simulation time 115305916 ps
CPU time 0.72 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 194380 kb
Host smart-6039738a-9757-44ee-81fa-e512d69a8f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087625766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1087625766
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1959575465
Short name T547
Test name
Test status
Simulation time 333348580 ps
CPU time 3.32 seconds
Started Feb 25 01:44:57 PM PST 24
Finished Feb 25 01:45:00 PM PST 24
Peak memory 198148 kb
Host smart-55ebab3c-b733-4fa7-8dcf-fcb0417fa04c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959575465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1959575465
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1014716528
Short name T147
Test name
Test status
Simulation time 167738935 ps
CPU time 1.13 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 195456 kb
Host smart-7528e1f0-86f7-4c70-945a-fb8529ed86cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014716528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1014716528
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4119280461
Short name T243
Test name
Test status
Simulation time 194585029 ps
CPU time 1.15 seconds
Started Feb 25 01:44:54 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 197164 kb
Host smart-2275d1b6-b1f9-4e8a-98e6-b78d77a5c092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119280461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4119280461
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1778129463
Short name T272
Test name
Test status
Simulation time 49376049 ps
CPU time 0.84 seconds
Started Feb 25 01:45:02 PM PST 24
Finished Feb 25 01:45:02 PM PST 24
Peak memory 196152 kb
Host smart-c42f9952-8fa0-40bc-977b-14b64c6d3e87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778129463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1778129463
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4257305415
Short name T246
Test name
Test status
Simulation time 1488349555 ps
CPU time 5.13 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:15 PM PST 24
Peak memory 198044 kb
Host smart-2cc96e09-29e0-4e96-b6ef-89b224e10e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257305415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4257305415
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1682252891
Short name T499
Test name
Test status
Simulation time 116606387 ps
CPU time 0.77 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 195268 kb
Host smart-7e6e71e3-2179-4e3a-900d-68355f5c318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682252891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1682252891
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3882330863
Short name T198
Test name
Test status
Simulation time 77911584 ps
CPU time 1.4 seconds
Started Feb 25 01:44:56 PM PST 24
Finished Feb 25 01:44:57 PM PST 24
Peak memory 198056 kb
Host smart-5ea769d3-d0c5-4478-8acf-15342225dbd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882330863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3882330863
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3182665817
Short name T478
Test name
Test status
Simulation time 3511898362 ps
CPU time 38.76 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 198192 kb
Host smart-2872ad03-268a-4572-9d08-ce50d6934c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182665817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3182665817
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1124559935
Short name T519
Test name
Test status
Simulation time 43571112863 ps
CPU time 719.06 seconds
Started Feb 25 01:45:02 PM PST 24
Finished Feb 25 01:57:01 PM PST 24
Peak memory 198272 kb
Host smart-5c19d7ee-f0e7-48b1-87d9-f727ec58af2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1124559935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1124559935
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.145465200
Short name T517
Test name
Test status
Simulation time 23268915 ps
CPU time 0.61 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 193884 kb
Host smart-a253bf57-c8b3-4d1f-80bc-17a70537c8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145465200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.145465200
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.582608723
Short name T194
Test name
Test status
Simulation time 405878198 ps
CPU time 0.78 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 195236 kb
Host smart-fae4ab3d-2aa6-423b-aa58-d9bf87e134a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582608723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.582608723
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3851011689
Short name T304
Test name
Test status
Simulation time 1841995648 ps
CPU time 14.77 seconds
Started Feb 25 01:45:01 PM PST 24
Finished Feb 25 01:45:16 PM PST 24
Peak memory 196860 kb
Host smart-7554c878-c239-4297-be36-40cff23002f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851011689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3851011689
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.865383336
Short name T691
Test name
Test status
Simulation time 69212560 ps
CPU time 0.67 seconds
Started Feb 25 01:45:01 PM PST 24
Finished Feb 25 01:45:02 PM PST 24
Peak memory 195252 kb
Host smart-3d0a53ad-f7af-4904-88e8-3e9110e6f9ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865383336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.865383336
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4166190919
Short name T475
Test name
Test status
Simulation time 75715248 ps
CPU time 0.79 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 195488 kb
Host smart-488ccfb4-58db-4243-8375-62684d0fd736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166190919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4166190919
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1727143973
Short name T542
Test name
Test status
Simulation time 234672379 ps
CPU time 2.68 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:12 PM PST 24
Peak memory 198196 kb
Host smart-5987da37-2073-4fc8-9edb-a3b3735eb3e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727143973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1727143973
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2896775688
Short name T454
Test name
Test status
Simulation time 336364835 ps
CPU time 2.61 seconds
Started Feb 25 01:45:00 PM PST 24
Finished Feb 25 01:45:03 PM PST 24
Peak memory 197300 kb
Host smart-e6256ec4-3644-4969-9859-d2b8a148e5db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896775688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2896775688
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4221216780
Short name T679
Test name
Test status
Simulation time 84509492 ps
CPU time 1.18 seconds
Started Feb 25 01:45:13 PM PST 24
Finished Feb 25 01:45:15 PM PST 24
Peak memory 196992 kb
Host smart-4f5167af-1a8f-4d09-bab0-73dec0f12dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221216780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4221216780
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3170521730
Short name T626
Test name
Test status
Simulation time 47365770 ps
CPU time 1.08 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 195932 kb
Host smart-1054acb3-aab0-4ec6-b575-6c1c1b2217b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170521730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3170521730
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1288117189
Short name T312
Test name
Test status
Simulation time 331209512 ps
CPU time 4.47 seconds
Started Feb 25 01:45:13 PM PST 24
Finished Feb 25 01:45:18 PM PST 24
Peak memory 197856 kb
Host smart-272abce7-bfd1-46a2-ada6-f26dc9c09934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288117189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1288117189
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1537075477
Short name T681
Test name
Test status
Simulation time 1131405970 ps
CPU time 1.15 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 195944 kb
Host smart-f35dc63b-b49f-43ce-b298-c026bfdc6869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537075477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1537075477
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.179712120
Short name T498
Test name
Test status
Simulation time 66265244 ps
CPU time 1.08 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 196596 kb
Host smart-565122b4-c0d6-46e3-8535-50302a4687ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179712120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.179712120
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1081583683
Short name T555
Test name
Test status
Simulation time 101967365254 ps
CPU time 192.68 seconds
Started Feb 25 01:45:13 PM PST 24
Finished Feb 25 01:48:26 PM PST 24
Peak memory 197984 kb
Host smart-32b13302-eb67-4bc2-992c-e198cf16e282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081583683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1081583683
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3254867463
Short name T245
Test name
Test status
Simulation time 15094115 ps
CPU time 0.55 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 194644 kb
Host smart-62e23cf6-5dd8-4d79-8180-3407a020a69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254867463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3254867463
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.907576839
Short name T52
Test name
Test status
Simulation time 209903845 ps
CPU time 0.85 seconds
Started Feb 25 01:43:31 PM PST 24
Finished Feb 25 01:43:32 PM PST 24
Peak memory 195488 kb
Host smart-829fa6b9-73b6-4ded-aee0-f84e1651150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907576839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.907576839
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.480348976
Short name T446
Test name
Test status
Simulation time 917025017 ps
CPU time 23.25 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 197000 kb
Host smart-1fbd4949-931c-4ba9-9b68-490162b44f54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480348976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.480348976
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1965104305
Short name T260
Test name
Test status
Simulation time 47228515 ps
CPU time 0.87 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 195984 kb
Host smart-0a0ab914-5710-4204-a006-3bea4a79b664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965104305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1965104305
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1794125843
Short name T408
Test name
Test status
Simulation time 83639035 ps
CPU time 1.24 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 196212 kb
Host smart-6e9cfcff-a65b-4f41-a639-f950bdbc3ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794125843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1794125843
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1122069745
Short name T684
Test name
Test status
Simulation time 68214166 ps
CPU time 2.66 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 198108 kb
Host smart-eac1e2e6-77dc-4c2b-b616-de62454e3d4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122069745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1122069745
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2737204322
Short name T161
Test name
Test status
Simulation time 33092261 ps
CPU time 0.98 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 195552 kb
Host smart-88b0d918-c7b8-44ff-b7ea-d444402c22d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737204322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2737204322
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3788741741
Short name T131
Test name
Test status
Simulation time 71710420 ps
CPU time 1.24 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 198060 kb
Host smart-e28a4771-98d1-41e7-b8de-0c478e6db177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788741741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3788741741
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.427321355
Short name T651
Test name
Test status
Simulation time 25972534 ps
CPU time 0.7 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 195348 kb
Host smart-d670d97b-4b5f-40d1-ba6d-acb3843ff007
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427321355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.427321355
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4077850512
Short name T160
Test name
Test status
Simulation time 56044005 ps
CPU time 2.6 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 198016 kb
Host smart-8c568c91-574c-473b-ae97-0ca0cc6fb993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077850512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4077850512
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.395070264
Short name T49
Test name
Test status
Simulation time 159486837 ps
CPU time 0.76 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 213772 kb
Host smart-16884dba-7484-4920-9383-efc8945083ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395070264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.395070264
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1960538986
Short name T610
Test name
Test status
Simulation time 502469142 ps
CPU time 1.13 seconds
Started Feb 25 01:43:33 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 196364 kb
Host smart-1131db36-1be4-47c3-a8c3-3296f9bc3bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960538986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1960538986
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.205106361
Short name T192
Test name
Test status
Simulation time 97774158 ps
CPU time 1.15 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 195612 kb
Host smart-59831a15-7069-42cf-8a09-0ab79c658212
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205106361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.205106361
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1527312585
Short name T352
Test name
Test status
Simulation time 6941340024 ps
CPU time 172.89 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:46:28 PM PST 24
Peak memory 198188 kb
Host smart-d69b7136-61ae-4eb2-9663-5140f623da19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527312585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1527312585
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3218632286
Short name T480
Test name
Test status
Simulation time 35982080 ps
CPU time 0.56 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 193720 kb
Host smart-4a72a9e5-715b-47a5-8be5-5d78705c2fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218632286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3218632286
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4260899150
Short name T343
Test name
Test status
Simulation time 35256427 ps
CPU time 0.73 seconds
Started Feb 25 01:45:02 PM PST 24
Finished Feb 25 01:45:03 PM PST 24
Peak memory 195220 kb
Host smart-92f3fad2-1e64-4cb2-8bcb-1478bebd7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260899150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4260899150
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2282628663
Short name T186
Test name
Test status
Simulation time 1507899118 ps
CPU time 18.7 seconds
Started Feb 25 01:45:02 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 198080 kb
Host smart-9a5b220d-6a67-4c7d-841a-80a2e5b4b7b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282628663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2282628663
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4248667700
Short name T16
Test name
Test status
Simulation time 161863437 ps
CPU time 0.99 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 197300 kb
Host smart-71ae24d6-f8ec-4da8-afa3-b91c2af15c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248667700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4248667700
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2589295789
Short name T315
Test name
Test status
Simulation time 132179442 ps
CPU time 0.78 seconds
Started Feb 25 01:45:10 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 196280 kb
Host smart-d4a797da-6262-4a94-9afa-d9e3201c721d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589295789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2589295789
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1448794199
Short name T201
Test name
Test status
Simulation time 58134867 ps
CPU time 2.4 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 198156 kb
Host smart-81ca6ab9-e36a-4f8a-a928-507dde9e1f33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448794199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1448794199
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3204714862
Short name T473
Test name
Test status
Simulation time 183934817 ps
CPU time 2.22 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 196976 kb
Host smart-f1c1b556-d8b7-44f1-a1b1-1d05bd141c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204714862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3204714862
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1648599222
Short name T456
Test name
Test status
Simulation time 70285121 ps
CPU time 1.13 seconds
Started Feb 25 01:45:01 PM PST 24
Finished Feb 25 01:45:02 PM PST 24
Peak memory 195852 kb
Host smart-cc250365-61fd-440a-81a4-9154d69083e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648599222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1648599222
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2496285066
Short name T583
Test name
Test status
Simulation time 94795836 ps
CPU time 1.38 seconds
Started Feb 25 01:45:02 PM PST 24
Finished Feb 25 01:45:03 PM PST 24
Peak memory 198084 kb
Host smart-b4d4a2f5-1a1f-4ad2-8d84-8f051d50602d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496285066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2496285066
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1250218793
Short name T286
Test name
Test status
Simulation time 317770058 ps
CPU time 5.5 seconds
Started Feb 25 01:45:05 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 198076 kb
Host smart-b3825e45-19f8-4734-be8b-857795d57f6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250218793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1250218793
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.4204275124
Short name T522
Test name
Test status
Simulation time 50744976 ps
CPU time 1.03 seconds
Started Feb 25 01:45:01 PM PST 24
Finished Feb 25 01:45:02 PM PST 24
Peak memory 196296 kb
Host smart-27e4b4b1-22f6-486d-94c3-fe2254e7ca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204275124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4204275124
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4217627234
Short name T211
Test name
Test status
Simulation time 152780125 ps
CPU time 1.48 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 195616 kb
Host smart-74d3d136-773f-4580-a9d2-97ceb753dc37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217627234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4217627234
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3932541943
Short name T514
Test name
Test status
Simulation time 4362107220 ps
CPU time 62.43 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 198232 kb
Host smart-78c7bbaa-1a3f-4e9d-9b03-468da24c46d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932541943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3932541943
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1561503804
Short name T344
Test name
Test status
Simulation time 36171046 ps
CPU time 0.54 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 193916 kb
Host smart-c0a04183-f5ea-47dd-b7bc-c731e82ebcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561503804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1561503804
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3699806631
Short name T154
Test name
Test status
Simulation time 25047128 ps
CPU time 0.82 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 196144 kb
Host smart-2d1a66ec-9464-4c50-925e-f161978abf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699806631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3699806631
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2603076739
Short name T593
Test name
Test status
Simulation time 450272353 ps
CPU time 22.66 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 196696 kb
Host smart-4a090e8e-92f4-4b61-a1a2-6905577d474d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603076739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2603076739
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2651128037
Short name T604
Test name
Test status
Simulation time 287056000 ps
CPU time 0.92 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 195984 kb
Host smart-2920d5eb-6c47-4fd2-b5f4-e0c7122081dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651128037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2651128037
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.323257920
Short name T342
Test name
Test status
Simulation time 111604162 ps
CPU time 1.09 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 196908 kb
Host smart-91232eda-0acf-490b-adee-93e54ce78ade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323257920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.323257920
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1733428364
Short name T321
Test name
Test status
Simulation time 182372235 ps
CPU time 1.95 seconds
Started Feb 25 01:45:13 PM PST 24
Finished Feb 25 01:45:16 PM PST 24
Peak memory 197960 kb
Host smart-67f8e975-dc1d-4430-b0ac-e2e61d089902
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733428364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1733428364
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1062945877
Short name T385
Test name
Test status
Simulation time 645512614 ps
CPU time 3.07 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 195872 kb
Host smart-c0bff5cc-1c9f-4203-a613-ca87496b0ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062945877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1062945877
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3545580756
Short name T98
Test name
Test status
Simulation time 228417528 ps
CPU time 0.89 seconds
Started Feb 25 01:45:10 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 195940 kb
Host smart-2a565fdd-d38e-4037-ba54-5cc35ed92c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545580756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3545580756
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1501002407
Short name T495
Test name
Test status
Simulation time 53733994 ps
CPU time 0.82 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:04 PM PST 24
Peak memory 196572 kb
Host smart-6cbd9e47-5066-46e6-b37c-05c2ff734851
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501002407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1501002407
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4235050214
Short name T19
Test name
Test status
Simulation time 180726429 ps
CPU time 1.66 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:06 PM PST 24
Peak memory 197156 kb
Host smart-4e0ae695-b9c9-4a54-aa4d-0fb95a278cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235050214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4235050214
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2958454069
Short name T288
Test name
Test status
Simulation time 141849981 ps
CPU time 1.13 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 195820 kb
Host smart-279c78ea-ef5d-47f6-806a-dc56f4290734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958454069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2958454069
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1555884131
Short name T614
Test name
Test status
Simulation time 287046443 ps
CPU time 1.32 seconds
Started Feb 25 01:45:03 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 195684 kb
Host smart-be7ad86f-8780-44ac-9d2e-645963ad3203
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555884131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1555884131
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1502134982
Short name T122
Test name
Test status
Simulation time 13468264610 ps
CPU time 35.16 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 198156 kb
Host smart-bd20b324-6004-4dec-93c1-50414559e2a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502134982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1502134982
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.312446176
Short name T350
Test name
Test status
Simulation time 13258327 ps
CPU time 0.6 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 193044 kb
Host smart-6dbb4126-856b-4938-b9cb-8f238e4ebc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312446176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.312446176
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3630703931
Short name T362
Test name
Test status
Simulation time 75466995 ps
CPU time 0.74 seconds
Started Feb 25 01:45:10 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 195868 kb
Host smart-bcfbd0eb-885b-4a9a-9d7c-ec2860498339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630703931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3630703931
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1630317331
Short name T240
Test name
Test status
Simulation time 1252272679 ps
CPU time 10.92 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:19 PM PST 24
Peak memory 196440 kb
Host smart-c17019a1-9b6e-46a6-aac8-9a54a6dc431e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630317331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1630317331
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3720195197
Short name T316
Test name
Test status
Simulation time 80300507 ps
CPU time 0.65 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 194620 kb
Host smart-b8314b52-2fe8-428a-9df7-d9313f59e612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720195197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3720195197
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4008689608
Short name T702
Test name
Test status
Simulation time 123270091 ps
CPU time 0.98 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 195864 kb
Host smart-88d91716-ca8d-4d3f-8ea9-de3cd69b9c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008689608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4008689608
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.226384342
Short name T536
Test name
Test status
Simulation time 434572849 ps
CPU time 3.2 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 198160 kb
Host smart-7e47a876-5b07-4226-9c02-58fbee1e6f2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226384342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.226384342
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4198259417
Short name T459
Test name
Test status
Simulation time 38361669 ps
CPU time 1.4 seconds
Started Feb 25 01:45:05 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 196052 kb
Host smart-35e60745-3e1d-4dfd-8123-cd56fd5a1496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198259417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4198259417
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3803943231
Short name T236
Test name
Test status
Simulation time 62920779 ps
CPU time 1.12 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 196652 kb
Host smart-10963f4f-51ca-467d-80b4-49d6d8d42758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803943231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3803943231
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1591140719
Short name T512
Test name
Test status
Simulation time 459162682 ps
CPU time 1.34 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 197104 kb
Host smart-c5b7b42d-b440-4581-a8b8-dffe82b47fe8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591140719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1591140719
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.621451179
Short name T10
Test name
Test status
Simulation time 560092577 ps
CPU time 3.33 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 197924 kb
Host smart-eae26e50-37ea-4ab0-a8a8-3dbe388767c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621451179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.621451179
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3882942853
Short name T133
Test name
Test status
Simulation time 108292278 ps
CPU time 1.13 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 196444 kb
Host smart-32a939b0-9175-4c2f-b8dc-edb747510f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882942853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3882942853
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1706651578
Short name T671
Test name
Test status
Simulation time 73621735 ps
CPU time 1.24 seconds
Started Feb 25 01:45:12 PM PST 24
Finished Feb 25 01:45:13 PM PST 24
Peak memory 195528 kb
Host smart-a9fa046c-2aa2-4f64-a7b7-e7b8a246cf11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706651578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1706651578
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.223064555
Short name T398
Test name
Test status
Simulation time 18589520309 ps
CPU time 210.1 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:48:40 PM PST 24
Peak memory 198208 kb
Host smart-d7ff7e62-6d7d-4fbf-b44a-189cf81fcd2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223064555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.223064555
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.223132707
Short name T63
Test name
Test status
Simulation time 47362846620 ps
CPU time 1004.77 seconds
Started Feb 25 01:45:05 PM PST 24
Finished Feb 25 02:01:50 PM PST 24
Peak memory 198264 kb
Host smart-2eb34a5b-72e1-4301-817a-72b5e97f0603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=223132707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.223132707
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.174544869
Short name T325
Test name
Test status
Simulation time 51040883 ps
CPU time 0.56 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 193876 kb
Host smart-5e5645e3-540e-4042-a3e0-741a590a9c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174544869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.174544869
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1639144598
Short name T317
Test name
Test status
Simulation time 124429542 ps
CPU time 0.63 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 194052 kb
Host smart-6a0385a5-1cd8-4d7c-982f-d70672b50abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639144598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1639144598
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3326957956
Short name T237
Test name
Test status
Simulation time 2737861342 ps
CPU time 14.67 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 197000 kb
Host smart-c7378db0-ebeb-4504-8840-5547261a012e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326957956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3326957956
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2437268657
Short name T100
Test name
Test status
Simulation time 76158308 ps
CPU time 1.04 seconds
Started Feb 25 01:45:05 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 196372 kb
Host smart-351de5f5-603f-41fd-a6c5-b76cb7061ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437268657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2437268657
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1726569779
Short name T229
Test name
Test status
Simulation time 94366350 ps
CPU time 1.32 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 196652 kb
Host smart-190dcd24-052d-4f06-a43b-1f2b220fc761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726569779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1726569779
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.558159304
Short name T307
Test name
Test status
Simulation time 27138020 ps
CPU time 1.14 seconds
Started Feb 25 01:45:10 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 197340 kb
Host smart-e851385a-cf53-4c43-8709-4473fdbac2ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558159304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.558159304
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1941920928
Short name T646
Test name
Test status
Simulation time 55510485 ps
CPU time 0.95 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 196244 kb
Host smart-b8990219-c883-48f4-8bd8-85523c617ead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941920928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1941920928
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1272159383
Short name T309
Test name
Test status
Simulation time 31247607 ps
CPU time 1.17 seconds
Started Feb 25 01:45:12 PM PST 24
Finished Feb 25 01:45:13 PM PST 24
Peak memory 196080 kb
Host smart-d8a7c506-4e18-4064-9211-9ab79e1097df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272159383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1272159383
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1627673460
Short name T625
Test name
Test status
Simulation time 32592805 ps
CPU time 0.79 seconds
Started Feb 25 01:45:09 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 195568 kb
Host smart-70ea13a4-5079-4166-a6fc-fd0d0f51e21a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627673460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1627673460
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1320517177
Short name T706
Test name
Test status
Simulation time 101359862 ps
CPU time 2.07 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 198080 kb
Host smart-defee90c-beba-4d76-9944-6764af504869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320517177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1320517177
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.703252769
Short name T306
Test name
Test status
Simulation time 206673234 ps
CPU time 1.06 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:10 PM PST 24
Peak memory 195668 kb
Host smart-cb107aa1-1a0d-45ff-a5b0-ae0ed17967bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703252769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.703252769
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.352672650
Short name T331
Test name
Test status
Simulation time 111404268 ps
CPU time 0.92 seconds
Started Feb 25 01:45:11 PM PST 24
Finished Feb 25 01:45:12 PM PST 24
Peak memory 197216 kb
Host smart-e13bf195-9cf1-488c-af1c-1dc88d24a066
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352672650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.352672650
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1188337705
Short name T507
Test name
Test status
Simulation time 13775992681 ps
CPU time 171.72 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:47:56 PM PST 24
Peak memory 198212 kb
Host smart-15870a08-0e4b-4f07-9de4-4a4ca500198e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188337705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1188337705
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.43842026
Short name T430
Test name
Test status
Simulation time 24474667 ps
CPU time 0.56 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:21 PM PST 24
Peak memory 193904 kb
Host smart-30cda490-7824-4c57-85df-a630ac3bed7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43842026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.43842026
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3024869015
Short name T55
Test name
Test status
Simulation time 41278798 ps
CPU time 0.6 seconds
Started Feb 25 01:45:08 PM PST 24
Finished Feb 25 01:45:09 PM PST 24
Peak memory 192876 kb
Host smart-f159c6ee-012f-4db7-938c-ac9d37f3fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024869015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3024869015
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3500642410
Short name T687
Test name
Test status
Simulation time 919264424 ps
CPU time 8.94 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 197984 kb
Host smart-7fbf2bd6-e912-47a7-b5cd-ce4b501d66f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500642410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3500642410
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1005905546
Short name T18
Test name
Test status
Simulation time 622163026 ps
CPU time 0.78 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 196692 kb
Host smart-75be8f48-0ef4-4b59-bb86-212b691c2453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005905546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1005905546
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.95118528
Short name T303
Test name
Test status
Simulation time 137688651 ps
CPU time 1.16 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 196132 kb
Host smart-fc6e3627-a1cf-431d-8773-340190110030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95118528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.95118528
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1976329502
Short name T379
Test name
Test status
Simulation time 352079589 ps
CPU time 3.55 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 198228 kb
Host smart-2d845d3a-2449-4c00-84a3-dfba15465485
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976329502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1976329502
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1896870242
Short name T376
Test name
Test status
Simulation time 107953384 ps
CPU time 1.27 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:25 PM PST 24
Peak memory 194612 kb
Host smart-93e50375-bcfc-4007-8cb9-8fa056962a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896870242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1896870242
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1042993018
Short name T600
Test name
Test status
Simulation time 35917657 ps
CPU time 0.84 seconds
Started Feb 25 01:45:07 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 195548 kb
Host smart-2be505eb-43c0-4ee1-9b63-9ce52f0a307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042993018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1042993018
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3167307328
Short name T212
Test name
Test status
Simulation time 524591183 ps
CPU time 1.14 seconds
Started Feb 25 01:45:04 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 196164 kb
Host smart-6415d118-c1cd-4d66-9c9c-08edf3544b60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167307328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3167307328
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3602196822
Short name T470
Test name
Test status
Simulation time 46713501 ps
CPU time 2.22 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 198044 kb
Host smart-6771b48a-f89b-4664-9235-732f92882961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602196822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3602196822
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3660392655
Short name T121
Test name
Test status
Simulation time 96304552 ps
CPU time 1.48 seconds
Started Feb 25 01:45:06 PM PST 24
Finished Feb 25 01:45:07 PM PST 24
Peak memory 196888 kb
Host smart-74f20ff6-bccf-48f8-b8c3-dee0df41c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660392655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3660392655
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1008523854
Short name T595
Test name
Test status
Simulation time 163164501 ps
CPU time 1.03 seconds
Started Feb 25 01:45:10 PM PST 24
Finished Feb 25 01:45:11 PM PST 24
Peak memory 195600 kb
Host smart-dfd4d36c-478e-4acf-bf4e-812c263eb795
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008523854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1008523854
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1947418007
Short name T187
Test name
Test status
Simulation time 3521902729 ps
CPU time 93.2 seconds
Started Feb 25 01:45:17 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 198216 kb
Host smart-ae3646eb-13e1-4917-8199-dba31fe50b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947418007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1947418007
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2184949181
Short name T683
Test name
Test status
Simulation time 26354593 ps
CPU time 0.57 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 194092 kb
Host smart-fcedb6ff-7605-4f2a-8a11-6ab257910584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184949181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2184949181
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3489856242
Short name T104
Test name
Test status
Simulation time 50915443 ps
CPU time 0.91 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 197316 kb
Host smart-7d137849-b33d-4578-939f-df3d375b1738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489856242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3489856242
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.271977449
Short name T573
Test name
Test status
Simulation time 1291171319 ps
CPU time 16.98 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:37 PM PST 24
Peak memory 198092 kb
Host smart-cb1c6457-eeda-4dd4-be0e-f55b719830d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271977449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.271977449
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3779975737
Short name T405
Test name
Test status
Simulation time 190808730 ps
CPU time 0.76 seconds
Started Feb 25 01:45:17 PM PST 24
Finished Feb 25 01:45:18 PM PST 24
Peak memory 195880 kb
Host smart-ef90e363-5ced-431b-8ee5-20334a09595d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779975737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3779975737
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3192291891
Short name T101
Test name
Test status
Simulation time 144814301 ps
CPU time 1.26 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:21 PM PST 24
Peak memory 195760 kb
Host smart-86c1e61a-242e-4aa5-8806-a47185f05884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192291891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3192291891
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.963312176
Short name T225
Test name
Test status
Simulation time 91805541 ps
CPU time 1.23 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 197976 kb
Host smart-8f36a730-7cd7-4cc2-9341-c64ebec3003e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963312176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.963312176
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2174354692
Short name T311
Test name
Test status
Simulation time 103382684 ps
CPU time 2.47 seconds
Started Feb 25 01:45:22 PM PST 24
Finished Feb 25 01:45:24 PM PST 24
Peak memory 196968 kb
Host smart-bcfe057e-dc76-4655-92bf-1fc8d39630fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174354692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2174354692
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.835816893
Short name T364
Test name
Test status
Simulation time 199251970 ps
CPU time 1.22 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 197424 kb
Host smart-1c5973b6-83b6-4995-bbd5-61d3967796ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835816893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.835816893
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2441140351
Short name T540
Test name
Test status
Simulation time 31801889 ps
CPU time 0.92 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 196584 kb
Host smart-fbe835bf-b359-44fe-965f-af1b165932d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441140351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2441140351
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.44820294
Short name T435
Test name
Test status
Simulation time 395514036 ps
CPU time 4.5 seconds
Started Feb 25 01:45:24 PM PST 24
Finished Feb 25 01:45:29 PM PST 24
Peak memory 198116 kb
Host smart-da4f55bf-4a44-4ebe-ba94-28d9456aee97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44820294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand
om_long_reg_writes_reg_reads.44820294
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4180092668
Short name T175
Test name
Test status
Simulation time 90222979 ps
CPU time 0.97 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 196424 kb
Host smart-3e5bb7b1-311b-4127-997a-602f6d85626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180092668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4180092668
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.38549514
Short name T420
Test name
Test status
Simulation time 39154127 ps
CPU time 1.17 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:19 PM PST 24
Peak memory 196596 kb
Host smart-a217be50-df12-451f-91f7-5b6f0ef45fba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38549514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.38549514
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1722027689
Short name T599
Test name
Test status
Simulation time 19941044195 ps
CPU time 129.55 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:47:27 PM PST 24
Peak memory 198192 kb
Host smart-995b1881-826c-4b5d-a94c-1081ed2c252a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722027689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1722027689
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3805370169
Short name T180
Test name
Test status
Simulation time 11411319 ps
CPU time 0.56 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:23 PM PST 24
Peak memory 193956 kb
Host smart-5e61a634-a129-420e-8c21-3a887d0f8369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805370169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3805370169
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1067365092
Short name T437
Test name
Test status
Simulation time 15690892 ps
CPU time 0.66 seconds
Started Feb 25 01:45:22 PM PST 24
Finished Feb 25 01:45:23 PM PST 24
Peak memory 193888 kb
Host smart-4d332dce-985c-4471-912c-6672f16d98bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067365092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1067365092
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3153786744
Short name T123
Test name
Test status
Simulation time 702144048 ps
CPU time 19.31 seconds
Started Feb 25 01:45:16 PM PST 24
Finished Feb 25 01:45:36 PM PST 24
Peak memory 196928 kb
Host smart-018e9ab7-a546-44f3-affc-e24613967166
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153786744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3153786744
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3535822020
Short name T31
Test name
Test status
Simulation time 79854504 ps
CPU time 0.79 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:25 PM PST 24
Peak memory 195820 kb
Host smart-5f666100-d53b-4854-8b4e-9fb850c0b46a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535822020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3535822020
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2784735930
Short name T661
Test name
Test status
Simulation time 1436266126 ps
CPU time 1.26 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 196712 kb
Host smart-34977a29-6062-4bb6-860d-9a967740e27d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784735930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2784735930
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3639225050
Short name T368
Test name
Test status
Simulation time 24802571 ps
CPU time 1.14 seconds
Started Feb 25 01:45:17 PM PST 24
Finished Feb 25 01:45:18 PM PST 24
Peak memory 197944 kb
Host smart-a7633368-1a06-4475-ab51-067ecfbf59f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639225050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3639225050
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2281145416
Short name T190
Test name
Test status
Simulation time 149826671 ps
CPU time 3.34 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:24 PM PST 24
Peak memory 197940 kb
Host smart-c71333ae-8d1b-425e-982d-30f533c41cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281145416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2281145416
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.961572196
Short name T224
Test name
Test status
Simulation time 135974071 ps
CPU time 0.94 seconds
Started Feb 25 01:45:17 PM PST 24
Finished Feb 25 01:45:18 PM PST 24
Peak memory 197328 kb
Host smart-62668775-9e00-46bf-bb6e-bbdb7d56a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961572196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.961572196
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3484543295
Short name T674
Test name
Test status
Simulation time 110941731 ps
CPU time 0.83 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 197488 kb
Host smart-fd51bb78-c543-4795-8d16-c6f5dd45d3cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484543295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3484543295
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_smoke.2867505924
Short name T487
Test name
Test status
Simulation time 94847852 ps
CPU time 1.07 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 195848 kb
Host smart-d6474240-0d6b-4484-8279-d69f8ad742d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867505924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2867505924
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2652127536
Short name T168
Test name
Test status
Simulation time 60747763 ps
CPU time 0.83 seconds
Started Feb 25 01:45:25 PM PST 24
Finished Feb 25 01:45:26 PM PST 24
Peak memory 195984 kb
Host smart-beed8031-e438-4aed-bfb1-2e60e1a59425
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652127536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2652127536
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2841434928
Short name T418
Test name
Test status
Simulation time 59352745297 ps
CPU time 194.44 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:48:33 PM PST 24
Peak memory 198152 kb
Host smart-bd10b8e1-23fe-4fbd-9cfd-061b55d27c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841434928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2841434928
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.56718015
Short name T523
Test name
Test status
Simulation time 25960574 ps
CPU time 0.55 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:21 PM PST 24
Peak memory 193944 kb
Host smart-f48214b6-a9bf-4e8f-a3a8-91245fe46cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56718015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.56718015
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.943263000
Short name T597
Test name
Test status
Simulation time 68404092 ps
CPU time 0.64 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 194044 kb
Host smart-e0da0478-721a-4334-b7ed-14f50744f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943263000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.943263000
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2859819521
Short name T701
Test name
Test status
Simulation time 5982824195 ps
CPU time 27.11 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 197112 kb
Host smart-3ef04241-08bd-43d0-b57e-580b8d07a1c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859819521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2859819521
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3045946347
Short name T293
Test name
Test status
Simulation time 143974490 ps
CPU time 0.76 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 195340 kb
Host smart-fe5402cb-4754-485f-9c49-ca6229899cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045946347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3045946347
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2031347824
Short name T263
Test name
Test status
Simulation time 22616843 ps
CPU time 0.7 seconds
Started Feb 25 01:45:17 PM PST 24
Finished Feb 25 01:45:18 PM PST 24
Peak memory 195132 kb
Host smart-77ec45dc-939e-4044-a91c-dcad50cefa69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031347824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2031347824
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.846038718
Short name T638
Test name
Test status
Simulation time 950398918 ps
CPU time 3.5 seconds
Started Feb 25 01:45:25 PM PST 24
Finished Feb 25 01:45:29 PM PST 24
Peak memory 198264 kb
Host smart-ca81efd4-c12a-43bd-8c4c-847a714d73c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846038718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.846038718
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1937251521
Short name T191
Test name
Test status
Simulation time 399017409 ps
CPU time 2.96 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:24 PM PST 24
Peak memory 197236 kb
Host smart-a01c3d21-ba02-4d86-ae61-1e314d74174f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937251521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1937251521
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2242533592
Short name T410
Test name
Test status
Simulation time 268930389 ps
CPU time 0.94 seconds
Started Feb 25 01:45:16 PM PST 24
Finished Feb 25 01:45:17 PM PST 24
Peak memory 195964 kb
Host smart-1cd5139d-393d-444a-842b-696b9bd5660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242533592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2242533592
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2553769114
Short name T204
Test name
Test status
Simulation time 63529414 ps
CPU time 1.23 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:21 PM PST 24
Peak memory 195868 kb
Host smart-a0f21704-a72d-48ef-947e-dd34f0993f25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553769114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2553769114
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2533337609
Short name T329
Test name
Test status
Simulation time 788340257 ps
CPU time 2.22 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 197884 kb
Host smart-2148412a-331c-43d7-9f30-1f6b59beb383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533337609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2533337609
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.167196572
Short name T566
Test name
Test status
Simulation time 29205255 ps
CPU time 0.96 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:19 PM PST 24
Peak memory 196556 kb
Host smart-cca5e4e9-4cfc-46dc-bf50-d7ae1c08cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167196572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.167196572
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2100870128
Short name T371
Test name
Test status
Simulation time 30258146 ps
CPU time 1.06 seconds
Started Feb 25 01:45:22 PM PST 24
Finished Feb 25 01:45:23 PM PST 24
Peak memory 196376 kb
Host smart-2664ff69-2af0-4757-9ecb-e766b3e32812
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100870128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2100870128
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3270537321
Short name T529
Test name
Test status
Simulation time 34019865888 ps
CPU time 243.29 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:49:24 PM PST 24
Peak memory 198192 kb
Host smart-b3c8da73-c2ed-45c6-ab8e-1de6a8c4edb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270537321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3270537321
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2464025569
Short name T367
Test name
Test status
Simulation time 18923411 ps
CPU time 0.57 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 193932 kb
Host smart-2d696871-5ed1-440b-b8f6-a54d6956c5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464025569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2464025569
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3446419965
Short name T575
Test name
Test status
Simulation time 104767723 ps
CPU time 0.83 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 195356 kb
Host smart-b357559d-88d1-4245-bf33-697cc890187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446419965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3446419965
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.224495311
Short name T665
Test name
Test status
Simulation time 1958533293 ps
CPU time 24.43 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 196784 kb
Host smart-196e52dc-ebc9-4027-b4cd-c921af60e5de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224495311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.224495311
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4237948031
Short name T407
Test name
Test status
Simulation time 54994784 ps
CPU time 0.68 seconds
Started Feb 25 01:45:24 PM PST 24
Finished Feb 25 01:45:25 PM PST 24
Peak memory 194652 kb
Host smart-48712348-e4a8-4339-be31-5084b0f548c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237948031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4237948031
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2158018468
Short name T441
Test name
Test status
Simulation time 153768453 ps
CPU time 0.81 seconds
Started Feb 25 01:45:19 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 195572 kb
Host smart-e24326d7-cb8b-4a7b-bf11-0090f7f3eb85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158018468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2158018468
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1970637251
Short name T15
Test name
Test status
Simulation time 89888505 ps
CPU time 2.91 seconds
Started Feb 25 01:45:18 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 198208 kb
Host smart-69842810-4895-4b0d-90cf-5c4255b32d18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970637251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1970637251
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.321808982
Short name T424
Test name
Test status
Simulation time 617332321 ps
CPU time 3.36 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:24 PM PST 24
Peak memory 198140 kb
Host smart-22057592-abcc-45df-85c7-9e4e7749a09b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321808982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
321808982
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1387654540
Short name T338
Test name
Test status
Simulation time 32161569 ps
CPU time 1.2 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 197104 kb
Host smart-53275fb5-b92a-4d8f-a1bf-3d886bbaab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387654540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1387654540
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2733605376
Short name T426
Test name
Test status
Simulation time 35424361 ps
CPU time 1.01 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 196752 kb
Host smart-51d02f01-fc66-4292-ab9d-31e72f4dbf0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733605376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2733605376
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3009416172
Short name T465
Test name
Test status
Simulation time 294347123 ps
CPU time 5.03 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:29 PM PST 24
Peak memory 196924 kb
Host smart-18a1b7a7-52a4-4ec0-9278-d1a9d820f6a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009416172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3009416172
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1970031392
Short name T648
Test name
Test status
Simulation time 216583991 ps
CPU time 1.06 seconds
Started Feb 25 01:45:25 PM PST 24
Finished Feb 25 01:45:26 PM PST 24
Peak memory 196408 kb
Host smart-820e50f8-a5f9-46f2-b05b-962384218004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970031392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1970031392
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3440948439
Short name T318
Test name
Test status
Simulation time 45007340 ps
CPU time 1.32 seconds
Started Feb 25 01:45:23 PM PST 24
Finished Feb 25 01:45:26 PM PST 24
Peak memory 197012 kb
Host smart-f072d719-4859-4e64-92b2-09a47e4db9d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440948439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3440948439
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.170014818
Short name T537
Test name
Test status
Simulation time 10948126466 ps
CPU time 143.4 seconds
Started Feb 25 01:45:20 PM PST 24
Finished Feb 25 01:47:44 PM PST 24
Peak memory 198192 kb
Host smart-0d6acc7e-fb93-4e50-a5b9-d5fd25ce8601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170014818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.170014818
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3037264735
Short name T370
Test name
Test status
Simulation time 11816412 ps
CPU time 0.56 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 193920 kb
Host smart-1a2f2f54-8e32-44a1-8e84-6e6a1637ca4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037264735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3037264735
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1995778464
Short name T605
Test name
Test status
Simulation time 146224433 ps
CPU time 0.84 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:40 PM PST 24
Peak memory 195400 kb
Host smart-2a37a7b3-b784-4699-ab66-1544923c7c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995778464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1995778464
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3801543215
Short name T451
Test name
Test status
Simulation time 1688811341 ps
CPU time 20.47 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 196600 kb
Host smart-bfa34508-0cdc-4bc7-92e8-8f4c35096eec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801543215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3801543215
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2219726928
Short name T608
Test name
Test status
Simulation time 279386997 ps
CPU time 0.87 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 196084 kb
Host smart-cc0174bb-16ac-4784-aecc-0cb2ab68c832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219726928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2219726928
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2959711240
Short name T689
Test name
Test status
Simulation time 32267192 ps
CPU time 0.68 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 195000 kb
Host smart-96edd237-8732-450e-980c-49b0b7e96657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959711240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2959711240
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2876930214
Short name T346
Test name
Test status
Simulation time 49118214 ps
CPU time 1.14 seconds
Started Feb 25 01:45:30 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 197916 kb
Host smart-411794d5-f8ec-493c-8675-e05b0bf9c658
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876930214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2876930214
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.96544581
Short name T138
Test name
Test status
Simulation time 206774164 ps
CPU time 3.02 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 197212 kb
Host smart-c11b75c2-2a73-4eab-b3b0-4f7c664d50f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96544581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.96544581
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1064809169
Short name T423
Test name
Test status
Simulation time 337771796 ps
CPU time 0.91 seconds
Started Feb 25 01:45:21 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 196112 kb
Host smart-069094a5-a434-4ee3-9b66-73b01deaca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064809169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1064809169
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1257046141
Short name T466
Test name
Test status
Simulation time 83025216 ps
CPU time 1.15 seconds
Started Feb 25 01:45:22 PM PST 24
Finished Feb 25 01:45:23 PM PST 24
Peak memory 196104 kb
Host smart-13e072fe-930e-46b0-bd27-2ee6e1b9adb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257046141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1257046141
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2896184676
Short name T694
Test name
Test status
Simulation time 120684157 ps
CPU time 5.88 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 198060 kb
Host smart-86c9b0bc-36dd-4444-b2f5-5acc123c550e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896184676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2896184676
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1218482775
Short name T450
Test name
Test status
Simulation time 21480766 ps
CPU time 0.75 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 196000 kb
Host smart-473b8ae7-ec60-4607-a87d-fc0e4755263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218482775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1218482775
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1312039740
Short name T676
Test name
Test status
Simulation time 24651892 ps
CPU time 0.75 seconds
Started Feb 25 01:45:22 PM PST 24
Finished Feb 25 01:45:23 PM PST 24
Peak memory 194180 kb
Host smart-2d3232fb-0945-46ab-bd74-9891ea27fcb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312039740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1312039740
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3652156535
Short name T177
Test name
Test status
Simulation time 10403419802 ps
CPU time 154.22 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:48:06 PM PST 24
Peak memory 198172 kb
Host smart-763239d8-fa73-4c96-908f-1fc5bc7eb03a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652156535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3652156535
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2537854599
Short name T505
Test name
Test status
Simulation time 35724167 ps
CPU time 0.55 seconds
Started Feb 25 01:43:31 PM PST 24
Finished Feb 25 01:43:32 PM PST 24
Peak memory 194620 kb
Host smart-0040e895-8b76-4477-9237-f2ad408bab46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537854599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2537854599
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2692538943
Short name T178
Test name
Test status
Simulation time 120129062 ps
CPU time 0.82 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 195420 kb
Host smart-3d2600c4-c0dc-4ed0-bfe8-84bc2ae18e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692538943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2692538943
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3495248071
Short name T572
Test name
Test status
Simulation time 553802385 ps
CPU time 30.04 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 197008 kb
Host smart-cabd57ac-0863-4463-b713-f8c81355f10a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495248071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3495248071
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4003504759
Short name T427
Test name
Test status
Simulation time 57581285 ps
CPU time 0.81 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 196004 kb
Host smart-1883457e-5d94-4bcc-a4ab-fb28f8e8f989
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003504759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4003504759
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3932271469
Short name T657
Test name
Test status
Simulation time 158100555 ps
CPU time 0.72 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 195424 kb
Host smart-354f56d8-8ec0-4765-9b05-f8ff9b8f17b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932271469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3932271469
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2027993425
Short name T440
Test name
Test status
Simulation time 131016668 ps
CPU time 1.61 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 198112 kb
Host smart-44d6b1da-c4b2-4a2f-b157-58a84c9db194
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027993425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2027993425
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.56436220
Short name T492
Test name
Test status
Simulation time 724478186 ps
CPU time 3.56 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 198052 kb
Host smart-413ef2d2-50de-4592-aa97-df0d01650eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56436220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.56436220
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1487047355
Short name T553
Test name
Test status
Simulation time 62699041 ps
CPU time 1.15 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 197192 kb
Host smart-2692ab29-8cb0-42e9-bf3e-71f01f52b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487047355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1487047355
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4224218039
Short name T449
Test name
Test status
Simulation time 35427276 ps
CPU time 0.98 seconds
Started Feb 25 01:43:31 PM PST 24
Finished Feb 25 01:43:32 PM PST 24
Peak memory 195916 kb
Host smart-c886479b-e8c1-489b-8bb0-b0a465187e81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224218039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4224218039
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2820184891
Short name T623
Test name
Test status
Simulation time 989843619 ps
CPU time 3.13 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 198040 kb
Host smart-44a932f4-0d19-485a-a904-8cb47f91a58e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820184891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2820184891
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.28426126
Short name T592
Test name
Test status
Simulation time 102039748 ps
CPU time 1.56 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 196872 kb
Host smart-fcd281cb-5ec4-4d25-8ff2-097773c862cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28426126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.28426126
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.196790876
Short name T234
Test name
Test status
Simulation time 196609049 ps
CPU time 1.62 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 196828 kb
Host smart-5741bf93-e830-440a-8250-e5190a62de66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196790876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.196790876
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3403358161
Short name T135
Test name
Test status
Simulation time 10390725567 ps
CPU time 102.11 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 198196 kb
Host smart-55dae86f-2eb5-4462-a198-310b2df9116b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403358161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3403358161
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3058802298
Short name T543
Test name
Test status
Simulation time 14840019 ps
CPU time 0.57 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 193888 kb
Host smart-ec64be90-259d-427d-b028-a2ad0b9075cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058802298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3058802298
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3376903921
Short name T615
Test name
Test status
Simulation time 159957824 ps
CPU time 0.84 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 196328 kb
Host smart-5d79e032-4491-4ef4-a9d7-87903015d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376903921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3376903921
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2711740596
Short name T642
Test name
Test status
Simulation time 449961832 ps
CPU time 23.18 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:58 PM PST 24
Peak memory 196924 kb
Host smart-cb73404e-c43e-4f5f-8c27-0fa3c7515de6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711740596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2711740596
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1531132863
Short name T700
Test name
Test status
Simulation time 88481714 ps
CPU time 1.04 seconds
Started Feb 25 01:43:33 PM PST 24
Finished Feb 25 01:43:34 PM PST 24
Peak memory 196720 kb
Host smart-907e6a89-475b-47a0-99e0-e09069054deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531132863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1531132863
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1746853452
Short name T655
Test name
Test status
Simulation time 166235595 ps
CPU time 1.38 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:35 PM PST 24
Peak memory 197024 kb
Host smart-e9ecc64f-6e27-4a2f-89b2-fd1a35e691e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746853452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1746853452
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2355133402
Short name T185
Test name
Test status
Simulation time 186428001 ps
CPU time 3.72 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:43 PM PST 24
Peak memory 196436 kb
Host smart-bf7e0f4a-f049-454a-bb4a-ea8d86b75a7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355133402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2355133402
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3682027031
Short name T586
Test name
Test status
Simulation time 116646648 ps
CPU time 2.48 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 196664 kb
Host smart-0a5f15d9-74b5-4bfc-a33b-aebabc94435d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682027031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3682027031
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.718085695
Short name T419
Test name
Test status
Simulation time 92698252 ps
CPU time 1.09 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 195836 kb
Host smart-33189722-1a3d-4c5a-a8f9-945a01d1f0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718085695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.718085695
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.437791350
Short name T685
Test name
Test status
Simulation time 32670504 ps
CPU time 1.12 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:34 PM PST 24
Peak memory 196180 kb
Host smart-3be947bc-82bf-4181-a967-0553718eaeb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437791350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.437791350
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.152924232
Short name T567
Test name
Test status
Simulation time 449246448 ps
CPU time 3.81 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 198040 kb
Host smart-0400414e-50b2-46a1-9703-cce7e9dd1e8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152924232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.152924232
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1898047093
Short name T294
Test name
Test status
Simulation time 45221265 ps
CPU time 1.26 seconds
Started Feb 25 01:43:33 PM PST 24
Finished Feb 25 01:43:34 PM PST 24
Peak memory 196808 kb
Host smart-e9fc88e0-6271-49c8-b5bc-c19c68293e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898047093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1898047093
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3224312249
Short name T520
Test name
Test status
Simulation time 622477752 ps
CPU time 1.01 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 196384 kb
Host smart-d795a96e-5926-46ce-8802-7459ca46c5e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224312249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3224312249
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2332036808
Short name T587
Test name
Test status
Simulation time 129030541312 ps
CPU time 162.96 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 198116 kb
Host smart-b3be894c-3674-48bc-bd19-d5151eed6ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332036808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2332036808
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.803553544
Short name T645
Test name
Test status
Simulation time 68172324003 ps
CPU time 278.2 seconds
Started Feb 25 01:43:32 PM PST 24
Finished Feb 25 01:48:11 PM PST 24
Peak memory 198328 kb
Host smart-cec4f8a0-bd3b-4165-a6fe-41942e117005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=803553544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.803553544
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.129488150
Short name T640
Test name
Test status
Simulation time 59274928 ps
CPU time 0.6 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 193928 kb
Host smart-06d25758-01b0-4899-9650-3c70cbf23e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129488150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.129488150
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.223796817
Short name T621
Test name
Test status
Simulation time 92322174 ps
CPU time 0.83 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 195436 kb
Host smart-75d7cf00-5538-4487-9f89-5ca6094f0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223796817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.223796817
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2747997757
Short name T235
Test name
Test status
Simulation time 3178814700 ps
CPU time 22.42 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 196708 kb
Host smart-b807a94d-1e54-4b07-a1a0-9041db4f4a04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747997757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2747997757
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.807189691
Short name T125
Test name
Test status
Simulation time 107506295 ps
CPU time 0.98 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 196724 kb
Host smart-b2fb1a3d-d610-4ef9-b51c-bb3e0ad85eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807189691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.807189691
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.863670324
Short name T26
Test name
Test status
Simulation time 19268976 ps
CPU time 0.65 seconds
Started Feb 25 01:43:34 PM PST 24
Finished Feb 25 01:43:34 PM PST 24
Peak memory 194308 kb
Host smart-88acfc40-2c54-4b6b-933d-5d8125508a51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863670324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.863670324
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3429055994
Short name T28
Test name
Test status
Simulation time 110112267 ps
CPU time 2.16 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 198128 kb
Host smart-cbd6cef1-1755-456f-a511-585215963d2b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429055994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3429055994
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3914039030
Short name T71
Test name
Test status
Simulation time 46406622 ps
CPU time 1.41 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 195844 kb
Host smart-2e7b2bf9-8e27-43dd-ae7c-fca5d41b861c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914039030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3914039030
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.58193568
Short name T199
Test name
Test status
Simulation time 37996295 ps
CPU time 0.68 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 194376 kb
Host smart-9aca8440-1d93-4245-a84c-82104e2a5e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58193568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.58193568
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3438481490
Short name T506
Test name
Test status
Simulation time 131856663 ps
CPU time 1.29 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 195928 kb
Host smart-eea00d70-fee2-42ca-90a5-e849fddd6bda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438481490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3438481490
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.74253770
Short name T297
Test name
Test status
Simulation time 1620530332 ps
CPU time 6.33 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:43 PM PST 24
Peak memory 197928 kb
Host smart-16edc1f4-0f42-46a7-af6e-fb43974ff8be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74253770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rando
m_long_reg_writes_reg_reads.74253770
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4038870406
Short name T193
Test name
Test status
Simulation time 1105713522 ps
CPU time 1.49 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 198116 kb
Host smart-681f25f8-5846-4b57-94da-da0443704765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038870406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4038870406
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2530716342
Short name T24
Test name
Test status
Simulation time 77538002 ps
CPU time 1.37 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 196812 kb
Host smart-1c5464e7-c690-4b54-bbed-5e90d408e1e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530716342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2530716342
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2433676703
Short name T401
Test name
Test status
Simulation time 19652822293 ps
CPU time 131.24 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 198216 kb
Host smart-8e5d5870-f252-4c22-892d-5bb819157b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433676703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2433676703
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3138093974
Short name T406
Test name
Test status
Simulation time 22381574 ps
CPU time 0.58 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 194052 kb
Host smart-577f179f-3026-46a1-b46a-5d76a729e6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138093974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3138093974
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.696496874
Short name T485
Test name
Test status
Simulation time 83652047 ps
CPU time 0.73 seconds
Started Feb 25 01:43:36 PM PST 24
Finished Feb 25 01:43:37 PM PST 24
Peak memory 194284 kb
Host smart-6d70df28-c778-487f-8087-26709a08f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696496874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.696496874
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1999768507
Short name T333
Test name
Test status
Simulation time 502757771 ps
CPU time 16.06 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:56 PM PST 24
Peak memory 198212 kb
Host smart-3fe3c438-bcb4-45d6-963d-ba28a068b44a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999768507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1999768507
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4272130525
Short name T660
Test name
Test status
Simulation time 32537731 ps
CPU time 0.72 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 194720 kb
Host smart-3755a58b-a505-49c3-9781-5d085441a38c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272130525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4272130525
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2775454236
Short name T652
Test name
Test status
Simulation time 515958702 ps
CPU time 1.07 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:40 PM PST 24
Peak memory 196080 kb
Host smart-98130b61-9fde-4027-9852-b1706b063b0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775454236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2775454236
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1175847315
Short name T690
Test name
Test status
Simulation time 147381044 ps
CPU time 3.08 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:48 PM PST 24
Peak memory 198096 kb
Host smart-6edfa92b-28b3-4160-a2f6-ddec93e9101d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175847315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1175847315
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1993654449
Short name T50
Test name
Test status
Simulation time 319347835 ps
CPU time 2.5 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 198072 kb
Host smart-c1cbabc6-985a-49b2-a50e-bb9ce55a4afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993654449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1993654449
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2472617538
Short name T469
Test name
Test status
Simulation time 23760302 ps
CPU time 0.69 seconds
Started Feb 25 01:43:35 PM PST 24
Finished Feb 25 01:43:36 PM PST 24
Peak memory 194268 kb
Host smart-e7003700-2df0-49c9-86f5-b0f9d57324c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472617538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2472617538
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3527636796
Short name T340
Test name
Test status
Simulation time 25643533 ps
CPU time 0.7 seconds
Started Feb 25 01:43:41 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 195356 kb
Host smart-9efed479-c72b-4c6a-87e9-f122b2a83bba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527636796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3527636796
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.615279570
Short name T704
Test name
Test status
Simulation time 530342900 ps
CPU time 5.94 seconds
Started Feb 25 01:43:41 PM PST 24
Finished Feb 25 01:43:47 PM PST 24
Peak memory 198092 kb
Host smart-836530ea-911e-484b-a330-3bafa6cc323c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615279570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.615279570
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.791120975
Short name T356
Test name
Test status
Simulation time 146076587 ps
CPU time 0.9 seconds
Started Feb 25 01:43:37 PM PST 24
Finished Feb 25 01:43:38 PM PST 24
Peak memory 195472 kb
Host smart-9423cccd-899e-47a3-ae42-5c35bacbd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791120975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.791120975
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.431358959
Short name T162
Test name
Test status
Simulation time 39871382 ps
CPU time 1.18 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 195852 kb
Host smart-a84326ae-cd25-4938-bf16-b75563033884
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431358959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.431358959
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3334522989
Short name T530
Test name
Test status
Simulation time 6532970478 ps
CPU time 71.8 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:45:00 PM PST 24
Peak memory 198136 kb
Host smart-2819e906-c34d-4da3-9a15-111632b24ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334522989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3334522989
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1921874913
Short name T298
Test name
Test status
Simulation time 15545366 ps
CPU time 0.62 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 193912 kb
Host smart-9c87af4f-0199-41f6-b0cd-5989423279e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921874913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1921874913
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3388723394
Short name T488
Test name
Test status
Simulation time 19574175 ps
CPU time 0.75 seconds
Started Feb 25 01:43:44 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 194892 kb
Host smart-034b81df-2fba-467a-8220-5dd28eb42f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388723394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3388723394
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3899182294
Short name T299
Test name
Test status
Simulation time 770595112 ps
CPU time 21.46 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:44:02 PM PST 24
Peak memory 198024 kb
Host smart-1739136b-961f-45b0-bc61-ffdbb4e403bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899182294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3899182294
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1458330677
Short name T612
Test name
Test status
Simulation time 41684836 ps
CPU time 0.85 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 196636 kb
Host smart-30e45176-382b-4b3d-8795-0c254b13acc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458330677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1458330677
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3758349798
Short name T416
Test name
Test status
Simulation time 40211554 ps
CPU time 0.92 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 196016 kb
Host smart-df792e80-aa55-42f0-9a33-8f6aace45f00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758349798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3758349798
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.814591841
Short name T411
Test name
Test status
Simulation time 82817417 ps
CPU time 3.68 seconds
Started Feb 25 01:43:39 PM PST 24
Finished Feb 25 01:43:43 PM PST 24
Peak memory 198096 kb
Host smart-2f543576-5764-45d2-8c92-bacc8b372c6b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814591841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.814591841
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1596222509
Short name T662
Test name
Test status
Simulation time 357757447 ps
CPU time 3.76 seconds
Started Feb 25 01:43:48 PM PST 24
Finished Feb 25 01:43:52 PM PST 24
Peak memory 196848 kb
Host smart-a3874a5c-dd86-481f-988f-a76b72e65898
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596222509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1596222509
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2008560440
Short name T468
Test name
Test status
Simulation time 516651251 ps
CPU time 1.21 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 198080 kb
Host smart-599f0266-bed7-4f3c-936b-759e893186d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008560440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2008560440
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.937074422
Short name T105
Test name
Test status
Simulation time 35911696 ps
CPU time 0.77 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 195292 kb
Host smart-f2d1c094-6ac1-4b63-8b42-7dc65d165bb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937074422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.937074422
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3077653059
Short name T128
Test name
Test status
Simulation time 92996494 ps
CPU time 4.27 seconds
Started Feb 25 01:43:40 PM PST 24
Finished Feb 25 01:43:45 PM PST 24
Peak memory 197980 kb
Host smart-3e1b4c58-9295-4d75-8b82-59060d9b961c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077653059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3077653059
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1090538905
Short name T99
Test name
Test status
Simulation time 55199558 ps
CPU time 0.91 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 195456 kb
Host smart-dffe1471-14b5-4ff3-a278-02de2bc8c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090538905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1090538905
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1587091717
Short name T113
Test name
Test status
Simulation time 45068356 ps
CPU time 0.82 seconds
Started Feb 25 01:43:38 PM PST 24
Finished Feb 25 01:43:39 PM PST 24
Peak memory 195404 kb
Host smart-546e9872-60f6-4578-ada6-c179e4ccbcef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587091717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1587091717
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1547573143
Short name T403
Test name
Test status
Simulation time 10167176325 ps
CPU time 121.8 seconds
Started Feb 25 01:43:49 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 198200 kb
Host smart-64e70911-6fdf-432f-a0e4-414629febdd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547573143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1547573143
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.324248334
Short name T845
Test name
Test status
Simulation time 862631892 ps
CPU time 1.44 seconds
Started Feb 25 01:17:03 PM PST 24
Finished Feb 25 01:17:04 PM PST 24
Peak memory 196980 kb
Host smart-86c27123-fb86-4174-8127-92dc0c4ffe62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=324248334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.324248334
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207039102
Short name T934
Test name
Test status
Simulation time 126966742 ps
CPU time 1.03 seconds
Started Feb 25 01:17:09 PM PST 24
Finished Feb 25 01:17:10 PM PST 24
Peak memory 197064 kb
Host smart-d5d1af4a-b0b2-4950-96e8-5ce217bf17f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207039102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.207039102
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1544702173
Short name T853
Test name
Test status
Simulation time 65794667 ps
CPU time 0.99 seconds
Started Feb 25 01:17:05 PM PST 24
Finished Feb 25 01:17:06 PM PST 24
Peak memory 196200 kb
Host smart-570dc99e-1f61-47a9-bbcf-c08d4b55a891
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1544702173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1544702173
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077862822
Short name T926
Test name
Test status
Simulation time 36292643 ps
CPU time 0.89 seconds
Started Feb 25 01:17:02 PM PST 24
Finished Feb 25 01:17:03 PM PST 24
Peak memory 196492 kb
Host smart-cd82496d-ba39-4e60-92bb-2138225f933f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077862822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1077862822
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.972398025
Short name T871
Test name
Test status
Simulation time 330827925 ps
CPU time 1.38 seconds
Started Feb 25 01:17:16 PM PST 24
Finished Feb 25 01:17:18 PM PST 24
Peak memory 196044 kb
Host smart-444bc135-f0ac-4a3c-9e7d-58f7715fe98c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=972398025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.972398025
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206628442
Short name T892
Test name
Test status
Simulation time 702786912 ps
CPU time 0.94 seconds
Started Feb 25 01:17:13 PM PST 24
Finished Feb 25 01:17:14 PM PST 24
Peak memory 196988 kb
Host smart-a6d88727-ff65-490b-a4aa-db66894eb8b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206628442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1206628442
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1075381621
Short name T867
Test name
Test status
Simulation time 35537819 ps
CPU time 1.06 seconds
Started Feb 25 01:17:08 PM PST 24
Finished Feb 25 01:17:09 PM PST 24
Peak memory 196000 kb
Host smart-a14c4763-1daa-4746-81fc-4655e81307da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1075381621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1075381621
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2242972490
Short name T888
Test name
Test status
Simulation time 56655520 ps
CPU time 0.91 seconds
Started Feb 25 01:17:03 PM PST 24
Finished Feb 25 01:17:04 PM PST 24
Peak memory 196768 kb
Host smart-28fd8231-3a6c-40cc-b05d-d05b82b99b33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242972490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2242972490
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.792897209
Short name T885
Test name
Test status
Simulation time 41482050 ps
CPU time 1.21 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 197360 kb
Host smart-18bf21d4-844c-4252-8549-a89c76a16956
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=792897209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.792897209
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3251080472
Short name T843
Test name
Test status
Simulation time 40001076 ps
CPU time 1.03 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 196768 kb
Host smart-497e8c69-477a-4643-bf63-3db2193dab8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251080472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3251080472
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.397443663
Short name T904
Test name
Test status
Simulation time 81241903 ps
CPU time 1.46 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196076 kb
Host smart-802197d0-72ef-495b-a4dc-799b9269440e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=397443663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.397443663
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2622719461
Short name T900
Test name
Test status
Simulation time 40498286 ps
CPU time 1.13 seconds
Started Feb 25 01:17:17 PM PST 24
Finished Feb 25 01:17:19 PM PST 24
Peak memory 196256 kb
Host smart-96ffd849-2dc3-4792-8827-2ad8fda3602d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622719461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2622719461
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4018545243
Short name T924
Test name
Test status
Simulation time 199818918 ps
CPU time 1.1 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196364 kb
Host smart-a4f02f34-4305-4dce-a4c9-c8e094672561
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4018545243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4018545243
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.21765788
Short name T907
Test name
Test status
Simulation time 56610668 ps
CPU time 1.05 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196928 kb
Host smart-364d4d24-0fe9-46e5-a19e-0af3d12cef9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21765788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.21765788
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1878265137
Short name T906
Test name
Test status
Simulation time 34329243 ps
CPU time 0.92 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196052 kb
Host smart-14c236b5-cb71-43ba-a5f9-3682c55ccc79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1878265137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1878265137
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1918717419
Short name T854
Test name
Test status
Simulation time 195411032 ps
CPU time 1.08 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 198380 kb
Host smart-ceaebac7-aefc-4eb5-9998-0b7a49827bff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918717419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1918717419
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2217478939
Short name T840
Test name
Test status
Simulation time 363630012 ps
CPU time 1.1 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196904 kb
Host smart-b7b17aac-daa5-4488-946c-35088aba961c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2217478939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2217478939
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4190478969
Short name T868
Test name
Test status
Simulation time 129967096 ps
CPU time 1 seconds
Started Feb 25 01:17:17 PM PST 24
Finished Feb 25 01:17:18 PM PST 24
Peak memory 196916 kb
Host smart-1288858e-5449-4990-ac1e-32bbcef43a41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190478969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4190478969
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3258281508
Short name T862
Test name
Test status
Simulation time 115980503 ps
CPU time 0.99 seconds
Started Feb 25 01:17:17 PM PST 24
Finished Feb 25 01:17:18 PM PST 24
Peak memory 198456 kb
Host smart-e4aae26f-64b3-4df8-9f63-d9db3014cf09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3258281508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3258281508
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.644515780
Short name T851
Test name
Test status
Simulation time 968169428 ps
CPU time 1.42 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 197348 kb
Host smart-b0a2d398-a78b-4b7c-9201-c8767c228bc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644515780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.644515780
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.887689235
Short name T859
Test name
Test status
Simulation time 116177579 ps
CPU time 1.01 seconds
Started Feb 25 01:17:16 PM PST 24
Finished Feb 25 01:17:17 PM PST 24
Peak memory 196240 kb
Host smart-b909ba2b-0cdc-449b-a47e-bdb2f986dc54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=887689235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.887689235
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3219845696
Short name T879
Test name
Test status
Simulation time 720643896 ps
CPU time 1.08 seconds
Started Feb 25 01:17:16 PM PST 24
Finished Feb 25 01:17:17 PM PST 24
Peak memory 197140 kb
Host smart-e64e7fc9-210c-4805-82c0-31340f9bf849
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219845696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3219845696
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3030499801
Short name T880
Test name
Test status
Simulation time 647659045 ps
CPU time 1.25 seconds
Started Feb 25 01:17:17 PM PST 24
Finished Feb 25 01:17:18 PM PST 24
Peak memory 196888 kb
Host smart-cee1915c-1e4f-4f35-8ae4-2b4f9dec22d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3030499801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3030499801
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1133666477
Short name T872
Test name
Test status
Simulation time 37903934 ps
CPU time 1.18 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 197164 kb
Host smart-9cdde215-0f45-42f8-a059-d184c256804c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133666477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1133666477
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3428113732
Short name T836
Test name
Test status
Simulation time 90378161 ps
CPU time 0.97 seconds
Started Feb 25 01:17:09 PM PST 24
Finished Feb 25 01:17:10 PM PST 24
Peak memory 196700 kb
Host smart-05e2791f-af57-4d7b-a60c-16e0ac0d9a4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3428113732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3428113732
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197360352
Short name T895
Test name
Test status
Simulation time 84834866 ps
CPU time 0.79 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 195760 kb
Host smart-723828ca-3266-4bf6-91a4-c92eca10c615
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197360352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4197360352
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2144200615
Short name T933
Test name
Test status
Simulation time 296841008 ps
CPU time 1.53 seconds
Started Feb 25 01:17:18 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 198420 kb
Host smart-7981515e-3d0e-4eaa-aa9a-53c03279a7be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2144200615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2144200615
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348358733
Short name T864
Test name
Test status
Simulation time 43856241 ps
CPU time 0.97 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 196988 kb
Host smart-45ceb075-da1d-4308-bfaf-2363032cb4b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348358733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1348358733
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2096848954
Short name T935
Test name
Test status
Simulation time 90932846 ps
CPU time 0.76 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 195716 kb
Host smart-a7b126ac-1fd2-423f-af53-f874c64439e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2096848954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2096848954
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854620633
Short name T875
Test name
Test status
Simulation time 95540244 ps
CPU time 0.91 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:20 PM PST 24
Peak memory 195956 kb
Host smart-46d1c7e8-4655-4311-b192-3a6c70155156
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854620633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.854620633
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1868316105
Short name T910
Test name
Test status
Simulation time 333679552 ps
CPU time 1.28 seconds
Started Feb 25 01:17:21 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 196872 kb
Host smart-2a0a3ada-081e-4b48-9c04-503681354ecb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1868316105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1868316105
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1683009183
Short name T865
Test name
Test status
Simulation time 165538150 ps
CPU time 1.32 seconds
Started Feb 25 01:17:25 PM PST 24
Finished Feb 25 01:17:27 PM PST 24
Peak memory 196760 kb
Host smart-cc3aa048-a6f6-4ef6-8789-a1a7d238c1bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683009183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1683009183
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2343664307
Short name T902
Test name
Test status
Simulation time 42186334 ps
CPU time 0.91 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 197100 kb
Host smart-b8c3857d-7e75-44dd-a2fd-70b79c2e4d50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2343664307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2343664307
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2607181480
Short name T923
Test name
Test status
Simulation time 28617774 ps
CPU time 0.98 seconds
Started Feb 25 01:17:23 PM PST 24
Finished Feb 25 01:17:25 PM PST 24
Peak memory 197024 kb
Host smart-90168fd9-589e-4125-b1d2-7b6abb1b4cbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607181480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2607181480
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3815155227
Short name T913
Test name
Test status
Simulation time 237939035 ps
CPU time 1.17 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 198392 kb
Host smart-9df30a94-f586-454a-abd8-d9ea410637dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3815155227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3815155227
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1006966663
Short name T844
Test name
Test status
Simulation time 74019337 ps
CPU time 1.39 seconds
Started Feb 25 01:17:24 PM PST 24
Finished Feb 25 01:17:26 PM PST 24
Peak memory 196052 kb
Host smart-f9220c52-16e4-43ff-8f54-31491a963992
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006966663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1006966663
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.55536194
Short name T841
Test name
Test status
Simulation time 272658529 ps
CPU time 1.14 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 197100 kb
Host smart-98320bdc-96cb-40a3-8344-80ee4d73351b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=55536194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.55536194
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566285359
Short name T878
Test name
Test status
Simulation time 89198562 ps
CPU time 0.75 seconds
Started Feb 25 01:17:24 PM PST 24
Finished Feb 25 01:17:26 PM PST 24
Peak memory 195704 kb
Host smart-43efe768-2565-4974-b105-a49b35342f08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566285359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1566285359
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1684181989
Short name T920
Test name
Test status
Simulation time 52975442 ps
CPU time 0.91 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:24 PM PST 24
Peak memory 196820 kb
Host smart-440eb78d-2c93-4ad5-9b81-6a34f27aa2c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1684181989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1684181989
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206155969
Short name T925
Test name
Test status
Simulation time 312111002 ps
CPU time 1.37 seconds
Started Feb 25 01:17:21 PM PST 24
Finished Feb 25 01:17:22 PM PST 24
Peak memory 197068 kb
Host smart-d6948a22-09a5-483b-956c-245b288bbfc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206155969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1206155969
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4280180095
Short name T838
Test name
Test status
Simulation time 190421408 ps
CPU time 1.31 seconds
Started Feb 25 01:17:21 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 197272 kb
Host smart-fdb54d7b-44ee-4d4d-9ab5-a4c79f9baf6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4280180095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4280180095
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237662177
Short name T847
Test name
Test status
Simulation time 93245431 ps
CPU time 1.17 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 196304 kb
Host smart-0e62a390-f75f-4163-9272-56f32608c4fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237662177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2237662177
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4174570626
Short name T849
Test name
Test status
Simulation time 45866236 ps
CPU time 1.35 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 197184 kb
Host smart-821e880b-2bb9-47c3-88d7-7b48be742cb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4174570626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4174570626
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3628575908
Short name T927
Test name
Test status
Simulation time 158025914 ps
CPU time 1.18 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 196104 kb
Host smart-4aad5655-be4e-45b0-8a73-0ab0d205a962
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628575908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3628575908
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4074422819
Short name T917
Test name
Test status
Simulation time 50568154 ps
CPU time 1.46 seconds
Started Feb 25 01:17:25 PM PST 24
Finished Feb 25 01:17:27 PM PST 24
Peak memory 197124 kb
Host smart-49721f62-280f-4a24-af64-a4795cd65fda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4074422819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4074422819
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3426201872
Short name T930
Test name
Test status
Simulation time 324032561 ps
CPU time 1.43 seconds
Started Feb 25 01:17:25 PM PST 24
Finished Feb 25 01:17:27 PM PST 24
Peak memory 198360 kb
Host smart-a7a214ed-91ca-4fa4-8d97-f46c454ef157
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426201872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3426201872
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.23398959
Short name T919
Test name
Test status
Simulation time 67130465 ps
CPU time 1 seconds
Started Feb 25 01:17:11 PM PST 24
Finished Feb 25 01:17:12 PM PST 24
Peak memory 196688 kb
Host smart-98f6eb82-2d3b-41ce-ab7d-b2bee81add42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=23398959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.23398959
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.781166776
Short name T876
Test name
Test status
Simulation time 63747199 ps
CPU time 1.16 seconds
Started Feb 25 01:17:03 PM PST 24
Finished Feb 25 01:17:05 PM PST 24
Peak memory 196076 kb
Host smart-8d4aec3d-a20c-4dbc-b5d3-fe31b7e33182
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781166776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.781166776
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1018242460
Short name T914
Test name
Test status
Simulation time 747569803 ps
CPU time 1.25 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:28 PM PST 24
Peak memory 196284 kb
Host smart-985362c6-1845-4530-98f0-8f0fbeb7ac3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1018242460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1018242460
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2924437528
Short name T886
Test name
Test status
Simulation time 43798146 ps
CPU time 1.14 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 196232 kb
Host smart-640bd3e0-5bd8-47e7-8832-d86f4ea18f31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924437528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2924437528
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2423546207
Short name T839
Test name
Test status
Simulation time 184646670 ps
CPU time 1.02 seconds
Started Feb 25 01:17:23 PM PST 24
Finished Feb 25 01:17:25 PM PST 24
Peak memory 196272 kb
Host smart-42f81171-ca78-4103-8e09-dd71830e1b48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2423546207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2423546207
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1790495440
Short name T858
Test name
Test status
Simulation time 87911940 ps
CPU time 1.58 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 197104 kb
Host smart-88badc53-0921-4705-8e07-06a9014c0b76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790495440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1790495440
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2160374511
Short name T842
Test name
Test status
Simulation time 143859623 ps
CPU time 1.46 seconds
Started Feb 25 01:17:23 PM PST 24
Finished Feb 25 01:17:25 PM PST 24
Peak memory 197096 kb
Host smart-5d2d7561-e5c8-46cd-9dde-251ba86dee3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2160374511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2160374511
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812166937
Short name T877
Test name
Test status
Simulation time 49489519 ps
CPU time 1.12 seconds
Started Feb 25 01:17:23 PM PST 24
Finished Feb 25 01:17:25 PM PST 24
Peak memory 197028 kb
Host smart-36b472be-2bbd-49b9-bece-5d8bc1c3ade2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812166937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1812166937
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2684454685
Short name T855
Test name
Test status
Simulation time 137610773 ps
CPU time 1.27 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:23 PM PST 24
Peak memory 197608 kb
Host smart-7d891bd6-48c0-45ad-a235-f167f8a4ff16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2684454685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2684454685
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545279912
Short name T837
Test name
Test status
Simulation time 286656549 ps
CPU time 1.28 seconds
Started Feb 25 01:17:28 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 197048 kb
Host smart-7c45549c-a540-4261-94a9-440e88ff8e26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545279912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.545279912
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1117823080
Short name T860
Test name
Test status
Simulation time 95141181 ps
CPU time 0.87 seconds
Started Feb 25 01:17:25 PM PST 24
Finished Feb 25 01:17:26 PM PST 24
Peak memory 195756 kb
Host smart-797ab47e-69dd-497e-acf0-0aa0b1049ea9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1117823080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1117823080
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3579208144
Short name T893
Test name
Test status
Simulation time 417451442 ps
CPU time 1.13 seconds
Started Feb 25 01:17:22 PM PST 24
Finished Feb 25 01:17:24 PM PST 24
Peak memory 198408 kb
Host smart-94c44e3f-e421-4b48-bd58-4fde9d949207
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579208144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3579208144
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2351930009
Short name T891
Test name
Test status
Simulation time 287515170 ps
CPU time 1.13 seconds
Started Feb 25 01:17:23 PM PST 24
Finished Feb 25 01:17:25 PM PST 24
Peak memory 197156 kb
Host smart-9c68ab52-3150-4549-88d0-6ee9ffa25fa1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2351930009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2351930009
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2021027230
Short name T894
Test name
Test status
Simulation time 59265837 ps
CPU time 1.48 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 198448 kb
Host smart-74fe7804-f53e-41f6-bcb8-3cc45f721780
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021027230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2021027230
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1176215791
Short name T897
Test name
Test status
Simulation time 94058706 ps
CPU time 1.02 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 197028 kb
Host smart-c0f4679b-0a2f-430e-bf83-c6b1bbaa59f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1176215791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1176215791
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581483998
Short name T896
Test name
Test status
Simulation time 45902803 ps
CPU time 0.77 seconds
Started Feb 25 01:17:25 PM PST 24
Finished Feb 25 01:17:26 PM PST 24
Peak memory 195648 kb
Host smart-d53d86ad-9319-4caa-a88b-7477dc2fa3c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581483998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.581483998
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.448840150
Short name T889
Test name
Test status
Simulation time 44035293 ps
CPU time 0.92 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 195836 kb
Host smart-e56a112b-d8ac-431e-93f3-cfcc4dab6c5f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=448840150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.448840150
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.359361806
Short name T873
Test name
Test status
Simulation time 142312112 ps
CPU time 1.11 seconds
Started Feb 25 01:17:26 PM PST 24
Finished Feb 25 01:17:28 PM PST 24
Peak memory 196776 kb
Host smart-ada41548-687a-4683-9c41-bade8ea9cc48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359361806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.359361806
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1096789314
Short name T852
Test name
Test status
Simulation time 38046434 ps
CPU time 1.08 seconds
Started Feb 25 01:17:28 PM PST 24
Finished Feb 25 01:17:30 PM PST 24
Peak memory 196192 kb
Host smart-fea699ef-28a2-4962-9418-9eeef06bfd5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1096789314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1096789314
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785403028
Short name T928
Test name
Test status
Simulation time 960722390 ps
CPU time 1.08 seconds
Started Feb 25 01:17:27 PM PST 24
Finished Feb 25 01:17:29 PM PST 24
Peak memory 196288 kb
Host smart-1de22253-295c-4f06-839f-70da4843b314
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785403028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1785403028
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1018525923
Short name T850
Test name
Test status
Simulation time 83615856 ps
CPU time 1.41 seconds
Started Feb 25 01:17:36 PM PST 24
Finished Feb 25 01:17:38 PM PST 24
Peak memory 198368 kb
Host smart-c1e9cafa-a660-4011-9c79-eadcd7d30a84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1018525923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1018525923
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.256152434
Short name T909
Test name
Test status
Simulation time 125344595 ps
CPU time 0.94 seconds
Started Feb 25 01:17:35 PM PST 24
Finished Feb 25 01:17:36 PM PST 24
Peak memory 195896 kb
Host smart-1a85453e-c912-4806-b8dd-92f152947c84
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256152434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.256152434
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1002859535
Short name T912
Test name
Test status
Simulation time 58421032 ps
CPU time 1.15 seconds
Started Feb 25 01:17:04 PM PST 24
Finished Feb 25 01:17:05 PM PST 24
Peak memory 196328 kb
Host smart-0075c1c7-eaec-4348-b229-b442e08d0883
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1002859535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1002859535
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1200821460
Short name T921
Test name
Test status
Simulation time 157855577 ps
CPU time 0.93 seconds
Started Feb 25 01:17:06 PM PST 24
Finished Feb 25 01:17:07 PM PST 24
Peak memory 197528 kb
Host smart-db8ed540-2341-45f7-b31d-cdfb34dd3718
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200821460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1200821460
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3083028090
Short name T863
Test name
Test status
Simulation time 40100925 ps
CPU time 0.74 seconds
Started Feb 25 01:17:33 PM PST 24
Finished Feb 25 01:17:34 PM PST 24
Peak memory 194776 kb
Host smart-016d7e2a-c7ad-47be-9caf-1d8852a44afd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3083028090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3083028090
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1661315031
Short name T887
Test name
Test status
Simulation time 61551130 ps
CPU time 1.31 seconds
Started Feb 25 01:17:32 PM PST 24
Finished Feb 25 01:17:34 PM PST 24
Peak memory 196356 kb
Host smart-f09117f7-cee2-46e7-b06f-6a894debc564
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661315031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1661315031
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4278689492
Short name T874
Test name
Test status
Simulation time 51913770 ps
CPU time 1.55 seconds
Started Feb 25 01:17:33 PM PST 24
Finished Feb 25 01:17:35 PM PST 24
Peak memory 198428 kb
Host smart-b511c57f-1d3a-41e2-a05f-b835939a6e3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4278689492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4278689492
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3158576944
Short name T929
Test name
Test status
Simulation time 28209783 ps
CPU time 0.86 seconds
Started Feb 25 01:17:38 PM PST 24
Finished Feb 25 01:17:39 PM PST 24
Peak memory 195788 kb
Host smart-bdfe1360-02e3-4e78-915b-b85caddffbfd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158576944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3158576944
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.94856172
Short name T869
Test name
Test status
Simulation time 31742218 ps
CPU time 1.02 seconds
Started Feb 25 01:17:36 PM PST 24
Finished Feb 25 01:17:37 PM PST 24
Peak memory 197144 kb
Host smart-c4bb314a-e3ba-4267-bd63-10cc11f92285
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=94856172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.94856172
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2246312975
Short name T901
Test name
Test status
Simulation time 33759298 ps
CPU time 0.79 seconds
Started Feb 25 01:17:35 PM PST 24
Finished Feb 25 01:17:37 PM PST 24
Peak memory 196428 kb
Host smart-e256252b-f64a-497c-a30f-a08c6a8bef63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246312975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2246312975
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3132817504
Short name T881
Test name
Test status
Simulation time 44301098 ps
CPU time 0.96 seconds
Started Feb 25 01:17:35 PM PST 24
Finished Feb 25 01:17:36 PM PST 24
Peak memory 196248 kb
Host smart-cddc7514-35b2-454d-a222-76091597b9e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3132817504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3132817504
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705642348
Short name T905
Test name
Test status
Simulation time 88497905 ps
CPU time 1.4 seconds
Started Feb 25 01:17:33 PM PST 24
Finished Feb 25 01:17:35 PM PST 24
Peak memory 196816 kb
Host smart-2ae1b655-7525-4f1c-a750-cac6d18c99db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705642348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2705642348
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1934605103
Short name T861
Test name
Test status
Simulation time 1096868465 ps
CPU time 1.08 seconds
Started Feb 25 01:17:33 PM PST 24
Finished Feb 25 01:17:34 PM PST 24
Peak memory 196308 kb
Host smart-c1878b55-fd48-4508-8820-87b0e9949257
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1934605103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1934605103
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3752845667
Short name T890
Test name
Test status
Simulation time 49456180 ps
CPU time 1.02 seconds
Started Feb 25 01:17:32 PM PST 24
Finished Feb 25 01:17:33 PM PST 24
Peak memory 198396 kb
Host smart-cd41342f-7fbc-4337-ac6a-5ca68594709b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752845667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3752845667
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1803881131
Short name T866
Test name
Test status
Simulation time 278457325 ps
CPU time 1.26 seconds
Started Feb 25 01:17:37 PM PST 24
Finished Feb 25 01:17:39 PM PST 24
Peak memory 197236 kb
Host smart-21c0bbb5-6791-4f55-a16d-a6d1412c4639
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1803881131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1803881131
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2660148119
Short name T903
Test name
Test status
Simulation time 41471990 ps
CPU time 1.01 seconds
Started Feb 25 01:17:36 PM PST 24
Finished Feb 25 01:17:37 PM PST 24
Peak memory 196992 kb
Host smart-ad12bae1-ba8a-4d62-8894-3590bbac0ffc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660148119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2660148119
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2597955335
Short name T898
Test name
Test status
Simulation time 43912663 ps
CPU time 1.01 seconds
Started Feb 25 01:17:34 PM PST 24
Finished Feb 25 01:17:35 PM PST 24
Peak memory 196964 kb
Host smart-2d149034-56fe-4765-8bcd-eb80a0db3d35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2597955335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2597955335
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4247434061
Short name T882
Test name
Test status
Simulation time 208909614 ps
CPU time 1.4 seconds
Started Feb 25 01:17:36 PM PST 24
Finished Feb 25 01:17:38 PM PST 24
Peak memory 198420 kb
Host smart-a3204393-4309-4cf4-8377-fa6852b08f2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247434061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4247434061
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2840841950
Short name T856
Test name
Test status
Simulation time 144130646 ps
CPU time 1.26 seconds
Started Feb 25 01:17:33 PM PST 24
Finished Feb 25 01:17:35 PM PST 24
Peak memory 196916 kb
Host smart-72a54e7f-efd3-40cc-bdbf-78d850790929
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2840841950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2840841950
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2193002070
Short name T911
Test name
Test status
Simulation time 55857657 ps
CPU time 1.01 seconds
Started Feb 25 01:17:36 PM PST 24
Finished Feb 25 01:17:37 PM PST 24
Peak memory 195952 kb
Host smart-fbcfa19f-c431-4db8-9d7e-16ce9081946f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193002070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2193002070
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4013873198
Short name T884
Test name
Test status
Simulation time 286264419 ps
CPU time 1.16 seconds
Started Feb 25 01:17:32 PM PST 24
Finished Feb 25 01:17:34 PM PST 24
Peak memory 196228 kb
Host smart-f3d72121-9e47-46e7-af18-d696f5f68615
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4013873198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4013873198
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931679529
Short name T848
Test name
Test status
Simulation time 69514932 ps
CPU time 1.01 seconds
Started Feb 25 01:17:38 PM PST 24
Finished Feb 25 01:17:39 PM PST 24
Peak memory 196464 kb
Host smart-d749b1b0-95e0-4d52-b731-2a16db7e7cc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931679529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3931679529
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.451974661
Short name T916
Test name
Test status
Simulation time 107281913 ps
CPU time 1.09 seconds
Started Feb 25 01:17:44 PM PST 24
Finished Feb 25 01:17:45 PM PST 24
Peak memory 197088 kb
Host smart-8102732e-215f-4c72-9e79-9172e4c18126
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=451974661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.451974661
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3321726213
Short name T899
Test name
Test status
Simulation time 54369429 ps
CPU time 1.12 seconds
Started Feb 25 01:17:46 PM PST 24
Finished Feb 25 01:17:47 PM PST 24
Peak memory 197160 kb
Host smart-2a3381b4-25c6-4ad0-8b1c-fff4c302b865
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321726213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3321726213
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3264135479
Short name T883
Test name
Test status
Simulation time 140093380 ps
CPU time 1.16 seconds
Started Feb 25 01:17:03 PM PST 24
Finished Feb 25 01:17:04 PM PST 24
Peak memory 196336 kb
Host smart-7ec2f661-15ec-4853-b731-a747ba055057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3264135479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3264135479
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781420243
Short name T931
Test name
Test status
Simulation time 36333367 ps
CPU time 1.06 seconds
Started Feb 25 01:17:04 PM PST 24
Finished Feb 25 01:17:05 PM PST 24
Peak memory 196052 kb
Host smart-a326e5ce-deb4-4369-82b6-9c5841b2f2b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781420243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1781420243
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2122616849
Short name T915
Test name
Test status
Simulation time 44248185 ps
CPU time 1.2 seconds
Started Feb 25 01:17:19 PM PST 24
Finished Feb 25 01:17:21 PM PST 24
Peak memory 196340 kb
Host smart-9a44ad8f-d722-4ad3-9d7c-bb4814807b26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2122616849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2122616849
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998472329
Short name T857
Test name
Test status
Simulation time 43164902 ps
CPU time 0.85 seconds
Started Feb 25 01:17:11 PM PST 24
Finished Feb 25 01:17:12 PM PST 24
Peak memory 195828 kb
Host smart-bbb71612-1ed0-4214-92e6-ac0f49f730f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998472329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3998472329
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4057000161
Short name T846
Test name
Test status
Simulation time 33744730 ps
CPU time 0.99 seconds
Started Feb 25 01:17:05 PM PST 24
Finished Feb 25 01:17:06 PM PST 24
Peak memory 196968 kb
Host smart-51871dd0-8235-4ab4-aba1-2717b31899a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4057000161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4057000161
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2706685665
Short name T870
Test name
Test status
Simulation time 310698794 ps
CPU time 1.04 seconds
Started Feb 25 01:17:03 PM PST 24
Finished Feb 25 01:17:04 PM PST 24
Peak memory 197000 kb
Host smart-1cd0bbe1-cd5b-4a35-af1a-7314929087ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706685665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2706685665
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3076181731
Short name T908
Test name
Test status
Simulation time 129238343 ps
CPU time 1.25 seconds
Started Feb 25 01:17:10 PM PST 24
Finished Feb 25 01:17:12 PM PST 24
Peak memory 198636 kb
Host smart-8011063a-03c1-4e10-9e22-1a6f9fc075d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3076181731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3076181731
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880165417
Short name T932
Test name
Test status
Simulation time 388946667 ps
CPU time 1.29 seconds
Started Feb 25 01:17:04 PM PST 24
Finished Feb 25 01:17:06 PM PST 24
Peak memory 197200 kb
Host smart-d0c93365-9734-45cc-b89a-f7e9b9ce6d37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880165417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2880165417
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2073273655
Short name T918
Test name
Test status
Simulation time 71359931 ps
CPU time 1.2 seconds
Started Feb 25 01:17:10 PM PST 24
Finished Feb 25 01:17:11 PM PST 24
Peak memory 196256 kb
Host smart-50e097a0-4049-4361-90fd-ef2d48323278
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2073273655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2073273655
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2143145656
Short name T922
Test name
Test status
Simulation time 48050954 ps
CPU time 0.98 seconds
Started Feb 25 01:17:04 PM PST 24
Finished Feb 25 01:17:06 PM PST 24
Peak memory 197012 kb
Host smart-a3d25b3c-ad07-4796-99ef-703f90cbdf04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143145656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2143145656
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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