Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3979447	1			T22	1		T23	47		T24	123
all_pins[1]	3979447	1			T22	1		T23	47		T24	123
all_pins[2]	3979447	1			T22	1		T23	47		T24	123
all_pins[3]	3979447	1			T22	1		T23	47		T24	123
all_pins[4]	3979447	1			T22	1		T23	47		T24	123
all_pins[5]	3979447	1			T22	1		T23	47		T24	123
all_pins[6]	3979447	1			T22	1		T23	47		T24	123
all_pins[7]	3979447	1			T22	1		T23	47		T24	123
all_pins[8]	3979447	1			T22	1		T23	47		T24	123
all_pins[9]	3979447	1			T22	1		T23	47		T24	123
all_pins[10]	3979447	1			T22	1		T23	47		T24	123
all_pins[11]	3979447	1			T22	1		T23	47		T24	123
all_pins[12]	3979447	1			T22	1		T23	47		T24	123
all_pins[13]	3979447	1			T22	1		T23	47		T24	123
all_pins[14]	3979447	1			T22	1		T23	47		T24	123
all_pins[15]	3979447	1			T22	1		T23	47		T24	123
all_pins[16]	3979447	1			T22	1		T23	47		T24	123
all_pins[17]	3979447	1			T22	1		T23	47		T24	123
all_pins[18]	3979447	1			T22	1		T23	47		T24	123
all_pins[19]	3979447	1			T22	1		T23	47		T24	123
all_pins[20]	3979447	1			T22	1		T23	47		T24	123
all_pins[21]	3979447	1			T22	1		T23	47		T24	123
all_pins[22]	3979447	1			T22	1		T23	47		T24	123
all_pins[23]	3979447	1			T22	1		T23	47		T24	123
all_pins[24]	3979447	1			T22	1		T23	47		T24	123
all_pins[25]	3979447	1			T22	1		T23	47		T24	123
all_pins[26]	3979447	1			T22	1		T23	47		T24	123
all_pins[27]	3979447	1			T22	1		T23	47		T24	123
all_pins[28]	3979447	1			T22	1		T23	47		T24	123
all_pins[29]	3979447	1			T22	1		T23	47		T24	123
all_pins[30]	3979447	1			T22	1		T23	47		T24	123
all_pins[31]	3979447	1			T22	1		T23	47		T24	123

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	79086674	1			T22	32		T23	814		T24	2678
values[0x1]	48255630	1			T23	690		T24	1258		T25	291636
transitions[0x0=>0x1]	28895480	1			T23	363		T24	858		T25	174459
transitions[0x1=>0x0]	28895330	1			T23	363		T24	858		T25	174459

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2470327	1			T22	1		T23	27		T24	73
all_pins[0]	values[0x1]	1509120	1			T23	20		T24	50		T25	92005
all_pins[0]	transitions[0x0=>0x1]	933406	1			T23	3		T24	25		T25	57162
all_pins[0]	transitions[0x1=>0x0]	931982	1			T23	16		T24	29		T25	55614
all_pins[1]	values[0x0]	2471635	1			T22	1		T23	27		T24	83
all_pins[1]	values[0x1]	1507812	1			T23	20		T24	40		T25	90337
all_pins[1]	transitions[0x0=>0x1]	901992	1			T23	10		T24	27		T25	53334
all_pins[1]	transitions[0x1=>0x0]	903300	1			T23	10		T24	37		T25	55002
all_pins[2]	values[0x0]	2471658	1			T22	1		T23	27		T24	105
all_pins[2]	values[0x1]	1507789	1			T23	20		T24	18		T25	90455
all_pins[2]	transitions[0x0=>0x1]	901748	1			T23	13		T24	12		T25	54244
all_pins[2]	transitions[0x1=>0x0]	901771	1			T23	13		T24	34		T25	54126
all_pins[3]	values[0x0]	2473190	1			T22	1		T23	24		T24	91
all_pins[3]	values[0x1]	1506257	1			T23	23		T24	32		T25	91003
all_pins[3]	transitions[0x0=>0x1]	903032	1			T23	13		T24	21		T25	54815
all_pins[3]	transitions[0x1=>0x0]	904564	1			T23	10		T24	7		T25	54267
all_pins[4]	values[0x0]	2473598	1			T22	1		T23	17		T24	84
all_pins[4]	values[0x1]	1505849	1			T23	30		T24	39		T25	91611
all_pins[4]	transitions[0x0=>0x1]	900262	1			T23	18		T24	31		T25	54764
all_pins[4]	transitions[0x1=>0x0]	900670	1			T23	11		T24	24		T25	54156
all_pins[5]	values[0x0]	2472014	1			T22	1		T23	32		T24	88
all_pins[5]	values[0x1]	1507433	1			T23	15		T24	35		T25	90165
all_pins[5]	transitions[0x0=>0x1]	905915	1			T23	6		T24	27		T25	53652
all_pins[5]	transitions[0x1=>0x0]	904331	1			T23	21		T24	31		T25	55098
all_pins[6]	values[0x0]	2475251	1			T22	1		T23	22		T24	91
all_pins[6]	values[0x1]	1504196	1			T23	25		T24	32		T25	89968
all_pins[6]	transitions[0x0=>0x1]	899315	1			T23	20		T24	23		T25	53752
all_pins[6]	transitions[0x1=>0x0]	902552	1			T23	10		T24	26		T25	53949
all_pins[7]	values[0x0]	2468855	1			T22	1		T23	26		T24	88
all_pins[7]	values[0x1]	1510592	1			T23	21		T24	35		T25	91254
all_pins[7]	transitions[0x0=>0x1]	905522	1			T23	11		T24	29		T25	55135
all_pins[7]	transitions[0x1=>0x0]	899126	1			T23	15		T24	26		T25	53849
all_pins[8]	values[0x0]	2474261	1			T22	1		T23	27		T24	65
all_pins[8]	values[0x1]	1505186	1			T23	20		T24	58		T25	92340
all_pins[8]	transitions[0x0=>0x1]	898794	1			T23	10		T24	42		T25	55549
all_pins[8]	transitions[0x1=>0x0]	904200	1			T23	11		T24	19		T25	54463
all_pins[9]	values[0x0]	2467060	1			T22	1		T23	30		T24	71
all_pins[9]	values[0x1]	1512387	1			T23	17		T24	52		T25	92077
all_pins[9]	transitions[0x0=>0x1]	907385	1			T23	10		T24	32		T25	54808
all_pins[9]	transitions[0x1=>0x0]	900184	1			T23	13		T24	38		T25	55071
all_pins[10]	values[0x0]	2476010	1			T22	1		T23	22		T24	81
all_pins[10]	values[0x1]	1503437	1			T23	25		T24	42		T25	91881
all_pins[10]	transitions[0x0=>0x1]	897312	1			T23	12		T24	30		T25	54523
all_pins[10]	transitions[0x1=>0x0]	906262	1			T23	4		T24	40		T25	54719
all_pins[11]	values[0x0]	2472947	1			T22	1		T23	23		T24	93
all_pins[11]	values[0x1]	1506500	1			T23	24		T24	30		T25	91396
all_pins[11]	transitions[0x0=>0x1]	902823	1			T23	10		T24	15		T25	54027
all_pins[11]	transitions[0x1=>0x0]	899760	1			T23	11		T24	27		T25	54512
all_pins[12]	values[0x0]	2468051	1			T22	1		T23	24		T24	74
all_pins[12]	values[0x1]	1511396	1			T23	23		T24	49		T25	91038
all_pins[12]	transitions[0x0=>0x1]	903515	1			T23	10		T24	33		T25	54172
all_pins[12]	transitions[0x1=>0x0]	898619	1			T23	11		T24	14		T25	54530
all_pins[13]	values[0x0]	2470695	1			T22	1		T23	24		T24	91
all_pins[13]	values[0x1]	1508752	1			T23	23		T24	32		T25	92781
all_pins[13]	transitions[0x0=>0x1]	901232	1			T23	14		T24	16		T25	55721
all_pins[13]	transitions[0x1=>0x0]	903876	1			T23	14		T24	33		T25	53978
all_pins[14]	values[0x0]	2474465	1			T22	1		T23	25		T24	77
all_pins[14]	values[0x1]	1504982	1			T23	22		T24	46		T25	90196
all_pins[14]	transitions[0x0=>0x1]	900485	1			T23	9		T24	27		T25	53841
all_pins[14]	transitions[0x1=>0x0]	904255	1			T23	10		T24	13		T25	56426
all_pins[15]	values[0x0]	2471573	1			T22	1		T23	23		T24	80
all_pins[15]	values[0x1]	1507874	1			T23	24		T24	43		T25	90865
all_pins[15]	transitions[0x0=>0x1]	905390	1			T23	11		T24	21		T25	54430
all_pins[15]	transitions[0x1=>0x0]	902498	1			T23	9		T24	24		T25	53761
all_pins[16]	values[0x0]	2477765	1			T22	1		T23	29		T24	82
all_pins[16]	values[0x1]	1501682	1			T23	18		T24	41		T25	91908
all_pins[16]	transitions[0x0=>0x1]	897867	1			T23	7		T24	25		T25	54434
all_pins[16]	transitions[0x1=>0x0]	904059	1			T23	13		T24	27		T25	53391
all_pins[17]	values[0x0]	2469571	1			T22	1		T23	26		T24	75
all_pins[17]	values[0x1]	1509876	1			T23	21		T24	48		T25	91473
all_pins[17]	transitions[0x0=>0x1]	903322	1			T23	12		T24	34		T25	54530
all_pins[17]	transitions[0x1=>0x0]	895128	1			T23	9		T24	27		T25	54965
all_pins[18]	values[0x0]	2466247	1			T22	1		T23	25		T24	97
all_pins[18]	values[0x1]	1513200	1			T23	22		T24	26		T25	91029
all_pins[18]	transitions[0x0=>0x1]	904366	1			T23	10		T24	14		T25	53989
all_pins[18]	transitions[0x1=>0x0]	901042	1			T23	9		T24	36		T25	54433
all_pins[19]	values[0x0]	2475120	1			T22	1		T23	26		T24	101
all_pins[19]	values[0x1]	1504327	1			T23	21		T24	22		T25	91132
all_pins[19]	transitions[0x0=>0x1]	896990	1			T23	9		T24	17		T25	54537
all_pins[19]	transitions[0x1=>0x0]	905863	1			T23	10		T24	21		T25	54434
all_pins[20]	values[0x0]	2475070	1			T22	1		T23	20		T24	86
all_pins[20]	values[0x1]	1504377	1			T23	27		T24	37		T25	90618
all_pins[20]	transitions[0x0=>0x1]	901407	1			T23	15		T24	32		T25	53939
all_pins[20]	transitions[0x1=>0x0]	901357	1			T23	9		T24	17		T25	54453
all_pins[21]	values[0x0]	2474312	1			T22	1		T23	23		T24	94
all_pins[21]	values[0x1]	1505135	1			T23	24		T24	29		T25	90320
all_pins[21]	transitions[0x0=>0x1]	901797	1			T23	13		T24	21		T25	54361
all_pins[21]	transitions[0x1=>0x0]	901039	1			T23	16		T24	29		T25	54659
all_pins[22]	values[0x0]	2465398	1			T22	1		T23	31		T24	58
all_pins[22]	values[0x1]	1514049	1			T23	16		T24	65		T25	91726
all_pins[22]	transitions[0x0=>0x1]	905831	1			T23	3		T24	52		T25	55435
all_pins[22]	transitions[0x1=>0x0]	896917	1			T23	11		T24	16		T25	54029
all_pins[23]	values[0x0]	2468477	1			T22	1		T23	24		T24	83
all_pins[23]	values[0x1]	1510970	1			T23	23		T24	40		T25	91299
all_pins[23]	transitions[0x0=>0x1]	901661	1			T23	14		T24	23		T25	54576
all_pins[23]	transitions[0x1=>0x0]	904740	1			T23	7		T24	48		T25	55003
all_pins[24]	values[0x0]	2467104	1			T22	1		T23	29		T24	104
all_pins[24]	values[0x1]	1512343	1			T23	18		T24	19		T25	92163
all_pins[24]	transitions[0x0=>0x1]	902665	1			T23	9		T24	18		T25	55119
all_pins[24]	transitions[0x1=>0x0]	901292	1			T23	14		T24	39		T25	54255
all_pins[25]	values[0x0]	2468758	1			T22	1		T23	23		T24	85
all_pins[25]	values[0x1]	1510689	1			T23	24		T24	38		T25	91776
all_pins[25]	transitions[0x0=>0x1]	901594	1			T23	12		T24	35		T25	54324
all_pins[25]	transitions[0x1=>0x0]	903248	1			T23	6		T24	16		T25	54711
all_pins[26]	values[0x0]	2470844	1			T22	1		T23	26		T24	73
all_pins[26]	values[0x1]	1508603	1			T23	21		T24	50		T25	90706
all_pins[26]	transitions[0x0=>0x1]	901823	1			T23	9		T24	37		T25	53457
all_pins[26]	transitions[0x1=>0x0]	903909	1			T23	12		T24	25		T25	54527
all_pins[27]	values[0x0]	2468926	1			T22	1		T23	28		T24	104
all_pins[27]	values[0x1]	1510521	1			T23	19		T24	19		T25	90015
all_pins[27]	transitions[0x0=>0x1]	902029	1			T23	12		T24	6		T25	54359
all_pins[27]	transitions[0x1=>0x0]	900111	1			T23	14		T24	37		T25	55050
all_pins[28]	values[0x0]	2477423	1			T22	1		T23	28		T24	83
all_pins[28]	values[0x1]	1502024	1			T23	19		T24	40		T25	89892
all_pins[28]	transitions[0x0=>0x1]	898889	1			T23	13		T24	34		T25	54198
all_pins[28]	transitions[0x1=>0x0]	907386	1			T23	13		T24	13		T25	54321
all_pins[29]	values[0x0]	2467704	1			T22	1		T23	24		T24	68
all_pins[29]	values[0x1]	1511743	1			T23	23		T24	55		T25	90644
all_pins[29]	transitions[0x0=>0x1]	906415	1			T23	14		T24	44		T25	54815
all_pins[29]	transitions[0x1=>0x0]	896696	1			T23	10		T24	29		T25	54063
all_pins[30]	values[0x0]	2470764	1			T22	1		T23	38		T24	81
all_pins[30]	values[0x1]	1508683	1			T23	9		T24	42		T25	91834
all_pins[30]	transitions[0x0=>0x1]	900944	1			T23	4		T24	27		T25	54594
all_pins[30]	transitions[0x1=>0x0]	904004	1			T23	18		T24	40		T25	53404
all_pins[31]	values[0x0]	2471601	1			T22	1		T23	14		T24	69
all_pins[31]	values[0x1]	1507846	1			T23	33		T24	54		T25	90457
all_pins[31]	transitions[0x0=>0x1]	899752	1			T23	27		T24	28		T25	54000
all_pins[31]	transitions[0x1=>0x0]	900589	1			T23	3		T24	16		T25	55377