Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13176622	1			T22	31		T23	671		T24	206
all_values[1]	13176622	1			T22	31		T23	671		T24	206
all_values[2]	13176622	1			T22	31		T23	671		T24	206
all_values[3]	13176622	1			T22	31		T23	671		T24	206
all_values[4]	13176622	1			T22	31		T23	671		T24	206
all_values[5]	13176622	1			T22	31		T23	671		T24	206
all_values[6]	13176622	1			T22	31		T23	671		T24	206
all_values[7]	13176622	1			T22	31		T23	671		T24	206
all_values[8]	13176622	1			T22	31		T23	671		T24	206
all_values[9]	13176622	1			T22	31		T23	671		T24	206
all_values[10]	13176622	1			T22	31		T23	671		T24	206
all_values[11]	13176622	1			T22	31		T23	671		T24	206
all_values[12]	13176622	1			T22	31		T23	671		T24	206
all_values[13]	13176622	1			T22	31		T23	671		T24	206
all_values[14]	13176622	1			T22	31		T23	671		T24	206
all_values[15]	13176622	1			T22	31		T23	671		T24	206
all_values[16]	13176622	1			T22	31		T23	671		T24	206
all_values[17]	13176622	1			T22	31		T23	671		T24	206
all_values[18]	13176622	1			T22	31		T23	671		T24	206
all_values[19]	13176622	1			T22	31		T23	671		T24	206
all_values[20]	13176622	1			T22	31		T23	671		T24	206
all_values[21]	13176622	1			T22	31		T23	671		T24	206
all_values[22]	13176622	1			T22	31		T23	671		T24	206
all_values[23]	13176622	1			T22	31		T23	671		T24	206
all_values[24]	13176622	1			T22	31		T23	671		T24	206
all_values[25]	13176622	1			T22	31		T23	671		T24	206
all_values[26]	13176622	1			T22	31		T23	671		T24	206
all_values[27]	13176622	1			T22	31		T23	671		T24	206
all_values[28]	13176622	1			T22	31		T23	671		T24	206
all_values[29]	13176622	1			T22	31		T23	671		T24	206
all_values[30]	13176622	1			T22	31		T23	671		T24	206
all_values[31]	13176622	1			T22	31		T23	671		T24	206

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240968023

1

T22

992

T23

21472

T24

3877

auto[1]

180683881

1

T24

2715

T25

110854

T1

10471

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94746356

1

T22

992

T23

21472

T24

1224

auto[1]

326905548

1

T24

5368

T25

200691

T1

18479

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417078639

1

T22

992

T23

21472

T24

6592

auto[1]

4573265

1

T25

242039

T1

763

T14

120

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2417534	1			T22	31		T23	671		T24	15
all_values[0]	auto[0]	auto[0]	auto[1]	5055734	1			T24	98		T25	314826		T1	257
all_values[0]	auto[0]	auto[1]	auto[0]	545323	1			T24	11		T25	32358		T1	60
all_values[0]	auto[0]	auto[1]	auto[1]	5015254	1			T24	82		T25	305944		T1	271
all_values[0]	auto[1]	auto[0]	auto[1]	71461	1			T25	3827		T1	8		T14	2
all_values[0]	auto[1]	auto[1]	auto[1]	71316	1			T25	3688		T1	14		T15	118
all_values[1]	auto[0]	auto[0]	auto[0]	2423616	1			T22	31		T23	671		T24	21
all_values[1]	auto[0]	auto[0]	auto[1]	5014815	1			T24	100		T25	316379		T1	203
all_values[1]	auto[0]	auto[1]	auto[0]	549694	1			T24	8		T25	33840		T1	42
all_values[1]	auto[0]	auto[1]	auto[1]	5045199	1			T24	77		T25	301783		T1	323
all_values[1]	auto[1]	auto[0]	auto[1]	72143	1			T25	3931		T1	12		T14	2
all_values[1]	auto[1]	auto[1]	auto[1]	71155	1			T25	3653		T1	14		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	2424198	1			T22	31		T23	671		T24	29
all_values[2]	auto[0]	auto[0]	auto[1]	5037029	1			T24	115		T25	304694		T1	313
all_values[2]	auto[0]	auto[1]	auto[0]	544708	1			T24	16		T25	31087		T1	53
all_values[2]	auto[0]	auto[1]	auto[1]	5027964	1			T24	46		T25	316954		T1	187
all_values[2]	auto[1]	auto[0]	auto[1]	71880	1			T25	3839		T1	18		T14	4
all_values[2]	auto[1]	auto[1]	auto[1]	70843	1			T25	3688		T1	11		T15	134
all_values[3]	auto[0]	auto[0]	auto[0]	2419083	1			T22	31		T23	671		T24	9
all_values[3]	auto[0]	auto[0]	auto[1]	5083218	1			T24	98		T25	310012		T1	356
all_values[3]	auto[0]	auto[1]	auto[0]	544554	1			T24	37		T25	30912		T1	17
all_values[3]	auto[0]	auto[1]	auto[1]	4987152	1			T24	62		T25	311209		T1	199
all_values[3]	auto[1]	auto[0]	auto[1]	71863	1			T25	3850		T1	14		T14	2
all_values[3]	auto[1]	auto[1]	auto[1]	70752	1			T25	3684		T1	6		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	2415175	1			T22	31		T23	671		T24	26
all_values[4]	auto[0]	auto[0]	auto[1]	5053214	1			T24	108		T25	320448		T1	366
all_values[4]	auto[0]	auto[1]	auto[0]	545413	1			T24	8		T25	33186		T1	39
all_values[4]	auto[0]	auto[1]	auto[1]	5019780	1			T24	64		T25	297498		T1	193
all_values[4]	auto[1]	auto[0]	auto[1]	71985	1			T25	3675		T1	16		T14	4
all_values[4]	auto[1]	auto[1]	auto[1]	71055	1			T25	3859		T1	4		T14	1
all_values[5]	auto[0]	auto[0]	auto[0]	2414503	1			T22	31		T23	671		T24	43
all_values[5]	auto[0]	auto[0]	auto[1]	5082937	1			T24	84		T25	319011		T1	350
all_values[5]	auto[0]	auto[1]	auto[0]	544708	1			T24	13		T25	30883		T1	35
all_values[5]	auto[0]	auto[1]	auto[1]	4991722	1			T24	66		T25	301475		T1	172
all_values[5]	auto[1]	auto[0]	auto[1]	71624	1			T25	3857		T1	12		T14	3
all_values[5]	auto[1]	auto[1]	auto[1]	71128	1			T25	3716		T1	9		T15	133
all_values[6]	auto[0]	auto[0]	auto[0]	2407804	1			T22	31		T23	671		T24	23
all_values[6]	auto[0]	auto[0]	auto[1]	5090013	1			T24	105		T25	310438		T1	300
all_values[6]	auto[0]	auto[1]	auto[0]	541668	1			T24	16		T25	32182		T1	47
all_values[6]	auto[0]	auto[1]	auto[1]	4994217	1			T24	62		T25	307897		T1	251
all_values[6]	auto[1]	auto[0]	auto[1]	71846	1			T25	3792		T1	17		T14	4
all_values[6]	auto[1]	auto[1]	auto[1]	71074	1			T25	3790		T1	11		T15	115
all_values[7]	auto[0]	auto[0]	auto[0]	2414875	1			T22	31		T23	671		T24	30
all_values[7]	auto[0]	auto[0]	auto[1]	5051143	1			T24	104		T25	305856		T1	239
all_values[7]	auto[0]	auto[1]	auto[0]	541569	1			T24	8		T25	32964		T1	16
all_values[7]	auto[0]	auto[1]	auto[1]	5026122	1			T24	64		T25	310470		T1	356
all_values[7]	auto[1]	auto[0]	auto[1]	71381	1			T25	3797		T1	4		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	71532	1			T25	3813		T1	21		T15	138
all_values[8]	auto[0]	auto[0]	auto[0]	2415111	1			T22	31		T23	671		T24	23
all_values[8]	auto[0]	auto[0]	auto[1]	5047862	1			T24	74		T25	300307		T1	253
all_values[8]	auto[0]	auto[1]	auto[0]	539722	1			T24	5		T25	31794		T1	67
all_values[8]	auto[0]	auto[1]	auto[1]	5031292	1			T24	104		T25	320987		T1	261
all_values[8]	auto[1]	auto[0]	auto[1]	71248	1			T25	3734		T1	17		T14	2
all_values[8]	auto[1]	auto[1]	auto[1]	71387	1			T25	3692		T1	7		T14	1
all_values[9]	auto[0]	auto[0]	auto[0]	2408770	1			T22	31		T23	671		T24	23
all_values[9]	auto[0]	auto[0]	auto[1]	5009106	1			T24	79		T25	309325		T1	184
all_values[9]	auto[0]	auto[1]	auto[0]	553251	1			T24	12		T25	33925		T1	60
all_values[9]	auto[0]	auto[1]	auto[1]	5062975	1			T24	92		T25	309174		T1	343
all_values[9]	auto[1]	auto[0]	auto[1]	71639	1			T25	3782		T1	8		T14	3
all_values[9]	auto[1]	auto[1]	auto[1]	70881	1			T25	3759		T1	17		T14	1
all_values[10]	auto[0]	auto[0]	auto[0]	2419503	1			T22	31		T23	671		T24	13
all_values[10]	auto[0]	auto[0]	auto[1]	5081686	1			T24	87		T25	311342		T1	278
all_values[10]	auto[0]	auto[1]	auto[0]	546012	1			T24	15		T25	32180		T1	42
all_values[10]	auto[0]	auto[1]	auto[1]	4986614	1			T24	91		T25	309020		T1	296
all_values[10]	auto[1]	auto[0]	auto[1]	71669	1			T25	3706		T1	14		T14	3
all_values[10]	auto[1]	auto[1]	auto[1]	71138	1			T25	3785		T1	14		T14	1
all_values[11]	auto[0]	auto[0]	auto[0]	2414081	1			T22	31		T23	671		T24	19
all_values[11]	auto[0]	auto[0]	auto[1]	5045703	1			T24	125		T25	321774		T1	239
all_values[11]	auto[0]	auto[1]	auto[0]	546228	1			T24	5		T25	32319		T1	56
all_values[11]	auto[0]	auto[1]	auto[1]	5027621	1			T24	57		T25	298174		T1	297
all_values[11]	auto[1]	auto[0]	auto[1]	71231	1			T25	3719		T1	14		T14	4
all_values[11]	auto[1]	auto[1]	auto[1]	71758	1			T25	3872		T1	11		T14	3
all_values[12]	auto[0]	auto[0]	auto[0]	2414080	1			T22	31		T23	671		T24	12
all_values[12]	auto[0]	auto[0]	auto[1]	5001562	1			T24	103		T25	318544		T1	291
all_values[12]	auto[0]	auto[1]	auto[0]	547002	1			T24	6		T25	32028		T1	39
all_values[12]	auto[0]	auto[1]	auto[1]	5070814	1			T24	85		T25	301959		T1	279
all_values[12]	auto[1]	auto[0]	auto[1]	71711	1			T25	3797		T1	19		T14	1
all_values[12]	auto[1]	auto[1]	auto[1]	71453	1			T25	3766		T1	10		T14	3
all_values[13]	auto[0]	auto[0]	auto[0]	2414503	1			T22	31		T23	671		T24	33
all_values[13]	auto[0]	auto[0]	auto[1]	5034634	1			T24	116		T25	310364		T1	364
all_values[13]	auto[0]	auto[1]	auto[0]	549809	1			T24	5		T25	30942		T1	17
all_values[13]	auto[0]	auto[1]	auto[1]	5034676	1			T24	52		T25	310726		T1	200
all_values[13]	auto[1]	auto[0]	auto[1]	71574	1			T25	3677		T1	16		T14	1
all_values[13]	auto[1]	auto[1]	auto[1]	71426	1			T25	3885		T1	12		T14	2
all_values[14]	auto[0]	auto[0]	auto[0]	2422047	1			T22	31		T23	671		T24	17
all_values[14]	auto[0]	auto[0]	auto[1]	5062260	1			T24	100		T25	310420		T1	202
all_values[14]	auto[0]	auto[1]	auto[0]	541526	1			T24	3		T25	34431		T1	37
all_values[14]	auto[0]	auto[1]	auto[1]	5008027	1			T24	86		T25	308475		T1	366
all_values[14]	auto[1]	auto[0]	auto[1]	71847	1			T25	3739		T1	6		T14	3
all_values[14]	auto[1]	auto[1]	auto[1]	70915	1			T25	3873		T1	24		T15	112
all_values[15]	auto[0]	auto[0]	auto[0]	2410733	1			T22	31		T23	671		T24	24
all_values[15]	auto[0]	auto[0]	auto[1]	5012896	1			T24	70		T25	298226		T1	212
all_values[15]	auto[0]	auto[1]	auto[0]	551904	1			T24	32		T25	32317		T1	100
all_values[15]	auto[0]	auto[1]	auto[1]	5058386	1			T24	80		T25	323342		T1	278
all_values[15]	auto[1]	auto[0]	auto[1]	71521	1			T25	3729		T1	11		T14	4
all_values[15]	auto[1]	auto[1]	auto[1]	71182	1			T25	3893		T1	15		T14	2
all_values[16]	auto[0]	auto[0]	auto[0]	2422544	1			T22	31		T23	671		T24	43
all_values[16]	auto[0]	auto[0]	auto[1]	5056186	1			T24	64		T25	304746		T1	298
all_values[16]	auto[0]	auto[1]	auto[0]	546896	1			T24	25		T25	32930		T1	23
all_values[16]	auto[0]	auto[1]	auto[1]	5008587	1			T24	74		T25	316103		T1	308
all_values[16]	auto[1]	auto[0]	auto[1]	71288	1			T25	3744		T1	11		T14	3
all_values[16]	auto[1]	auto[1]	auto[1]	71121	1			T25	3829		T1	11		T14	1
all_values[17]	auto[0]	auto[0]	auto[0]	2417639	1			T22	31		T23	671		T24	18
all_values[17]	auto[0]	auto[0]	auto[1]	5006864	1			T24	83		T25	301515		T1	289
all_values[17]	auto[0]	auto[1]	auto[0]	543604	1			T24	18		T25	32849		T1	33
all_values[17]	auto[0]	auto[1]	auto[1]	5065083	1			T24	87		T25	317437		T1	274
all_values[17]	auto[1]	auto[0]	auto[1]	72383	1			T25	3879		T1	12		T14	3
all_values[17]	auto[1]	auto[1]	auto[1]	71049	1			T25	3724		T1	13		T14	3
all_values[18]	auto[0]	auto[0]	auto[0]	2418497	1			T22	31		T23	671		T24	47
all_values[18]	auto[0]	auto[0]	auto[1]	5035306	1			T24	94		T25	311225		T1	245
all_values[18]	auto[0]	auto[1]	auto[0]	542158	1			T24	20		T25	31970		T1	29
all_values[18]	auto[0]	auto[1]	auto[1]	5037932	1			T24	45		T25	308921		T1	321
all_values[18]	auto[1]	auto[0]	auto[1]	71499	1			T25	3792		T1	16		T15	109
all_values[18]	auto[1]	auto[1]	auto[1]	71230	1			T25	3728		T1	9		T14	2
all_values[19]	auto[0]	auto[0]	auto[0]	2408301	1			T22	31		T23	671		T24	30
all_values[19]	auto[0]	auto[0]	auto[1]	5070405	1			T24	131		T25	313779		T1	281
all_values[19]	auto[0]	auto[1]	auto[0]	541811	1			T24	3		T25	32896		T1	50
all_values[19]	auto[0]	auto[1]	auto[1]	5013310	1			T24	42		T25	307515		T1	248
all_values[19]	auto[1]	auto[0]	auto[1]	71827	1			T25	3727		T1	6		T14	3
all_values[19]	auto[1]	auto[1]	auto[1]	70968	1			T25	3800		T1	15		T15	134
all_values[20]	auto[0]	auto[0]	auto[0]	2418234	1			T22	31		T23	671		T24	17
all_values[20]	auto[0]	auto[0]	auto[1]	5021008	1			T24	82		T25	316840		T1	297
all_values[20]	auto[0]	auto[1]	auto[0]	537857	1			T24	38		T25	31696		T1	7
all_values[20]	auto[0]	auto[1]	auto[1]	5056095	1			T24	69		T25	302722		T1	286
all_values[20]	auto[1]	auto[0]	auto[1]	71885	1			T25	3744		T1	13		T14	2
all_values[20]	auto[1]	auto[1]	auto[1]	71543	1			T25	3852		T1	11		T15	116
all_values[21]	auto[0]	auto[0]	auto[0]	2412623	1			T22	31		T23	671		T24	21
all_values[21]	auto[0]	auto[0]	auto[1]	5060911	1			T24	117		T25	302213		T1	285
all_values[21]	auto[0]	auto[1]	auto[0]	545327	1			T24	15		T25	34709		T1	40
all_values[21]	auto[0]	auto[1]	auto[1]	5014838	1			T24	53		T25	316707		T1	287
all_values[21]	auto[1]	auto[0]	auto[1]	72382	1			T25	3819		T1	12		T14	5
all_values[21]	auto[1]	auto[1]	auto[1]	70541	1			T25	3844		T1	12		T15	120
all_values[22]	auto[0]	auto[0]	auto[0]	2409184	1			T22	31		T23	671		T24	16
all_values[22]	auto[0]	auto[0]	auto[1]	5039905	1			T24	61		T25	302188		T1	292
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all_values[22]	auto[0]	auto[1]	auto[1]	5042366	1			T24	112		T25	318090		T1	237
all_values[22]	auto[1]	auto[0]	auto[1]	71796	1			T25	3848		T1	12		T14	4
all_values[22]	auto[1]	auto[1]	auto[1]	71345	1			T25	3729		T1	8		T14	1
all_values[23]	auto[0]	auto[0]	auto[0]	2412849	1			T22	31		T23	671		T24	32
all_values[23]	auto[0]	auto[0]	auto[1]	5027310	1			T24	100		T25	306020		T1	328
all_values[23]	auto[0]	auto[1]	auto[0]	546418	1			T24	8		T25	32953		T1	17
all_values[23]	auto[0]	auto[1]	auto[1]	5046919	1			T24	66		T25	314203		T1	278
all_values[23]	auto[1]	auto[0]	auto[1]	71772	1			T25	3829		T1	10		T14	3
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all_values[24]	auto[0]	auto[0]	auto[1]	5025839	1			T24	134		T25	301295		T1	223
all_values[24]	auto[0]	auto[1]	auto[0]	555582	1			T25	34052		T1	67		T14	2
all_values[24]	auto[0]	auto[1]	auto[1]	5046129	1			T24	35		T25	318830		T1	309
all_values[24]	auto[1]	auto[0]	auto[1]	71707	1			T25	3683		T1	10		T14	4
all_values[24]	auto[1]	auto[1]	auto[1]	71072	1			T25	3831		T1	10		T15	93
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all_values[25]	auto[0]	auto[0]	auto[1]	5044785	1			T24	92		T25	314008		T1	237
all_values[25]	auto[0]	auto[1]	auto[0]	548567	1			T24	19		T25	34172		T1	65
all_values[25]	auto[0]	auto[1]	auto[1]	5027052	1			T24	67		T25	303982		T1	318
all_values[25]	auto[1]	auto[0]	auto[1]	71409	1			T25	3791		T1	5		T14	1
all_values[25]	auto[1]	auto[1]	auto[1]	71276	1			T25	3777		T1	15		T14	2
all_values[26]	auto[0]	auto[0]	auto[0]	2415786	1			T22	31		T23	671		T24	32
all_values[26]	auto[0]	auto[0]	auto[1]	5046359	1			T24	62		T25	308805		T1	251
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all_values[26]	auto[0]	auto[1]	auto[1]	5019691	1			T24	84		T25	308233		T1	348
all_values[26]	auto[1]	auto[0]	auto[1]	71850	1			T25	3871		T1	8		T14	1
all_values[26]	auto[1]	auto[1]	auto[1]	71671	1			T25	3706		T1	14		T15	143
all_values[27]	auto[0]	auto[0]	auto[0]	2411641	1			T22	31		T23	671		T24	38
all_values[27]	auto[0]	auto[0]	auto[1]	5036070	1			T24	114		T25	318534		T1	256
all_values[27]	auto[0]	auto[1]	auto[0]	549157	1			T24	13		T25	33699		T1	58
all_values[27]	auto[0]	auto[1]	auto[1]	5036829	1			T24	41		T25	300894		T1	295
all_values[27]	auto[1]	auto[0]	auto[1]	71802	1			T25	3867		T1	11		T14	4
all_values[27]	auto[1]	auto[1]	auto[1]	71123	1			T25	3699		T1	13		T15	126
all_values[28]	auto[0]	auto[0]	auto[0]	2418738	1			T22	31		T23	671		T24	25
all_values[28]	auto[0]	auto[0]	auto[1]	5061116	1			T24	109		T25	307501		T1	288
all_values[28]	auto[0]	auto[1]	auto[0]	544704	1			T24	2		T25	33021		T1	18
all_values[28]	auto[0]	auto[1]	auto[1]	5009681	1			T24	70		T25	311303		T1	262
all_values[28]	auto[1]	auto[0]	auto[1]	71565	1			T25	3860		T1	11		T14	4
all_values[28]	auto[1]	auto[1]	auto[1]	70818	1			T25	3715		T1	9		T14	1
all_values[29]	auto[0]	auto[0]	auto[0]	2412274	1			T22	31		T23	671		T24	9
all_values[29]	auto[0]	auto[0]	auto[1]	5014513	1			T24	111		T25	304665		T1	312
all_values[29]	auto[0]	auto[1]	auto[0]	545249	1			T24	1		T25	31327		T1	41
all_values[29]	auto[0]	auto[1]	auto[1]	5061295	1			T24	85		T25	315024		T1	266
all_values[29]	auto[1]	auto[0]	auto[1]	71478	1			T25	3759		T1	9		T14	2
all_values[29]	auto[1]	auto[1]	auto[1]	71813	1			T25	3872		T1	10		T15	117
all_values[30]	auto[0]	auto[0]	auto[0]	2415610	1			T22	31		T23	671		T24	16
all_values[30]	auto[0]	auto[0]	auto[1]	5028837	1			T24	79		T25	305000		T1	286
all_values[30]	auto[0]	auto[1]	auto[0]	539448	1			T24	26		T25	32573		T1	14
all_values[30]	auto[0]	auto[1]	auto[1]	5049618	1			T24	85		T25	316579		T1	280
all_values[30]	auto[1]	auto[0]	auto[1]	71643	1			T25	3695		T1	11		T14	6
all_values[30]	auto[1]	auto[1]	auto[1]	71466	1			T25	3909		T1	10		T15	122
all_values[31]	auto[0]	auto[0]	auto[0]	2419221	1			T22	31		T23	671		T24	16
all_values[31]	auto[0]	auto[0]	auto[1]	5045361	1			T24	93		T25	309308		T1	337
all_values[31]	auto[0]	auto[1]	auto[0]	544613	1			T24	6		T25	34325		T1	50
all_values[31]	auto[0]	auto[1]	auto[1]	5024456	1			T24	91		T25	305918		T1	215
all_values[31]	auto[1]	auto[0]	auto[1]	71944	1			T25	3761		T1	19		T14	2
all_values[31]	auto[1]	auto[1]	auto[1]	71027	1			T25	3718		T1	5		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal