Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[1]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[2]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[3]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[4]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[5]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[6]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[7]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[8]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[9]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[10]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[11]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[12]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[13]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[14]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[15]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[16]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[17]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[18]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[19]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[20]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[21]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[22]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[23]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[24]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[25]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[26]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[27]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[28]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[29]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[30]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[31]	12992670	1			T22	56		T23	671		T24	109

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244778117

1

T22

466

T23

11007

T24

1783

auto[1]

170987323

1

T22

1326

T23

10465

T24

1705

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332807124

1

T22

1556

T23

21472

T24

3488

auto[1]

82958316

1

T22

236

T25

465367

T26

180

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308611504

1

T22

1307

T23

21472

T24

3488

auto[1]

107153936

1

T22

485

T25

604465

T26

474

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4755537	1			T22	7		T23	372		T24	58
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3589597	1			T22	41		T23	299		T24	51
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1303440	1			T22	8		T25	73676		T26	10
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1591252	1			T25	109585		T1	11		T11	34
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	463782	1			T25	7866		T1	162		T11	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1289062	1			T25	72012		T1	114		T11	10
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4750326	1			T22	15		T23	379		T24	43
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3588417	1			T22	41		T23	292		T24	66
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1302590	1			T25	71673		T26	16		T1	162
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1589189	1			T25	109566		T26	2		T1	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	465801	1			T25	8015		T26	3		T1	199
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1296347	1			T25	73683		T1	81		T11	6
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4743079	1			T22	11		T23	395		T24	52
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3597959	1			T22	37		T23	276		T24	57
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1304795	1			T22	8		T25	73408		T26	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1590556	1			T25	108136		T1	15		T11	36
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	464735	1			T25	7728		T1	192		T11	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1291546	1			T25	71631		T1	164		T11	9
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4751388	1			T22	12		T23	298		T24	52
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3587754	1			T22	31		T23	373		T24	57
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1302784	1			T22	2		T25	72700		T26	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1593691	1			T22	1		T25	108282		T26	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	464612	1			T22	10		T25	7677		T26	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1292441	1			T25	72886		T1	154		T11	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4759867	1			T22	14		T23	335		T24	68
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3574646	1			T22	34		T23	336		T24	41
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1303453	1			T22	8		T25	73143		T26	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1593529	1			T25	109758		T26	2		T1	11
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	464440	1			T25	7616		T26	6		T1	158
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1296735	1			T25	72334		T26	2		T1	104
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4743844	1			T22	8		T23	411		T24	57
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3596417	1			T22	40		T23	260		T24	52
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1305377	1			T22	8		T25	72782		T26	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1591622	1			T25	108868		T26	6		T1	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	467777	1			T25	7960		T26	19		T1	196
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1287633	1			T25	73078		T1	152		T11	24
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4743925	1			T22	5		T23	296		T24	68
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3587948	1			T22	29		T23	375		T24	41
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1303780	1			T22	6		T25	72853		T26	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1598306	1			T22	8		T25	108297		T1	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	465039	1			T22	6		T25	7667		T1	108
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1293672	1			T22	2		T25	72070		T1	122
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4741274	1			T22	2		T23	379		T24	59
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3596210	1			T22	25		T23	292		T24	50
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1303837	1			T22	2		T25	74391		T26	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1596341	1			T22	8		T25	107433		T26	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	464117	1			T22	19		T25	7711		T26	24
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1290891	1			T25	72137		T26	2		T1	74
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4736917	1			T22	1		T23	336		T24	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3595063	1			T22	28		T23	335		T24	51
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1301651	1			T25	72875		T26	10		T1	133
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1599569	1			T22	9		T25	108894		T26	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	465317	1			T22	12		T25	7980		T26	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1294153	1			T22	6		T25	72525		T1	121
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4748653	1			T22	1		T23	362		T24	49
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3585076	1			T22	33		T23	309		T24	60
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1305764	1			T22	6		T25	73691		T26	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1596597	1			T22	6		T25	109338		T26	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	465217	1			T22	10		T25	7783		T26	19
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1291363	1			T25	73478		T26	8		T1	140
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4750189	1			T22	5		T23	329		T24	37
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3584414	1			T22	45		T23	342		T24	72
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1306880	1			T22	6		T25	73819		T26	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1596330	1			T25	108817		T26	3		T1	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	466785	1			T25	7909		T26	9		T1	206
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1288072	1			T25	72270		T26	6		T1	127
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4750774	1			T22	9		T23	393		T24	69
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3585360	1			T22	39		T23	278		T24	40
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1306990	1			T22	8		T25	72494		T26	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1589156	1			T25	109011		T26	2		T1	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	463804	1			T25	7816		T26	3		T1	168
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1296586	1			T25	72569		T1	121		T11	25
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4753930	1			T22	8		T23	251		T24	44
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3584062	1			T22	46		T23	420		T24	65
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1303878	1			T22	2		T25	73946		T26	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1598353	1			T25	108796		T26	1		T1	9
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	465329	1			T25	7825		T26	4		T1	150
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1287118	1			T25	72498		T1	126		T11	12
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4750893	1			T22	4		T23	324		T24	65
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3590400	1			T22	23		T23	347		T24	44
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1299984	1			T22	2		T25	72507		T1	95
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1595222	1			T22	8		T25	109400		T26	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	466261	1			T22	13		T25	7765		T26	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1289910	1			T22	6		T25	72679		T26	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4754457	1			T22	10		T23	324		T24	64
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3587043	1			T22	29		T23	347		T24	45
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1309838	1			T22	6		T25	73837		T26	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1588813	1			T22	1		T25	108196		T26	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	464152	1			T22	6		T25	7739		T26	21
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1288367	1			T22	4		T25	71717		T1	175
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4752882	1			T22	7		T23	374		T24	64
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3584743	1			T22	47		T23	297		T24	45
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1307358	1			T22	2		T25	73830		T26	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1597327	1			T25	109925		T1	16		T11	65
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	462324	1			T25	8254		T1	163		T11	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1288036	1			T25	71772		T1	139		T14	9
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4750907	1			T22	6		T23	319		T24	62
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3589210	1			T22	39		T23	352		T24	47
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1296574	1			T22	11		T25	72058		T26	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1601647	1			T25	109526		T26	8		T1	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	465707	1			T25	8059		T26	9		T1	195
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1288625	1			T25	72647		T26	4		T1	148
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4754470	1			T22	1		T23	356		T24	54
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3592471	1			T22	5		T23	315		T24	55
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1301374	1			T22	2		T25	72027		T26	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1591034	1			T22	8		T25	109284		T26	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	463137	1			T22	31		T25	7843		T26	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1290184	1			T22	9		T25	73571		T26	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4758758	1			T22	7		T23	332		T24	47
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3592201	1			T22	34		T23	339		T24	62
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1300884	1			T22	15		T25	73753		T1	155
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1590455	1			T25	107621		T26	5		T1	24
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	463241	1			T25	7729		T26	20		T1	186
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1287131	1			T25	71943		T1	124		T11	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4759003	1			T23	366		T24	52		T25	263424
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3589204	1			T22	1		T23	305		T24	57
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1299700	1			T25	72905		T26	8		T1	112
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1594721	1			T22	10		T25	107703		T1	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	464095	1			T22	35		T25	7614		T26	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1285947	1			T22	10		T25	72088		T1	134
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4748346	1			T23	305		T24	59		T25	262512
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3590591	1			T22	1		T23	366		T24	50
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1304638	1			T25	72027		T26	6		T1	146
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1594258	1			T22	10		T25	108566		T26	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	464851	1			T22	36		T25	7813		T26	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1289986	1			T22	9		T25	72478		T26	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4745033	1			T22	8		T23	305		T24	65
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3594208	1			T22	40		T23	366		T24	44
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1299692	1			T22	8		T25	71913		T26	10
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1598854	1			T25	108244		T11	4		T14	28
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	466452	1			T25	7466		T1	114		T11	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1288431	1			T25	71935		T1	111		T11	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4752579	1			T22	1		T23	333		T24	50
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3591108	1			T22	5		T23	338		T24	59
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1297183	1			T22	2		T25	72031		T1	128
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1598619	1			T22	13		T25	109143		T26	3
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	464899	1			T22	31		T25	7754		T26	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1288282	1			T22	4		T25	72957		T1	135
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4751790	1			T22	11		T23	369		T24	43
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3593710	1			T22	35		T23	302		T24	66
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1311283	1			T22	10		T25	73635		T26	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1587772	1			T25	107265		T26	1		T1	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	462207	1			T25	7705		T26	6		T1	136
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1285908	1			T25	72175		T1	118		T11	30
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4750066	1			T23	385		T24	42		T25	261902
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3591773	1			T22	8		T23	286		T24	67
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1299844	1			T25	72455		T1	105		T11	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1596850	1			T22	5		T25	109097		T26	7
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	465484	1			T22	37		T25	7569		T26	22
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1288653	1			T22	6		T25	72455		T26	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4754035	1			T22	10		T23	292		T24	48
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3591937	1			T22	40		T23	379		T24	61
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1302215	1			T22	6		T25	74270		T1	73
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1595429	1			T25	107108		T26	9		T1	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	464259	1			T25	7610		T26	22		T1	230
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1284795	1			T25	71430		T1	125		T11	6
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4755557	1			T22	1		T23	386		T24	60
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3593122	1			T22	7		T23	285		T24	49
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1303357	1			T25	74113		T1	142		T11	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1589980	1			T22	8		T25	108499		T26	5
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	463568	1			T22	31		T25	7760		T26	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1287086	1			T22	9		T25	72205		T26	2
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4747150	1			T22	8		T23	378		T24	49
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3595002	1			T22	42		T23	293		T24	60
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1303741	1			T22	6		T25	73158		T26	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1597115	1			T25	108523		T26	6		T1	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	463894	1			T25	7851		T26	24		T1	129
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1285768	1			T25	72692		T1	158		T11	4
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4760914	1			T22	10		T23	374		T24	65
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3583427	1			T22	42		T23	297		T24	44
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1305162	1			T22	4		T25	72172		T1	157
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1591848	1			T25	109749		T26	3		T1	17
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	463636	1			T25	7980		T26	23		T1	174
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1287683	1			T25	72621		T1	62		T11	6
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4772898	1			T22	12		T23	291		T24	67
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3573575	1			T22	34		T23	380		T24	42
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1299823	1			T22	10		T25	72704		T26	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1593713	1			T25	107905		T26	7		T1	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	465720	1			T25	7594		T26	12		T1	97
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1286941	1			T25	72363		T26	8		T1	124
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4742818	1			T23	342		T24	61		T25	261736
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3594918	1			T22	8		T23	329		T24	48
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1298655	1			T25	72328		T26	2		T1	130
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1603720	1			T22	11		T25	109401		T26	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	466503	1			T22	23		T25	7815		T26	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1286056	1			T22	14		T25	72131		T1	148
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4762742	1			T22	9		T23	316		T24	52
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3585419	1			T22	38		T23	355		T24	57
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1302994	1			T22	9		T25	73105		T1	189
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1591730	1			T25	108125		T26	3		T1	11
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	464395	1			T25	7730		T26	4		T1	155
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1285390	1			T25	72365		T1	101		T11	22

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal