Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[1]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[2]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[3]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[4]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[5]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[6]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[7]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[8]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[9]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[10]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[11]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[12]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[13]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[14]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[15]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[16]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[17]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[18]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[19]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[20]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[21]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[22]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[23]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[24]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[25]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[26]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[27]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[28]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[29]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[30]	12992670	1			T22	56		T23	671		T24	109
bins_for_gpio_bits[31]	12992670	1			T22	56		T23	671		T24	109

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244778117

1

T22

466

T23

11007

T24

1783

auto[1]

170987323

1

T22

1326

T23

10465

T24

1705

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244771247

1

T22

466

T23

11007

T24

1783

auto[1]

170994193

1

T22

1326

T23

10465

T24

1705

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7417063	1			T22	13		T23	372		T24	58
bins_for_gpio_bits[0]	auto[0]	auto[1]	233013	1			T22	2		T25	13301		T26	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	233166	1			T22	2		T25	13303		T26	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5109428	1			T22	39		T23	299		T24	51
bins_for_gpio_bits[1]	auto[0]	auto[0]	7408449	1			T22	15		T23	379		T24	43
bins_for_gpio_bits[1]	auto[0]	auto[1]	233447	1			T25	13360		T26	3		T1	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	233656	1			T25	13361		T26	3		T1	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	5117118	1			T22	41		T23	292		T24	66
bins_for_gpio_bits[2]	auto[0]	auto[0]	7404558	1			T22	17		T23	395		T24	52
bins_for_gpio_bits[2]	auto[0]	auto[1]	233634	1			T22	2		T25	13036		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	233872	1			T22	2		T25	13036		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5120606	1			T22	35		T23	276		T24	57
bins_for_gpio_bits[3]	auto[0]	auto[0]	7413874	1			T22	14		T23	298		T24	52
bins_for_gpio_bits[3]	auto[0]	auto[1]	233765	1			T22	1		T25	13311		T26	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	233989	1			T22	1		T25	13313		T26	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5111042	1			T22	40		T23	373		T24	57
bins_for_gpio_bits[4]	auto[0]	auto[0]	7422850	1			T22	20		T23	335		T24	68
bins_for_gpio_bits[4]	auto[0]	auto[1]	233789	1			T22	2		T25	13245		T26	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	233999	1			T22	2		T25	13247		T26	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	5102032	1			T22	32		T23	336		T24	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	7407737	1			T22	13		T23	411		T24	57
bins_for_gpio_bits[5]	auto[0]	auto[1]	232900	1			T22	3		T25	13326		T26	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	233106	1			T22	3		T25	13326		T26	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5118927	1			T22	37		T23	260		T24	52
bins_for_gpio_bits[6]	auto[0]	auto[0]	7411644	1			T22	16		T23	296		T24	68
bins_for_gpio_bits[6]	auto[0]	auto[1]	234124	1			T22	3		T25	13220		T26	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	234367	1			T22	3		T25	13221		T26	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	5112535	1			T22	34		T23	375		T24	41
bins_for_gpio_bits[7]	auto[0]	auto[0]	7407903	1			T22	11		T23	379		T24	59
bins_for_gpio_bits[7]	auto[0]	auto[1]	233340	1			T22	1		T25	13180		T26	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	233549	1			T22	1		T25	13180		T26	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5117878	1			T22	43		T23	292		T24	50
bins_for_gpio_bits[8]	auto[0]	auto[0]	7404159	1			T22	10		T23	336		T24	58
bins_for_gpio_bits[8]	auto[0]	auto[1]	233754	1			T25	13186		T26	2		T1	23
bins_for_gpio_bits[8]	auto[1]	auto[0]	233978	1			T25	13186		T26	2		T1	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	5120779	1			T22	46		T23	335		T24	51
bins_for_gpio_bits[9]	auto[0]	auto[0]	7417303	1			T22	10		T23	362		T24	49
bins_for_gpio_bits[9]	auto[0]	auto[1]	233463	1			T22	3		T25	13273		T26	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	233711	1			T22	3		T25	13273		T26	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	5108193	1			T22	40		T23	309		T24	60
bins_for_gpio_bits[10]	auto[0]	auto[0]	7420020	1			T22	9		T23	329		T24	37
bins_for_gpio_bits[10]	auto[0]	auto[1]	233171	1			T22	2		T25	13114		T26	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	233379	1			T22	2		T25	13116		T26	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	5106100	1			T22	43		T23	342		T24	72
bins_for_gpio_bits[11]	auto[0]	auto[0]	7413227	1			T22	15		T23	393		T24	69
bins_for_gpio_bits[11]	auto[0]	auto[1]	233464	1			T22	2		T25	13191		T26	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	233693	1			T22	2		T25	13191		T26	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	5112286	1			T22	37		T23	278		T24	40
bins_for_gpio_bits[12]	auto[0]	auto[0]	7422709	1			T22	9		T23	251		T24	44
bins_for_gpio_bits[12]	auto[0]	auto[1]	233223	1			T22	1		T25	13249		T26	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	233452	1			T22	1		T25	13250		T26	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	5103286	1			T22	45		T23	420		T24	65
bins_for_gpio_bits[13]	auto[0]	auto[0]	7413222	1			T22	13		T23	324		T24	65
bins_for_gpio_bits[13]	auto[0]	auto[1]	232655	1			T22	1		T25	13288		T1	18
bins_for_gpio_bits[13]	auto[1]	auto[0]	232877	1			T22	1		T25	13290		T1	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	5113916	1			T22	41		T23	347		T24	44
bins_for_gpio_bits[14]	auto[0]	auto[0]	7419296	1			T22	14		T23	324		T24	64
bins_for_gpio_bits[14]	auto[0]	auto[1]	233547	1			T22	3		T25	13184		T26	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	233812	1			T22	3		T25	13186		T26	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5106015	1			T22	36		T23	347		T24	45
bins_for_gpio_bits[15]	auto[0]	auto[0]	7423646	1			T22	8		T23	374		T24	64
bins_for_gpio_bits[15]	auto[0]	auto[1]	233719	1			T22	1		T25	13210		T26	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	233921	1			T22	1		T25	13210		T26	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	5101384	1			T22	46		T23	297		T24	45
bins_for_gpio_bits[16]	auto[0]	auto[0]	7415562	1			T22	14		T23	319		T24	62
bins_for_gpio_bits[16]	auto[0]	auto[1]	233392	1			T22	3		T25	13150		T26	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	233566	1			T22	3		T25	13150		T26	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5110150	1			T22	36		T23	352		T24	47
bins_for_gpio_bits[17]	auto[0]	auto[0]	7413087	1			T22	10		T23	356		T24	54
bins_for_gpio_bits[17]	auto[0]	auto[1]	233574	1			T22	1		T25	13246		T26	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	233791	1			T22	1		T25	13247		T26	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5112218	1			T22	44		T23	315		T24	55
bins_for_gpio_bits[18]	auto[0]	auto[0]	7416736	1			T22	19		T23	332		T24	47
bins_for_gpio_bits[18]	auto[0]	auto[1]	233171	1			T22	3		T25	13093		T1	19
bins_for_gpio_bits[18]	auto[1]	auto[0]	233361	1			T22	3		T25	13094		T1	19
bins_for_gpio_bits[18]	auto[1]	auto[1]	5109402	1			T22	31		T23	339		T24	62
bins_for_gpio_bits[19]	auto[0]	auto[0]	7420059	1			T22	10		T23	366		T24	52
bins_for_gpio_bits[19]	auto[0]	auto[1]	233156	1			T25	13153		T26	1		T1	22
bins_for_gpio_bits[19]	auto[1]	auto[0]	233365	1			T25	13153		T26	1		T1	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	5106090	1			T22	46		T23	305		T24	57
bins_for_gpio_bits[20]	auto[0]	auto[0]	7412853	1			T22	10		T23	305		T24	59
bins_for_gpio_bits[20]	auto[0]	auto[1]	234177	1			T25	13187		T26	1		T1	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	234389	1			T25	13188		T26	1		T1	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	5111251	1			T22	46		T23	366		T24	50
bins_for_gpio_bits[21]	auto[0]	auto[0]	7409497	1			T22	14		T23	305		T24	65
bins_for_gpio_bits[21]	auto[0]	auto[1]	233856	1			T22	2		T25	13131		T26	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	234082	1			T22	2		T25	13132		T26	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5115235	1			T22	38		T23	366		T24	44
bins_for_gpio_bits[22]	auto[0]	auto[0]	7414479	1			T22	15		T23	333		T24	50
bins_for_gpio_bits[22]	auto[0]	auto[1]	233725	1			T22	1		T25	13178		T1	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	233902	1			T22	1		T25	13181		T1	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	5110564	1			T22	39		T23	338		T24	59
bins_for_gpio_bits[23]	auto[0]	auto[0]	7416656	1			T22	18		T23	369		T24	43
bins_for_gpio_bits[23]	auto[0]	auto[1]	233974	1			T22	3		T25	13171		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	234189	1			T22	3		T25	13171		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5107851	1			T22	32		T23	302		T24	66
bins_for_gpio_bits[24]	auto[0]	auto[0]	7412833	1			T22	5		T23	385		T24	42
bins_for_gpio_bits[24]	auto[0]	auto[1]	233727	1			T25	13331		T1	15		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	233927	1			T25	13332		T1	15		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	5112183	1			T22	51		T23	286		T24	67
bins_for_gpio_bits[25]	auto[0]	auto[0]	7418368	1			T22	14		T23	292		T24	48
bins_for_gpio_bits[25]	auto[0]	auto[1]	233088	1			T22	2		T25	13089		T1	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	233311	1			T22	2		T25	13090		T1	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	5107903	1			T22	38		T23	379		T24	61
bins_for_gpio_bits[26]	auto[0]	auto[0]	7415078	1			T22	9		T23	386		T24	60
bins_for_gpio_bits[26]	auto[0]	auto[1]	233561	1			T25	13290		T1	17		T11	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	233816	1			T25	13290		T1	17		T11	4
bins_for_gpio_bits[26]	auto[1]	auto[1]	5110215	1			T22	47		T23	285		T24	49
bins_for_gpio_bits[27]	auto[0]	auto[0]	7414336	1			T22	13		T23	378		T24	49
bins_for_gpio_bits[27]	auto[0]	auto[1]	233449	1			T22	1		T25	13186		T26	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	233670	1			T22	1		T25	13186		T26	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5111215	1			T22	41		T23	293		T24	60
bins_for_gpio_bits[28]	auto[0]	auto[0]	7423588	1			T22	12		T23	374		T24	65
bins_for_gpio_bits[28]	auto[0]	auto[1]	234113	1			T22	2		T25	13274		T1	20
bins_for_gpio_bits[28]	auto[1]	auto[0]	234336	1			T22	2		T25	13276		T1	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	5100633	1			T22	40		T23	297		T24	44
bins_for_gpio_bits[29]	auto[0]	auto[0]	7433371	1			T22	19		T23	291		T24	67
bins_for_gpio_bits[29]	auto[0]	auto[1]	232855	1			T22	3		T25	13337		T26	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	233063	1			T22	3		T25	13337		T26	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5093381	1			T22	31		T23	380		T24	42
bins_for_gpio_bits[30]	auto[0]	auto[0]	7410928	1			T22	11		T23	342		T24	61
bins_for_gpio_bits[30]	auto[0]	auto[1]	234043	1			T25	13243		T26	1		T1	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	234265	1			T25	13243		T26	1		T1	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	5113434	1			T22	45		T23	329		T24	48
bins_for_gpio_bits[31]	auto[0]	auto[0]	7423933	1			T22	16		T23	316		T24	52
bins_for_gpio_bits[31]	auto[0]	auto[1]	233354	1			T22	2		T25	13203		T1	23
bins_for_gpio_bits[31]	auto[1]	auto[0]	233533	1			T22	2		T25	13204		T1	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	5101850	1			T22	36		T23	355		T24	57