Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7544729 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
113 |
| auto[1] |
5631893 |
1 |
|
|
T24 |
93 |
|
T25 |
341990 |
|
T1 |
345 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12451658 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
724964 |
1 |
|
|
T24 |
5 |
|
T25 |
44505 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7563468 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
126 |
| auto[1] |
5613154 |
1 |
|
|
T24 |
80 |
|
T25 |
333534 |
|
T1 |
329 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2441198 |
1 |
|
|
T24 |
59 |
|
T25 |
142783 |
|
T1 |
147 |
| auto[1] |
auto[0] |
auto[1] |
362224 |
1 |
|
|
T24 |
5 |
|
T25 |
21856 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2446992 |
1 |
|
|
T24 |
16 |
|
T25 |
146246 |
|
T1 |
166 |
| auto[1] |
auto[1] |
auto[1] |
362740 |
1 |
|
|
T25 |
22649 |
|
T1 |
8 |
|
T14 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7510574 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
121 |
| auto[1] |
5666048 |
1 |
|
|
T24 |
85 |
|
T25 |
339276 |
|
T1 |
379 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446879 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
200 |
| auto[1] |
729743 |
1 |
|
|
T24 |
6 |
|
T25 |
47331 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7526146 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
98 |
| auto[1] |
5650476 |
1 |
|
|
T24 |
108 |
|
T25 |
351581 |
|
T1 |
291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2454366 |
1 |
|
|
T24 |
48 |
|
T25 |
156970 |
|
T1 |
158 |
| auto[1] |
auto[0] |
auto[1] |
363984 |
1 |
|
|
T24 |
3 |
|
T25 |
24328 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2466367 |
1 |
|
|
T24 |
54 |
|
T25 |
147280 |
|
T1 |
122 |
| auto[1] |
auto[1] |
auto[1] |
365759 |
1 |
|
|
T24 |
3 |
|
T25 |
23003 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7572858 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
100 |
| auto[1] |
5603764 |
1 |
|
|
T24 |
106 |
|
T25 |
344985 |
|
T1 |
352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12444575 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
732047 |
1 |
|
|
T24 |
5 |
|
T25 |
47022 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7513493 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
100 |
| auto[1] |
5663129 |
1 |
|
|
T24 |
106 |
|
T25 |
349010 |
|
T1 |
384 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2492581 |
1 |
|
|
T24 |
61 |
|
T25 |
152987 |
|
T1 |
187 |
| auto[1] |
auto[0] |
auto[1] |
371009 |
1 |
|
|
T24 |
2 |
|
T25 |
24172 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2438501 |
1 |
|
|
T24 |
40 |
|
T25 |
149001 |
|
T1 |
181 |
| auto[1] |
auto[1] |
auto[1] |
361038 |
1 |
|
|
T24 |
3 |
|
T25 |
22850 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7531015 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
144 |
| auto[1] |
5645607 |
1 |
|
|
T24 |
62 |
|
T25 |
334365 |
|
T1 |
364 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445311 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
731311 |
1 |
|
|
T24 |
5 |
|
T25 |
48592 |
|
T1 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7527454 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
115 |
| auto[1] |
5649168 |
1 |
|
|
T24 |
91 |
|
T25 |
357385 |
|
T1 |
480 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2465244 |
1 |
|
|
T24 |
63 |
|
T25 |
160335 |
|
T1 |
212 |
| auto[1] |
auto[0] |
auto[1] |
366611 |
1 |
|
|
T24 |
3 |
|
T25 |
25207 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2452613 |
1 |
|
|
T24 |
23 |
|
T25 |
148458 |
|
T1 |
247 |
| auto[1] |
auto[1] |
auto[1] |
364700 |
1 |
|
|
T24 |
2 |
|
T25 |
23385 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487353 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
115 |
| auto[1] |
5689269 |
1 |
|
|
T24 |
91 |
|
T25 |
337753 |
|
T1 |
328 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12442872 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
733750 |
1 |
|
|
T24 |
7 |
|
T25 |
45472 |
|
T1 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7506974 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
79 |
| auto[1] |
5669648 |
1 |
|
|
T24 |
127 |
|
T25 |
338333 |
|
T1 |
308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2446919 |
1 |
|
|
T24 |
54 |
|
T25 |
148645 |
|
T1 |
129 |
| auto[1] |
auto[0] |
auto[1] |
362903 |
1 |
|
|
T24 |
3 |
|
T25 |
23114 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2488979 |
1 |
|
|
T24 |
66 |
|
T25 |
144216 |
|
T1 |
164 |
| auto[1] |
auto[1] |
auto[1] |
370847 |
1 |
|
|
T24 |
4 |
|
T25 |
22358 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520711 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
149 |
| auto[1] |
5655911 |
1 |
|
|
T24 |
57 |
|
T25 |
345553 |
|
T1 |
229 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12453138 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
203 |
| auto[1] |
723484 |
1 |
|
|
T24 |
3 |
|
T25 |
45135 |
|
T1 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7562656 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
128 |
| auto[1] |
5613966 |
1 |
|
|
T24 |
78 |
|
T25 |
340452 |
|
T1 |
423 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2450993 |
1 |
|
|
T24 |
62 |
|
T25 |
147303 |
|
T1 |
270 |
| auto[1] |
auto[0] |
auto[1] |
361584 |
1 |
|
|
T24 |
2 |
|
T25 |
22567 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2439489 |
1 |
|
|
T24 |
13 |
|
T25 |
148014 |
|
T1 |
136 |
| auto[1] |
auto[1] |
auto[1] |
361900 |
1 |
|
|
T24 |
1 |
|
T25 |
22568 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7556154 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
117 |
| auto[1] |
5620468 |
1 |
|
|
T24 |
89 |
|
T25 |
346779 |
|
T1 |
427 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12449402 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
727220 |
1 |
|
|
T24 |
7 |
|
T25 |
45823 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7550817 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
63 |
| auto[1] |
5625805 |
1 |
|
|
T24 |
143 |
|
T25 |
341454 |
|
T1 |
233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2454360 |
1 |
|
|
T24 |
78 |
|
T25 |
148773 |
|
T1 |
101 |
| auto[1] |
auto[0] |
auto[1] |
363601 |
1 |
|
|
T24 |
6 |
|
T25 |
23207 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2444225 |
1 |
|
|
T24 |
58 |
|
T25 |
146858 |
|
T1 |
121 |
| auto[1] |
auto[1] |
auto[1] |
363619 |
1 |
|
|
T24 |
1 |
|
T25 |
22616 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7495150 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
94 |
| auto[1] |
5681472 |
1 |
|
|
T24 |
112 |
|
T25 |
359552 |
|
T1 |
393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12444220 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
203 |
| auto[1] |
732402 |
1 |
|
|
T24 |
3 |
|
T25 |
46580 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507318 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
158 |
| auto[1] |
5669304 |
1 |
|
|
T24 |
48 |
|
T25 |
347059 |
|
T1 |
226 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2446568 |
1 |
|
|
T24 |
18 |
|
T25 |
141474 |
|
T1 |
70 |
| auto[1] |
auto[0] |
auto[1] |
361834 |
1 |
|
|
T24 |
1 |
|
T25 |
21735 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2490334 |
1 |
|
|
T24 |
27 |
|
T25 |
159005 |
|
T1 |
145 |
| auto[1] |
auto[1] |
auto[1] |
370568 |
1 |
|
|
T24 |
2 |
|
T25 |
24845 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7550018 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
107 |
| auto[1] |
5626604 |
1 |
|
|
T24 |
99 |
|
T25 |
352862 |
|
T1 |
342 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445155 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
731467 |
1 |
|
|
T24 |
5 |
|
T25 |
44741 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7529095 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
106 |
| auto[1] |
5647527 |
1 |
|
|
T24 |
100 |
|
T25 |
334614 |
|
T1 |
308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2465943 |
1 |
|
|
T24 |
42 |
|
T25 |
143146 |
|
T1 |
156 |
| auto[1] |
auto[0] |
auto[1] |
367261 |
1 |
|
|
T24 |
3 |
|
T25 |
22068 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2450117 |
1 |
|
|
T24 |
53 |
|
T25 |
146727 |
|
T1 |
141 |
| auto[1] |
auto[1] |
auto[1] |
364206 |
1 |
|
|
T24 |
2 |
|
T25 |
22673 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7496886 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
101 |
| auto[1] |
5679736 |
1 |
|
|
T24 |
105 |
|
T25 |
354010 |
|
T1 |
320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12448169 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
728453 |
1 |
|
|
T24 |
5 |
|
T25 |
45051 |
|
T1 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7532877 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
118 |
| auto[1] |
5643745 |
1 |
|
|
T24 |
88 |
|
T25 |
336445 |
|
T1 |
428 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2436939 |
1 |
|
|
T24 |
37 |
|
T25 |
139824 |
|
T1 |
232 |
| auto[1] |
auto[0] |
auto[1] |
359810 |
1 |
|
|
T24 |
2 |
|
T25 |
21451 |
|
T1 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2478353 |
1 |
|
|
T24 |
46 |
|
T25 |
151570 |
|
T1 |
171 |
| auto[1] |
auto[1] |
auto[1] |
368643 |
1 |
|
|
T24 |
3 |
|
T25 |
23600 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7525302 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
141 |
| auto[1] |
5651320 |
1 |
|
|
T24 |
65 |
|
T25 |
344619 |
|
T1 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12442249 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
198 |
| auto[1] |
734373 |
1 |
|
|
T24 |
8 |
|
T25 |
47351 |
|
T1 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7505515 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
90 |
| auto[1] |
5671107 |
1 |
|
|
T24 |
116 |
|
T25 |
352034 |
|
T1 |
221 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2464295 |
1 |
|
|
T24 |
74 |
|
T25 |
153724 |
|
T1 |
99 |
| auto[1] |
auto[0] |
auto[1] |
365311 |
1 |
|
|
T24 |
6 |
|
T25 |
23727 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2472439 |
1 |
|
|
T24 |
34 |
|
T25 |
150959 |
|
T1 |
113 |
| auto[1] |
auto[1] |
auto[1] |
369062 |
1 |
|
|
T24 |
2 |
|
T25 |
23624 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7550533 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
161 |
| auto[1] |
5626089 |
1 |
|
|
T24 |
45 |
|
T25 |
344211 |
|
T1 |
313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12443814 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
202 |
| auto[1] |
732808 |
1 |
|
|
T24 |
4 |
|
T25 |
46084 |
|
T1 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7511048 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
114 |
| auto[1] |
5665574 |
1 |
|
|
T24 |
92 |
|
T25 |
345492 |
|
T1 |
316 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2472604 |
1 |
|
|
T24 |
60 |
|
T25 |
146224 |
|
T1 |
161 |
| auto[1] |
auto[0] |
auto[1] |
368389 |
1 |
|
|
T24 |
2 |
|
T25 |
22547 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2460162 |
1 |
|
|
T24 |
28 |
|
T25 |
153184 |
|
T1 |
140 |
| auto[1] |
auto[1] |
auto[1] |
364419 |
1 |
|
|
T24 |
2 |
|
T25 |
23537 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7533107 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
144 |
| auto[1] |
5643515 |
1 |
|
|
T24 |
62 |
|
T25 |
351729 |
|
T1 |
251 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12444096 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
202 |
| auto[1] |
732526 |
1 |
|
|
T24 |
4 |
|
T25 |
45947 |
|
T1 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7511494 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
128 |
| auto[1] |
5665128 |
1 |
|
|
T24 |
78 |
|
T25 |
343715 |
|
T1 |
299 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2475805 |
1 |
|
|
T24 |
54 |
|
T25 |
148189 |
|
T1 |
147 |
| auto[1] |
auto[0] |
auto[1] |
367780 |
1 |
|
|
T24 |
4 |
|
T25 |
22956 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2456797 |
1 |
|
|
T24 |
20 |
|
T25 |
149579 |
|
T1 |
143 |
| auto[1] |
auto[1] |
auto[1] |
364746 |
1 |
|
|
T25 |
22991 |
|
T1 |
4 |
|
T15 |
934 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7511127 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
99 |
| auto[1] |
5665495 |
1 |
|
|
T24 |
107 |
|
T25 |
338270 |
|
T1 |
304 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446396 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
196 |
| auto[1] |
730226 |
1 |
|
|
T24 |
10 |
|
T25 |
45073 |
|
T1 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7519148 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
73 |
| auto[1] |
5657474 |
1 |
|
|
T24 |
133 |
|
T25 |
336999 |
|
T1 |
362 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2450127 |
1 |
|
|
T24 |
63 |
|
T25 |
147789 |
|
T1 |
206 |
| auto[1] |
auto[0] |
auto[1] |
362534 |
1 |
|
|
T24 |
6 |
|
T25 |
22978 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2477121 |
1 |
|
|
T24 |
60 |
|
T25 |
144137 |
|
T1 |
142 |
| auto[1] |
auto[1] |
auto[1] |
367692 |
1 |
|
|
T24 |
4 |
|
T25 |
22095 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7545916 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
138 |
| auto[1] |
5630706 |
1 |
|
|
T24 |
68 |
|
T25 |
355260 |
|
T1 |
339 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12449534 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
198 |
| auto[1] |
727088 |
1 |
|
|
T24 |
8 |
|
T25 |
47056 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7545213 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
81 |
| auto[1] |
5631409 |
1 |
|
|
T24 |
125 |
|
T25 |
348865 |
|
T1 |
232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2466920 |
1 |
|
|
T24 |
86 |
|
T25 |
149999 |
|
T1 |
112 |
| auto[1] |
auto[0] |
auto[1] |
366148 |
1 |
|
|
T24 |
6 |
|
T25 |
23601 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2437401 |
1 |
|
|
T24 |
31 |
|
T25 |
151810 |
|
T1 |
110 |
| auto[1] |
auto[1] |
auto[1] |
360940 |
1 |
|
|
T24 |
2 |
|
T25 |
23455 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520885 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
77 |
| auto[1] |
5655737 |
1 |
|
|
T24 |
129 |
|
T25 |
354930 |
|
T1 |
275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446525 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
730097 |
1 |
|
|
T24 |
7 |
|
T25 |
47141 |
|
T1 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7527231 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
80 |
| auto[1] |
5649391 |
1 |
|
|
T24 |
126 |
|
T25 |
352929 |
|
T1 |
301 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2472654 |
1 |
|
|
T24 |
37 |
|
T25 |
147970 |
|
T1 |
141 |
| auto[1] |
auto[0] |
auto[1] |
367090 |
1 |
|
|
T24 |
1 |
|
T25 |
22627 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2446640 |
1 |
|
|
T24 |
82 |
|
T25 |
157818 |
|
T1 |
143 |
| auto[1] |
auto[1] |
auto[1] |
363007 |
1 |
|
|
T24 |
6 |
|
T25 |
24514 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7511931 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
132 |
| auto[1] |
5664691 |
1 |
|
|
T24 |
74 |
|
T25 |
350926 |
|
T1 |
311 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445990 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
195 |
| auto[1] |
730632 |
1 |
|
|
T24 |
11 |
|
T25 |
45767 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7516567 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
71 |
| auto[1] |
5660055 |
1 |
|
|
T24 |
135 |
|
T25 |
340699 |
|
T1 |
381 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2464162 |
1 |
|
|
T24 |
74 |
|
T25 |
140682 |
|
T1 |
178 |
| auto[1] |
auto[0] |
auto[1] |
364876 |
1 |
|
|
T24 |
5 |
|
T25 |
21723 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2465261 |
1 |
|
|
T24 |
50 |
|
T25 |
154250 |
|
T1 |
185 |
| auto[1] |
auto[1] |
auto[1] |
365756 |
1 |
|
|
T24 |
6 |
|
T25 |
24044 |
|
T1 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503839 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
171 |
| auto[1] |
5672783 |
1 |
|
|
T24 |
35 |
|
T25 |
356713 |
|
T1 |
386 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12449265 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
200 |
| auto[1] |
727357 |
1 |
|
|
T24 |
6 |
|
T25 |
47130 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7536553 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
103 |
| auto[1] |
5640069 |
1 |
|
|
T24 |
103 |
|
T25 |
348839 |
|
T1 |
481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2456367 |
1 |
|
|
T24 |
69 |
|
T25 |
143123 |
|
T1 |
212 |
| auto[1] |
auto[0] |
auto[1] |
364177 |
1 |
|
|
T24 |
5 |
|
T25 |
21965 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2456345 |
1 |
|
|
T24 |
28 |
|
T25 |
158586 |
|
T1 |
253 |
| auto[1] |
auto[1] |
auto[1] |
363180 |
1 |
|
|
T24 |
1 |
|
T25 |
25165 |
|
T1 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7529727 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
120 |
| auto[1] |
5646895 |
1 |
|
|
T24 |
86 |
|
T25 |
341931 |
|
T1 |
398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12444429 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
732193 |
1 |
|
|
T24 |
5 |
|
T25 |
44806 |
|
T1 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7514895 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
131 |
| auto[1] |
5661727 |
1 |
|
|
T24 |
75 |
|
T25 |
336465 |
|
T1 |
369 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2467734 |
1 |
|
|
T24 |
27 |
|
T25 |
149341 |
|
T1 |
133 |
| auto[1] |
auto[0] |
auto[1] |
367369 |
1 |
|
|
T24 |
2 |
|
T25 |
22955 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2461800 |
1 |
|
|
T24 |
43 |
|
T25 |
142318 |
|
T1 |
222 |
| auto[1] |
auto[1] |
auto[1] |
364824 |
1 |
|
|
T24 |
3 |
|
T25 |
21851 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |