Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7569064 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
127 |
| auto[1] |
5607558 |
1 |
|
|
T24 |
79 |
|
T25 |
336074 |
|
T1 |
216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12444085 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
200 |
| auto[1] |
732537 |
1 |
|
|
T24 |
6 |
|
T25 |
46228 |
|
T1 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7517381 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
119 |
| auto[1] |
5659241 |
1 |
|
|
T24 |
87 |
|
T25 |
346544 |
|
T1 |
297 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2484844 |
1 |
|
|
T24 |
41 |
|
T25 |
153071 |
|
T1 |
215 |
| auto[1] |
auto[0] |
auto[1] |
369010 |
1 |
|
|
T24 |
5 |
|
T25 |
23699 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2441860 |
1 |
|
|
T24 |
40 |
|
T25 |
147245 |
|
T1 |
69 |
| auto[1] |
auto[1] |
auto[1] |
363527 |
1 |
|
|
T24 |
1 |
|
T25 |
22529 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |