Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7569663 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
128 |
| auto[1] |
5606959 |
1 |
|
|
T24 |
78 |
|
T25 |
343869 |
|
T1 |
309 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12447200 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
200 |
| auto[1] |
729422 |
1 |
|
|
T24 |
6 |
|
T25 |
46078 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7533339 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
81 |
| auto[1] |
5643283 |
1 |
|
|
T24 |
125 |
|
T25 |
343961 |
|
T1 |
344 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2480064 |
1 |
|
|
T24 |
70 |
|
T25 |
150444 |
|
T1 |
159 |
| auto[1] |
auto[0] |
auto[1] |
367296 |
1 |
|
|
T24 |
2 |
|
T25 |
23482 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2433797 |
1 |
|
|
T24 |
49 |
|
T25 |
147439 |
|
T1 |
167 |
| auto[1] |
auto[1] |
auto[1] |
362126 |
1 |
|
|
T24 |
4 |
|
T25 |
22596 |
|
T1 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |