Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7537399 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
134 |
| auto[1] |
5639223 |
1 |
|
|
T24 |
72 |
|
T25 |
347247 |
|
T1 |
393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446479 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
730143 |
1 |
|
|
T24 |
7 |
|
T25 |
46364 |
|
T1 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7524250 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
107 |
| auto[1] |
5652372 |
1 |
|
|
T24 |
99 |
|
T25 |
345935 |
|
T1 |
306 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2469972 |
1 |
|
|
T24 |
70 |
|
T25 |
146643 |
|
T1 |
124 |
| auto[1] |
auto[0] |
auto[1] |
367048 |
1 |
|
|
T24 |
4 |
|
T25 |
22540 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2452257 |
1 |
|
|
T24 |
22 |
|
T25 |
152928 |
|
T1 |
165 |
| auto[1] |
auto[1] |
auto[1] |
363095 |
1 |
|
|
T24 |
3 |
|
T25 |
23824 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |