Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7534221 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
97 |
| auto[1] |
5642401 |
1 |
|
|
T24 |
109 |
|
T25 |
356473 |
|
T1 |
335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12450541 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
202 |
| auto[1] |
726081 |
1 |
|
|
T24 |
4 |
|
T25 |
45144 |
|
T1 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7550293 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
122 |
| auto[1] |
5626329 |
1 |
|
|
T24 |
84 |
|
T25 |
339441 |
|
T1 |
275 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2475517 |
1 |
|
|
T24 |
47 |
|
T25 |
142363 |
|
T1 |
108 |
| auto[1] |
auto[0] |
auto[1] |
366574 |
1 |
|
|
T24 |
2 |
|
T25 |
21402 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2424731 |
1 |
|
|
T24 |
33 |
|
T25 |
151934 |
|
T1 |
158 |
| auto[1] |
auto[1] |
auto[1] |
359507 |
1 |
|
|
T24 |
2 |
|
T25 |
23742 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |