Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7489515 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
102 |
| auto[1] |
5687107 |
1 |
|
|
T24 |
104 |
|
T25 |
346858 |
|
T1 |
420 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446997 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
201 |
| auto[1] |
729625 |
1 |
|
|
T24 |
5 |
|
T25 |
45942 |
|
T1 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7525626 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
140 |
| auto[1] |
5650996 |
1 |
|
|
T24 |
66 |
|
T25 |
343423 |
|
T1 |
346 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2461289 |
1 |
|
|
T24 |
30 |
|
T25 |
148969 |
|
T1 |
153 |
| auto[1] |
auto[0] |
auto[1] |
364915 |
1 |
|
|
T24 |
3 |
|
T25 |
23012 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2460082 |
1 |
|
|
T24 |
31 |
|
T25 |
148512 |
|
T1 |
178 |
| auto[1] |
auto[1] |
auto[1] |
364710 |
1 |
|
|
T24 |
2 |
|
T25 |
22930 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |