Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7544729 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
113 |
| auto[1] |
5631893 |
1 |
|
|
T24 |
93 |
|
T25 |
341990 |
|
T1 |
345 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10808861 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
127 |
| auto[1] |
2367761 |
1 |
|
|
T24 |
79 |
|
T25 |
136871 |
|
T1 |
261 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7536128 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
52 |
| auto[1] |
5640494 |
1 |
|
|
T24 |
154 |
|
T25 |
356087 |
|
T1 |
332 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1645661 |
1 |
|
|
T24 |
38 |
|
T25 |
115801 |
|
T1 |
45 |
| auto[1] |
auto[0] |
auto[1] |
1192178 |
1 |
|
|
T24 |
46 |
|
T25 |
70918 |
|
T1 |
120 |
| auto[1] |
auto[1] |
auto[0] |
1627072 |
1 |
|
|
T24 |
37 |
|
T25 |
103415 |
|
T1 |
26 |
| auto[1] |
auto[1] |
auto[1] |
1175583 |
1 |
|
|
T24 |
33 |
|
T25 |
65953 |
|
T1 |
141 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |