Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7510574 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
121 |
| auto[1] |
5666048 |
1 |
|
|
T24 |
85 |
|
T25 |
339276 |
|
T1 |
379 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10807718 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
134 |
| auto[1] |
2368904 |
1 |
|
|
T24 |
72 |
|
T25 |
134749 |
|
T1 |
181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7546531 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
86 |
| auto[1] |
5630091 |
1 |
|
|
T24 |
120 |
|
T25 |
351670 |
|
T1 |
251 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1623855 |
1 |
|
|
T24 |
34 |
|
T25 |
112823 |
|
T1 |
34 |
| auto[1] |
auto[0] |
auto[1] |
1179263 |
1 |
|
|
T24 |
37 |
|
T25 |
68804 |
|
T1 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1637332 |
1 |
|
|
T24 |
14 |
|
T25 |
104098 |
|
T1 |
36 |
| auto[1] |
auto[1] |
auto[1] |
1189641 |
1 |
|
|
T24 |
35 |
|
T25 |
65945 |
|
T1 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |