Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7572858 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
100 |
| auto[1] |
5603764 |
1 |
|
|
T24 |
106 |
|
T25 |
344985 |
|
T1 |
352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10796405 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
131 |
| auto[1] |
2380217 |
1 |
|
|
T24 |
75 |
|
T25 |
132669 |
|
T1 |
354 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7513386 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
90 |
| auto[1] |
5663236 |
1 |
|
|
T24 |
116 |
|
T25 |
345862 |
|
T1 |
443 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1654880 |
1 |
|
|
T24 |
12 |
|
T25 |
105869 |
|
T1 |
37 |
| auto[1] |
auto[0] |
auto[1] |
1200811 |
1 |
|
|
T24 |
40 |
|
T25 |
65888 |
|
T1 |
167 |
| auto[1] |
auto[1] |
auto[0] |
1628139 |
1 |
|
|
T24 |
29 |
|
T25 |
107324 |
|
T1 |
52 |
| auto[1] |
auto[1] |
auto[1] |
1179406 |
1 |
|
|
T24 |
35 |
|
T25 |
66781 |
|
T1 |
187 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |