Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7531015 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
144 |
| auto[1] |
5645607 |
1 |
|
|
T24 |
62 |
|
T25 |
334365 |
|
T1 |
364 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10809692 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
172 |
| auto[1] |
2366930 |
1 |
|
|
T24 |
34 |
|
T25 |
129976 |
|
T1 |
198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7553579 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
115 |
| auto[1] |
5623043 |
1 |
|
|
T24 |
91 |
|
T25 |
338237 |
|
T1 |
247 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1617421 |
1 |
|
|
T24 |
41 |
|
T25 |
104872 |
|
T1 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1181199 |
1 |
|
|
T24 |
25 |
|
T25 |
64823 |
|
T1 |
74 |
| auto[1] |
auto[1] |
auto[0] |
1638692 |
1 |
|
|
T24 |
16 |
|
T25 |
103389 |
|
T1 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1185731 |
1 |
|
|
T24 |
9 |
|
T25 |
65153 |
|
T1 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |