Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487353 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
115 |
| auto[1] |
5689269 |
1 |
|
|
T24 |
91 |
|
T25 |
337753 |
|
T1 |
328 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10796585 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
141 |
| auto[1] |
2380037 |
1 |
|
|
T24 |
65 |
|
T25 |
133428 |
|
T1 |
204 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7517434 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
98 |
| auto[1] |
5659188 |
1 |
|
|
T24 |
108 |
|
T25 |
343745 |
|
T1 |
264 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1623163 |
1 |
|
|
T24 |
23 |
|
T25 |
108015 |
|
T1 |
39 |
| auto[1] |
auto[0] |
auto[1] |
1185295 |
1 |
|
|
T24 |
25 |
|
T25 |
68048 |
|
T1 |
98 |
| auto[1] |
auto[1] |
auto[0] |
1655988 |
1 |
|
|
T24 |
20 |
|
T25 |
102302 |
|
T1 |
21 |
| auto[1] |
auto[1] |
auto[1] |
1194742 |
1 |
|
|
T24 |
40 |
|
T25 |
65380 |
|
T1 |
106 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |