Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7533995 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
94 |
| auto[1] |
5642627 |
1 |
|
|
T24 |
112 |
|
T25 |
345336 |
|
T1 |
379 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12449345 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
200 |
| auto[1] |
727277 |
1 |
|
|
T24 |
6 |
|
T25 |
43673 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7544590 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
121 |
| auto[1] |
5632032 |
1 |
|
|
T24 |
85 |
|
T25 |
329571 |
|
T1 |
349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2464142 |
1 |
|
|
T24 |
30 |
|
T25 |
144433 |
|
T1 |
135 |
| auto[1] |
auto[0] |
auto[1] |
366255 |
1 |
|
|
T24 |
2 |
|
T25 |
22074 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2440613 |
1 |
|
|
T24 |
49 |
|
T25 |
141465 |
|
T1 |
196 |
| auto[1] |
auto[1] |
auto[1] |
361022 |
1 |
|
|
T24 |
4 |
|
T25 |
21599 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |