Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520711 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
149 |
| auto[1] |
5655911 |
1 |
|
|
T24 |
57 |
|
T25 |
345553 |
|
T1 |
229 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10781141 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
168 |
| auto[1] |
2395481 |
1 |
|
|
T24 |
38 |
|
T25 |
133547 |
|
T1 |
265 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479097 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
69 |
| auto[1] |
5697525 |
1 |
|
|
T24 |
137 |
|
T25 |
345759 |
|
T1 |
321 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1649546 |
1 |
|
|
T24 |
68 |
|
T25 |
106120 |
|
T1 |
43 |
| auto[1] |
auto[0] |
auto[1] |
1193409 |
1 |
|
|
T24 |
23 |
|
T25 |
66296 |
|
T1 |
168 |
| auto[1] |
auto[1] |
auto[0] |
1652498 |
1 |
|
|
T24 |
31 |
|
T25 |
106092 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1202072 |
1 |
|
|
T24 |
15 |
|
T25 |
67251 |
|
T1 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |