Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7556154 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
117 |
| auto[1] |
5620468 |
1 |
|
|
T24 |
89 |
|
T25 |
346779 |
|
T1 |
427 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10804818 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
183 |
| auto[1] |
2371804 |
1 |
|
|
T24 |
23 |
|
T25 |
132117 |
|
T1 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7535716 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
98 |
| auto[1] |
5640906 |
1 |
|
|
T24 |
108 |
|
T25 |
343990 |
|
T1 |
313 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1638486 |
1 |
|
|
T24 |
46 |
|
T25 |
104251 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1188530 |
1 |
|
|
T24 |
14 |
|
T25 |
65752 |
|
T1 |
98 |
| auto[1] |
auto[1] |
auto[0] |
1630616 |
1 |
|
|
T24 |
39 |
|
T25 |
107622 |
|
T1 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1183274 |
1 |
|
|
T24 |
9 |
|
T25 |
66365 |
|
T1 |
158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |