Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7495150 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
94 |
| auto[1] |
5681472 |
1 |
|
|
T24 |
112 |
|
T25 |
359552 |
|
T1 |
393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10814917 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
176 |
| auto[1] |
2361705 |
1 |
|
|
T24 |
30 |
|
T25 |
133504 |
|
T1 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7565071 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
108 |
| auto[1] |
5611551 |
1 |
|
|
T24 |
98 |
|
T25 |
347291 |
|
T1 |
186 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1611954 |
1 |
|
|
T24 |
32 |
|
T25 |
99842 |
|
T1 |
42 |
| auto[1] |
auto[0] |
auto[1] |
1175058 |
1 |
|
|
T24 |
15 |
|
T25 |
63658 |
|
T1 |
48 |
| auto[1] |
auto[1] |
auto[0] |
1637892 |
1 |
|
|
T24 |
36 |
|
T25 |
113945 |
|
T1 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1186647 |
1 |
|
|
T24 |
15 |
|
T25 |
69846 |
|
T1 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |