Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7496886 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
101 |
| auto[1] |
5679736 |
1 |
|
|
T24 |
105 |
|
T25 |
354010 |
|
T1 |
320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10813987 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
150 |
| auto[1] |
2362635 |
1 |
|
|
T24 |
56 |
|
T25 |
132546 |
|
T1 |
207 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7560024 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
113 |
| auto[1] |
5616598 |
1 |
|
|
T24 |
93 |
|
T25 |
340074 |
|
T1 |
282 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1606335 |
1 |
|
|
T24 |
11 |
|
T25 |
101004 |
|
T1 |
29 |
| auto[1] |
auto[0] |
auto[1] |
1173906 |
1 |
|
|
T24 |
23 |
|
T25 |
64581 |
|
T1 |
93 |
| auto[1] |
auto[1] |
auto[0] |
1647628 |
1 |
|
|
T24 |
26 |
|
T25 |
106524 |
|
T1 |
46 |
| auto[1] |
auto[1] |
auto[1] |
1188729 |
1 |
|
|
T24 |
33 |
|
T25 |
67965 |
|
T1 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |