Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7525302 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
141 |
| auto[1] |
5651320 |
1 |
|
|
T24 |
65 |
|
T25 |
344619 |
|
T1 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10805543 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
154 |
| auto[1] |
2371079 |
1 |
|
|
T24 |
52 |
|
T25 |
130367 |
|
T1 |
334 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7537090 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
120 |
| auto[1] |
5639532 |
1 |
|
|
T24 |
86 |
|
T25 |
337086 |
|
T1 |
461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1635426 |
1 |
|
|
T24 |
24 |
|
T25 |
101147 |
|
T1 |
77 |
| auto[1] |
auto[0] |
auto[1] |
1183284 |
1 |
|
|
T24 |
29 |
|
T25 |
62900 |
|
T1 |
145 |
| auto[1] |
auto[1] |
auto[0] |
1633027 |
1 |
|
|
T24 |
10 |
|
T25 |
105572 |
|
T1 |
50 |
| auto[1] |
auto[1] |
auto[1] |
1187795 |
1 |
|
|
T24 |
23 |
|
T25 |
67467 |
|
T1 |
189 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |