Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7550533 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
161 |
| auto[1] |
5626089 |
1 |
|
|
T24 |
45 |
|
T25 |
344211 |
|
T1 |
313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10801703 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
138 |
| auto[1] |
2374919 |
1 |
|
|
T24 |
68 |
|
T25 |
128561 |
|
T1 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7529332 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
73 |
| auto[1] |
5647290 |
1 |
|
|
T24 |
133 |
|
T25 |
333235 |
|
T1 |
198 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1643947 |
1 |
|
|
T24 |
52 |
|
T25 |
104020 |
|
T1 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1190905 |
1 |
|
|
T24 |
49 |
|
T25 |
64695 |
|
T1 |
99 |
| auto[1] |
auto[1] |
auto[0] |
1628424 |
1 |
|
|
T24 |
13 |
|
T25 |
100654 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1184014 |
1 |
|
|
T24 |
19 |
|
T25 |
63866 |
|
T1 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |