Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7533107 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
144 |
| auto[1] |
5643515 |
1 |
|
|
T24 |
62 |
|
T25 |
351729 |
|
T1 |
251 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10804921 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
167 |
| auto[1] |
2371701 |
1 |
|
|
T24 |
39 |
|
T25 |
132643 |
|
T1 |
181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7538171 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
125 |
| auto[1] |
5638451 |
1 |
|
|
T24 |
81 |
|
T25 |
345265 |
|
T1 |
223 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1632922 |
1 |
|
|
T24 |
38 |
|
T25 |
103108 |
|
T1 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1189745 |
1 |
|
|
T24 |
33 |
|
T25 |
65333 |
|
T1 |
105 |
| auto[1] |
auto[1] |
auto[0] |
1633828 |
1 |
|
|
T24 |
4 |
|
T25 |
109514 |
|
T1 |
16 |
| auto[1] |
auto[1] |
auto[1] |
1181956 |
1 |
|
|
T24 |
6 |
|
T25 |
67310 |
|
T1 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |