Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7545916 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
138 |
| auto[1] |
5630706 |
1 |
|
|
T24 |
68 |
|
T25 |
355260 |
|
T1 |
339 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10799709 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
168 |
| auto[1] |
2376913 |
1 |
|
|
T24 |
38 |
|
T25 |
133760 |
|
T1 |
232 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7525790 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
117 |
| auto[1] |
5650832 |
1 |
|
|
T24 |
89 |
|
T25 |
346987 |
|
T1 |
307 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1642026 |
1 |
|
|
T24 |
30 |
|
T25 |
103691 |
|
T1 |
45 |
| auto[1] |
auto[0] |
auto[1] |
1194752 |
1 |
|
|
T24 |
21 |
|
T25 |
65775 |
|
T1 |
141 |
| auto[1] |
auto[1] |
auto[0] |
1631893 |
1 |
|
|
T24 |
21 |
|
T25 |
109536 |
|
T1 |
30 |
| auto[1] |
auto[1] |
auto[1] |
1182161 |
1 |
|
|
T24 |
17 |
|
T25 |
67985 |
|
T1 |
91 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |