Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7519513 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
152 |
| auto[1] |
5657109 |
1 |
|
|
T24 |
54 |
|
T25 |
338292 |
|
T1 |
366 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12450407 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
726215 |
1 |
|
|
T24 |
7 |
|
T25 |
45937 |
|
T1 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7552099 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
110 |
| auto[1] |
5624523 |
1 |
|
|
T24 |
96 |
|
T25 |
344418 |
|
T1 |
311 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2450531 |
1 |
|
|
T24 |
69 |
|
T25 |
157477 |
|
T1 |
139 |
| auto[1] |
auto[0] |
auto[1] |
363245 |
1 |
|
|
T24 |
6 |
|
T25 |
24338 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2447777 |
1 |
|
|
T24 |
20 |
|
T25 |
141004 |
|
T1 |
151 |
| auto[1] |
auto[1] |
auto[1] |
362970 |
1 |
|
|
T24 |
1 |
|
T25 |
21599 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |