Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520885 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
77 |
| auto[1] |
5655737 |
1 |
|
|
T24 |
129 |
|
T25 |
354930 |
|
T1 |
275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10802570 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
163 |
| auto[1] |
2374052 |
1 |
|
|
T24 |
43 |
|
T25 |
136690 |
|
T1 |
146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7552938 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
120 |
| auto[1] |
5623684 |
1 |
|
|
T24 |
86 |
|
T25 |
351520 |
|
T1 |
189 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1621337 |
1 |
|
|
T24 |
14 |
|
T25 |
106188 |
|
T1 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1181627 |
1 |
|
|
T24 |
16 |
|
T25 |
67408 |
|
T1 |
76 |
| auto[1] |
auto[1] |
auto[0] |
1628295 |
1 |
|
|
T24 |
29 |
|
T25 |
108642 |
|
T1 |
31 |
| auto[1] |
auto[1] |
auto[1] |
1192425 |
1 |
|
|
T24 |
27 |
|
T25 |
69282 |
|
T1 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |