Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7511931 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
132 |
| auto[1] |
5664691 |
1 |
|
|
T24 |
74 |
|
T25 |
350926 |
|
T1 |
311 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10811826 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
162 |
| auto[1] |
2364796 |
1 |
|
|
T24 |
44 |
|
T25 |
137726 |
|
T1 |
244 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7547040 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
128 |
| auto[1] |
5629582 |
1 |
|
|
T24 |
78 |
|
T25 |
355199 |
|
T1 |
332 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1631480 |
1 |
|
|
T24 |
21 |
|
T25 |
109140 |
|
T1 |
48 |
| auto[1] |
auto[0] |
auto[1] |
1181415 |
1 |
|
|
T24 |
21 |
|
T25 |
68674 |
|
T1 |
116 |
| auto[1] |
auto[1] |
auto[0] |
1633306 |
1 |
|
|
T24 |
13 |
|
T25 |
108333 |
|
T1 |
40 |
| auto[1] |
auto[1] |
auto[1] |
1183381 |
1 |
|
|
T24 |
23 |
|
T25 |
69052 |
|
T1 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |