Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503839 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
171 |
| auto[1] |
5672783 |
1 |
|
|
T24 |
35 |
|
T25 |
356713 |
|
T1 |
386 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10813190 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
160 |
| auto[1] |
2363432 |
1 |
|
|
T24 |
46 |
|
T25 |
131221 |
|
T1 |
276 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7552649 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
108 |
| auto[1] |
5623973 |
1 |
|
|
T24 |
98 |
|
T25 |
342354 |
|
T1 |
361 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1625011 |
1 |
|
|
T24 |
37 |
|
T25 |
103002 |
|
T1 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1180879 |
1 |
|
|
T24 |
37 |
|
T25 |
63619 |
|
T1 |
124 |
| auto[1] |
auto[1] |
auto[0] |
1635530 |
1 |
|
|
T24 |
15 |
|
T25 |
108131 |
|
T1 |
67 |
| auto[1] |
auto[1] |
auto[1] |
1182553 |
1 |
|
|
T24 |
9 |
|
T25 |
67602 |
|
T1 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |