Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7551419 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
134 |
| auto[1] |
5625203 |
1 |
|
|
T24 |
72 |
|
T25 |
348039 |
|
T1 |
289 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12451403 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
202 |
| auto[1] |
725219 |
1 |
|
|
T24 |
4 |
|
T25 |
46882 |
|
T1 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7560700 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
124 |
| auto[1] |
5615922 |
1 |
|
|
T24 |
82 |
|
T25 |
345775 |
|
T1 |
244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2465519 |
1 |
|
|
T24 |
52 |
|
T25 |
150569 |
|
T1 |
148 |
| auto[1] |
auto[0] |
auto[1] |
364663 |
1 |
|
|
T24 |
4 |
|
T25 |
23393 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2425184 |
1 |
|
|
T24 |
26 |
|
T25 |
148324 |
|
T1 |
83 |
| auto[1] |
auto[1] |
auto[1] |
360556 |
1 |
|
|
T25 |
23489 |
|
T1 |
6 |
|
T15 |
808 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |