Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7498265 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
120 |
| auto[1] |
5678357 |
1 |
|
|
T24 |
86 |
|
T25 |
350223 |
|
T1 |
317 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12448496 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
728126 |
1 |
|
|
T24 |
7 |
|
T25 |
47388 |
|
T1 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7535819 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
114 |
| auto[1] |
5640803 |
1 |
|
|
T24 |
92 |
|
T25 |
353443 |
|
T1 |
351 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2451786 |
1 |
|
|
T24 |
56 |
|
T25 |
149196 |
|
T1 |
180 |
| auto[1] |
auto[0] |
auto[1] |
363073 |
1 |
|
|
T24 |
4 |
|
T25 |
22953 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2460891 |
1 |
|
|
T24 |
29 |
|
T25 |
156859 |
|
T1 |
150 |
| auto[1] |
auto[1] |
auto[1] |
365053 |
1 |
|
|
T24 |
3 |
|
T25 |
24435 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |