Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7574164 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
107 |
| auto[1] |
5602458 |
1 |
|
|
T24 |
99 |
|
T25 |
345805 |
|
T1 |
222 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12448798 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
727824 |
1 |
|
|
T24 |
7 |
|
T25 |
46351 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7540112 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
103 |
| auto[1] |
5636510 |
1 |
|
|
T24 |
103 |
|
T25 |
345585 |
|
T1 |
227 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2469588 |
1 |
|
|
T24 |
59 |
|
T25 |
150779 |
|
T1 |
148 |
| auto[1] |
auto[0] |
auto[1] |
365838 |
1 |
|
|
T24 |
4 |
|
T25 |
23192 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2439098 |
1 |
|
|
T24 |
37 |
|
T25 |
148455 |
|
T1 |
72 |
| auto[1] |
auto[1] |
auto[1] |
361986 |
1 |
|
|
T24 |
3 |
|
T25 |
23159 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |