Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7516090 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
95 |
| auto[1] |
5660532 |
1 |
|
|
T24 |
111 |
|
T25 |
353061 |
|
T1 |
304 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446916 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
729706 |
1 |
|
|
T24 |
7 |
|
T25 |
46487 |
|
T1 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7529297 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
67 |
| auto[1] |
5647325 |
1 |
|
|
T24 |
139 |
|
T25 |
347955 |
|
T1 |
255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2457224 |
1 |
|
|
T24 |
59 |
|
T25 |
147931 |
|
T1 |
102 |
| auto[1] |
auto[0] |
auto[1] |
363577 |
1 |
|
|
T24 |
4 |
|
T25 |
22846 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2460395 |
1 |
|
|
T24 |
73 |
|
T25 |
153537 |
|
T1 |
141 |
| auto[1] |
auto[1] |
auto[1] |
366129 |
1 |
|
|
T24 |
3 |
|
T25 |
23641 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |