Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7536526 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
109 |
| auto[1] |
5640096 |
1 |
|
|
T24 |
97 |
|
T25 |
343961 |
|
T1 |
270 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445500 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
204 |
| auto[1] |
731122 |
1 |
|
|
T24 |
2 |
|
T25 |
46140 |
|
T1 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7523872 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
125 |
| auto[1] |
5652750 |
1 |
|
|
T24 |
81 |
|
T25 |
343772 |
|
T1 |
333 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2459253 |
1 |
|
|
T24 |
43 |
|
T25 |
148974 |
|
T1 |
211 |
| auto[1] |
auto[0] |
auto[1] |
365551 |
1 |
|
|
T25 |
23013 |
|
T1 |
12 |
|
T15 |
741 |
| auto[1] |
auto[1] |
auto[0] |
2462375 |
1 |
|
|
T24 |
36 |
|
T25 |
148658 |
|
T1 |
105 |
| auto[1] |
auto[1] |
auto[1] |
365571 |
1 |
|
|
T24 |
2 |
|
T25 |
23127 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |