Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7540374 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
134 |
| auto[1] |
5636248 |
1 |
|
|
T24 |
72 |
|
T25 |
334543 |
|
T1 |
236 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12447082 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
199 |
| auto[1] |
729540 |
1 |
|
|
T24 |
7 |
|
T25 |
46571 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7534139 |
1 |
|
|
T22 |
31 |
|
T23 |
671 |
|
T24 |
103 |
| auto[1] |
5642483 |
1 |
|
|
T24 |
103 |
|
T25 |
348457 |
|
T1 |
260 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2465522 |
1 |
|
|
T24 |
63 |
|
T25 |
157295 |
|
T1 |
176 |
| auto[1] |
auto[0] |
auto[1] |
365274 |
1 |
|
|
T24 |
6 |
|
T25 |
24640 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2447421 |
1 |
|
|
T24 |
33 |
|
T25 |
144591 |
|
T1 |
68 |
| auto[1] |
auto[1] |
auto[1] |
364266 |
1 |
|
|
T24 |
1 |
|
T25 |
21931 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |